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Merge tag 'pull-riscv-to-apply-20241107' of https://github.com/alistair23/qemu into staging
RISC-V PR for 9.2 * Fix broken SiFive UART on big endian hosts * Fix IOMMU Coverity issues * Improve the performance of vector unit-stride/whole register ld/st instructions * Update kvm exts to Linux v6.11 * Convert the RV32-on-RV64 riscv test # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmcsPXsACgkQr3yVEwxT # gBOMjBAAm91x1C+mMLehRo4ESquziP1fGTPO0EyZmv/16Ze2AuKlfs/zPwbypmMY # VuUAsl2+/+XfiIQ+p7XN6YMrI9ixVluEHu6/o0FXObPyMOBE+5fLF+rqWfqmvbin # ifFmh8U7nkQ6Y9fxa7KOph8G5C+I4nDZRi4D6DS01+gljIBbNwxHz07YwAShoJiF # IlqwaiUmZAzA8thR5+WskpYLNOAdfR/0Z67QRc7xw7y3xcRUCsbwyUKCZMC7lWbJ # yvQeWPaOfFetbu7JFUZMlMwwNF1AGe6rigCaqT6Xjt0uBoeJLyXb6IOEOG8BN5aB # o+EeFK4gvn18qqegY1R7YNwS9p3XVvPnlw7AxF6YfkgOEb0qgAYhWabXG0CGizoH # A9prIg1Vft+qvOkAknq7v2knrv2mZ8VJsH4f+gBkKWWRnwpwE3S+jdhbbbw7af6W # AqkKgf96Klncikf/tYtnwUqG/42/yueUPg4Qfp2hUaxgy3M/ichze3FPF/DatS7B # ti/nlb+rXwheKaHUXFG8HpB7S4VNYToOeX+o79lXuV4XJAOVWEUVkE/LFV0B8hKT # O1NpLiF8Ql5MI0ylnUZ+kd/QFNMROrnzDJClOuNKEgBO+wMwZ+f2AKo/FWsCR9gD # 8i07SDj9GE+EmDpHtOgWMzp7KcpdqLNmQMBrezpLex/Z3390sQ4= # =dYLw # -----END PGP SIGNATURE----- # gpg: Signature made Thu 07 Nov 2024 04:09:31 GMT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20241107' of https://github.com/alistair23/qemu: tests/functional: Convert the RV32-on-RV64 riscv test target/riscv/kvm: Update kvm exts to Linux v6.11 target/riscv: Inline unit-stride ld/st and corresponding functions for performance target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride load-only-first load instructions target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us target/riscv: Set vdata.vm field for vector load/store whole register instructions hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check hw/riscv/riscv-iommu: change 'depth' to int hw/char/sifive_uart: Fix broken UART on big endian hosts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
@@ -174,10 +174,11 @@ sifive_uart_write(void *opaque, hwaddr addr,
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{
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SiFiveUARTState *s = opaque;
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uint32_t value = val64;
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uint8_t ch = value;
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switch (addr) {
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case SIFIVE_UART_TXFIFO:
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sifive_uart_write_tx_fifo(s, (uint8_t *) &value, 1);
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sifive_uart_write_tx_fifo(s, &ch, 1);
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return;
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case SIFIVE_UART_IE:
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s->ie = val64;
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@@ -820,7 +820,7 @@ static bool riscv_iommu_validate_process_ctx(RISCVIOMMUState *s,
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}
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if (ctx->tc & RISCV_IOMMU_DC_TC_SXL) {
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if (mode == RISCV_IOMMU_CAP_SV32 &&
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if (mode == RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 &&
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!(s->cap & RISCV_IOMMU_CAP_SV32)) {
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return false;
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}
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@@ -863,7 +863,7 @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx)
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/* Device Context format: 0: extended (64 bytes) | 1: base (32 bytes) */
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const int dc_fmt = !s->enable_msi;
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const size_t dc_len = sizeof(dc) >> dc_fmt;
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unsigned depth;
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int depth;
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uint64_t de;
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switch (mode) {
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@@ -770,6 +770,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)
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/* Mask destination register are always tail-agnostic */
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data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
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data = FIELD_DP32(data, VDATA, VMA, s->vma);
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data = FIELD_DP32(data, VDATA, VM, 1);
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return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
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}
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@@ -787,6 +788,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew)
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/* EMUL = 1, NFIELDS = 1 */
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data = FIELD_DP32(data, VDATA, LMUL, 0);
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data = FIELD_DP32(data, VDATA, NF, 1);
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data = FIELD_DP32(data, VDATA, VM, 1);
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return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
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}
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@@ -1106,6 +1108,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
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TCGv_i32 desc;
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uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
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data = FIELD_DP32(data, VDATA, VM, 1);
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dest = tcg_temp_new_ptr();
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desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
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s->cfg_ptr->vlenb, data));
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@@ -281,7 +281,10 @@ static KVMCPUConfig kvm_multi_ext_cfgs[] = {
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KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL),
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KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
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KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM),
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KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP),
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KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP),
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KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS),
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KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS),
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KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA),
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KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH),
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KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN),
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@@ -292,6 +295,10 @@ static KVMCPUConfig kvm_multi_ext_cfgs[] = {
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KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC),
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KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX),
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KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS),
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KVM_EXT_CFG("zca", ext_zca, KVM_RISCV_ISA_EXT_ZCA),
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KVM_EXT_CFG("zcb", ext_zcb, KVM_RISCV_ISA_EXT_ZCB),
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KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD),
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KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF),
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KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND),
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KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE),
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KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH),
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+395
-199
File diff suppressed because it is too large
Load Diff
@@ -222,19 +222,3 @@ class TuxRunBaselineTest(QemuSystemTest):
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"rootfs.ext4.zst" :
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"e6ffd8813c8a335bc15728f2835f90539c84be7f8f5f691a8b01451b47fb4bd7"}
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self.common_tuxrun(csums=sums)
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def test_riscv64_rv32(self):
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"""
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:avocado: tags=arch:riscv64
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:avocado: tags=machine:virt
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:avocado: tags=tuxboot:riscv32
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:avocado: tags=cpu:rv32
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"""
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sums = { "Image" :
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"89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
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"fw_jump.elf" :
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"f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
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"rootfs.ext4.zst" :
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"7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
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self.common_tuxrun(csums=sums)
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@@ -23,6 +23,13 @@ class TuxRunRiscV64Test(TuxRunBaselineTest):
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'https://storage.tuxboot.com/20230331/riscv64/rootfs.ext4.zst',
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'b18e3a3bdf27be03da0b285e84cb71bf09eca071c3a087b42884b6982ed679eb')
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ASSET_RISCV32_KERNEL = Asset(
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'https://storage.tuxboot.com/20230331/riscv32/Image',
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'89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5')
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ASSET_RISCV32_ROOTFS = Asset(
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'https://storage.tuxboot.com/20230331/riscv32/rootfs.ext4.zst',
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'7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba')
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def test_riscv64(self):
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self.set_machine('virt')
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self.common_tuxrun(kernel_asset=self.ASSET_RISCV64_KERNEL,
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@@ -34,5 +41,11 @@ class TuxRunRiscV64Test(TuxRunBaselineTest):
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self.common_tuxrun(kernel_asset=self.ASSET_RISCV64_KERNEL,
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rootfs_asset=self.ASSET_RISCV64_ROOTFS)
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def test_riscv64_rv32(self):
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self.set_machine('virt')
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self.cpu='rv32'
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self.common_tuxrun(kernel_asset=self.ASSET_RISCV32_KERNEL,
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rootfs_asset=self.ASSET_RISCV32_ROOTFS)
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if __name__ == '__main__':
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TuxRunBaselineTest.main()
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