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exec: Make ldl_*_phys input an AddressSpace

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Edgar E. Iglesias
2014-02-11 22:56:54 +10:00
parent 33bde2e13f
commit fdfba1a298
30 changed files with 186 additions and 145 deletions
Download Patch File Download Diff File Expand all files Collapse all files
cpu-exec.c
+4 -1
View File
@@ -395,7 +395,10 @@ int cpu_exec(CPUArchState *env)
/* FIXME: this should respect TPR */
cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
0);
intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
intno = ldl_phys(cpu->as,
env->vm_vmcb
+ offsetof(struct vmcb,
control.int_vector));
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
exec.c
+9 -10
View File
@@ -1614,7 +1614,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
switch (size) {
case 1: return ldub_phys(addr);
case 2: return lduw_phys(addr);
case 4: return ldl_phys(addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
}
@@ -2348,7 +2348,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
}
/* warning: addr must be aligned */
static inline uint32_t ldl_phys_internal(hwaddr addr,
static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2357,8 +2357,7 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
hwaddr l = 4;
hwaddr addr1;
mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
false);
mr = address_space_translate(as, addr, &addr1, &l, false);
if (l < 4 || !memory_access_is_direct(mr, false)) {
/* I/O case */
io_mem_read(mr, addr1, &val, 4);
@@ -2391,19 +2390,19 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
return val;
}
uint32_t ldl_phys(hwaddr addr)
uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
uint32_t ldl_le_phys(hwaddr addr)
uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
uint32_t ldl_be_phys(hwaddr addr)
uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
hw/dma/pl080.c
+5 -4
View File
@@ -8,6 +8,7 @@
*/
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E 0x1
@@ -204,10 +205,10 @@ again:
if (size == 0) {
/* Transfer complete. */
if (ch->lli) {
ch->src = ldl_le_phys(ch->lli);
ch->dest = ldl_le_phys(ch->lli + 4);
ch->ctrl = ldl_le_phys(ch->lli + 12);
ch->lli = ldl_le_phys(ch->lli + 8);
ch->src = ldl_le_phys(&address_space_memory, ch->lli);
ch->dest = ldl_le_phys(&address_space_memory, ch->lli + 4);
ch->ctrl = ldl_le_phys(&address_space_memory, ch->lli + 12);
ch->lli = ldl_le_phys(&address_space_memory, ch->lli + 8);
} else {
ch->conf &= ~PL080_CCONF_E;
}
hw/dma/sun4m_iommu.c
+2 -1
View File
@@ -24,6 +24,7 @@
#include "hw/sparc/sun4m.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#include "trace.h"
/*
@@ -262,7 +263,7 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
iopte = s->regs[IOMMU_BASE] << 4;
addr &= ~s->iostart;
iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
ret = ldl_be_phys(iopte);
ret = ldl_be_phys(&address_space_memory, iopte);
trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
return ret;
}
hw/net/vmware_utils.h
+1 -1
View File
@@ -95,7 +95,7 @@ vmw_shmem_st16(hwaddr addr, uint16_t value)
static inline uint32_t
vmw_shmem_ld32(hwaddr addr)
{
uint32_t res = ldl_le_phys(addr);
uint32_t res = ldl_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
hw/ppc/spapr_hcall.c
+9 -4
View File
@@ -390,6 +390,7 @@ static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
{
CPUState *cs = ENV_GET_CPU(env);
uint32_t size;
if (addr == 0) {
@@ -397,7 +398,7 @@ static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
return H_HARDWARE;
}
size = ldl_be_phys(addr + 0x4);
size = ldl_be_phys(cs->as, addr + 0x4);
if (size < 0x8) {
return H_PARAMETER;
}
@@ -425,6 +426,7 @@ static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
{
CPUState *cs = ENV_GET_CPU(env);
uint32_t size;
if (addr == 0) {
@@ -432,7 +434,7 @@ static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
return H_HARDWARE;
}
size = ldl_be_phys(addr + 0x4);
size = ldl_be_phys(cs->as, addr + 0x4);
if (size < 48) {
return H_PARAMETER;
@@ -532,6 +534,7 @@ static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr,
static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
CPUState *cs = CPU(cpu);
target_ulong size = args[0];
target_ulong addr = args[1];
@@ -543,7 +546,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
args[0] = lduw_phys(addr);
return H_SUCCESS;
case 4:
args[0] = ldl_phys(addr);
args[0] = ldl_phys(cs->as, addr);
return H_SUCCESS;
case 8:
args[0] = ldq_phys(addr);
@@ -579,6 +582,8 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
CPUState *cs = CPU(cpu);
target_ulong dst = args[0]; /* Destination address */
target_ulong src = args[1]; /* Source address */
target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
@@ -611,7 +616,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
tmp = lduw_phys(src);
break;
case 2:
tmp = ldl_phys(src);
tmp = ldl_phys(cs->as, src);
break;
case 3:
tmp = ldq_phys(src);
hw/s390x/css.c
+2 -1
View File
@@ -11,6 +11,7 @@
#include <hw/qdev.h>
#include "qemu/bitops.h"
#include "exec/address-spaces.h"
#include "cpu.h"
#include "ioinst.h"
#include "css.h"
@@ -667,7 +668,7 @@ static void css_update_chnmon(SubchDev *sch)
/* Format 1, per-subchannel area. */
uint32_t count;
count = ldl_phys(sch->curr_status.mba);
count = ldl_phys(&address_space_memory, sch->curr_status.mba);
count++;
stl_phys(sch->curr_status.mba, count);
} else {
hw/s390x/s390-virtio-bus.c
+1 -1
View File
@@ -409,7 +409,7 @@ void s390_virtio_device_update_status(VirtIOS390Device *dev)
/* Update guest supported feature bitmap */
features = bswap32(ldl_be_phys(dev->feat_offs));
features = bswap32(ldl_be_phys(&address_space_memory, dev->feat_offs));
virtio_set_features(vdev, features);
}
hw/s390x/virtio-ccw.c
+3 -2
View File
@@ -263,7 +263,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ret = -EFAULT;
} else {
info.queue = ldq_phys(ccw.cda);
info.align = ldl_phys(ccw.cda + sizeof(info.queue));
info.align = ldl_phys(&address_space_memory,
ccw.cda + sizeof(info.queue));
info.index = lduw_phys(ccw.cda + sizeof(info.queue)
+ sizeof(info.align));
info.num = lduw_phys(ccw.cda + sizeof(info.queue)
@@ -320,7 +321,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ret = -EFAULT;
} else {
features.index = ldub_phys(ccw.cda + sizeof(features.features));
features.features = ldl_le_phys(ccw.cda);
features.features = ldl_le_phys(&address_space_memory, ccw.cda);
if (features.index < ARRAY_SIZE(dev->host_features)) {
virtio_bus_set_vdev_features(&dev->bus, features.features);
vdev->guest_features = features.features;
hw/scsi/megasas.c
+2 -2
View File
@@ -602,8 +602,8 @@ static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
pa_lo = le32_to_cpu(initq->pi_addr_lo);
pa_hi = le32_to_cpu(initq->pi_addr_hi);
s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
s->reply_queue_head = ldl_le_phys(s->producer_pa);
s->reply_queue_tail = ldl_le_phys(s->consumer_pa);
s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
flags = le32_to_cpu(initq->flags);
if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
s->flags |= MEGASAS_MASK_USE_QUEUE64;
hw/scsi/vmw_pvscsi.c
+2 -1
View File
@@ -43,7 +43,8 @@
(sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
#define RS_GET_FIELD(rs_pa, field) \
(ldl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field)))
(ldl_le_phys(&address_space_memory, \
rs_pa + offsetof(struct PVSCSIRingsState, field)))
#define RS_SET_FIELD(rs_pa, field, val) \
(stl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field), val))
hw/virtio/virtio.c
+2 -1
View File
@@ -14,6 +14,7 @@
#include <inttypes.h>
#include "trace.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "hw/virtio/virtio.h"
#include "qemu/atomic.h"
@@ -111,7 +112,7 @@ static inline uint32_t vring_desc_len(hwaddr desc_pa, int i)
{
hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, len);
return ldl_phys(pa);
return ldl_phys(&address_space_memory, pa);
}
static inline uint16_t vring_desc_flags(hwaddr desc_pa, int i)
include/exec/cpu-common.h
+3 -3
View File
@@ -86,8 +86,8 @@ void qemu_flush_coalesced_mmio_buffer(void);
uint32_t ldub_phys(hwaddr addr);
uint32_t lduw_le_phys(hwaddr addr);
uint32_t lduw_be_phys(hwaddr addr);
uint32_t ldl_le_phys(hwaddr addr);
uint32_t ldl_be_phys(hwaddr addr);
uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_le_phys(hwaddr addr);
uint64_t ldq_be_phys(hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
@@ -100,7 +100,7 @@ void stq_be_phys(hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
uint32_t lduw_phys(hwaddr addr);
uint32_t ldl_phys(hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
include/hw/ppc/spapr.h
+1 -1
View File
@@ -348,7 +348,7 @@ static inline uint64_t ppc64_phys_to_real(uint64_t addr)
static inline uint32_t rtas_ld(target_ulong phys, int n)
{
return ldl_be_phys(ppc64_phys_to_real(phys + 4*n));
return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
}
static inline void rtas_st(target_ulong phys, int n, uint32_t val)
target-alpha/helper.h
+1 -1
View File
@@ -101,7 +101,7 @@ DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_2(hw_ret, void, env, i64)
DEF_HELPER_3(call_pal, void, env, i64, i64)
DEF_HELPER_1(ldl_phys, i64, i64)
DEF_HELPER_2(ldl_phys, i64, env, i64)
DEF_HELPER_1(ldq_phys, i64, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
target-alpha/mem_helper.c
+7 -4
View File
@@ -24,9 +24,10 @@
/* Softmmu support */
#ifndef CONFIG_USER_ONLY
uint64_t helper_ldl_phys(uint64_t p)
uint64_t helper_ldl_phys(CPUAlphaState *env, uint64_t p)
{
return (int32_t)ldl_phys(p);
CPUState *cs = ENV_GET_CPU(env);
return (int32_t)ldl_phys(cs->as, p);
}
uint64_t helper_ldq_phys(uint64_t p)
@@ -36,8 +37,9 @@ uint64_t helper_ldq_phys(uint64_t p)
uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p)
{
CPUState *cs = ENV_GET_CPU(env);
env->lock_addr = p;
return env->lock_value = (int32_t)ldl_phys(p);
return env->lock_value = (int32_t)ldl_phys(cs->as, p);
}
uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p)
@@ -58,10 +60,11 @@ void helper_stq_phys(uint64_t p, uint64_t v)
uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
{
CPUState *cs = ENV_GET_CPU(env);
uint64_t ret = 0;
if (p == env->lock_addr) {
int32_t old = ldl_phys(p);
int32_t old = ldl_phys(cs->as, p);
if (old == (int32_t)env->lock_value) {
stl_phys(p, v);
ret = 1;
target-alpha/translate.c
+1 -1
View File
@@ -2912,7 +2912,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access (hw_ldl/p) */
gen_helper_ldl_phys(cpu_ir[ra], addr);
gen_helper_ldl_phys(cpu_ir[ra], cpu_env, addr);
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
target-arm/helper.c
+9 -6
View File
@@ -2455,8 +2455,9 @@ static void v7m_push(CPUARMState *env, uint32_t val)
static uint32_t v7m_pop(CPUARMState *env)
{
CPUState *cs = ENV_GET_CPU(env);
uint32_t val;
val = ldl_phys(env->regs[13]);
val = ldl_phys(cs->as, env->regs[13]);
env->regs[13] += 4;
return val;
}
@@ -2611,7 +2612,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
/* Clear IT bits */
env->condexec_bits = 0;
env->regs[14] = lr;
addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
env->regs[15] = addr & 0xfffffffe;
env->thumb = addr & 1;
}
@@ -2816,6 +2817,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
int is_user, hwaddr *phys_ptr,
int *prot, target_ulong *page_size)
{
CPUState *cs = ENV_GET_CPU(env);
int code;
uint32_t table;
uint32_t desc;
@@ -2828,7 +2830,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
/* Pagetable walk. */
/* Lookup l1 descriptor. */
table = get_level1_table_address(env, address);
desc = ldl_phys(table);
desc = ldl_phys(cs->as, table);
type = (desc & 3);
domain = (desc >> 5) & 0x0f;
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
@@ -2859,7 +2861,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
/* Fine pagetable. */
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
}
desc = ldl_phys(table);
desc = ldl_phys(cs->as, table);
switch (desc & 3) {
case 0: /* Page translation fault. */
code = 7;
@@ -2911,6 +2913,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
int is_user, hwaddr *phys_ptr,
int *prot, target_ulong *page_size)
{
CPUState *cs = ENV_GET_CPU(env);
int code;
uint32_t table;
uint32_t desc;
@@ -2925,7 +2928,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
/* Pagetable walk. */
/* Lookup l1 descriptor. */
table = get_level1_table_address(env, address);
desc = ldl_phys(table);
desc = ldl_phys(cs->as, table);
type = (desc & 3);
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
/* Section translation fault, or attempt to use the encoding
@@ -2967,7 +2970,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
}
/* Lookup l2 entry. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
desc = ldl_phys(table);
desc = ldl_phys(cs->as, table);
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
switch (desc & 3) {
case 0: /* Page translation fault. */
target-i386/arch_memory_mapping.c
+19 -17
View File
@@ -16,7 +16,8 @@
#include "sysemu/memory_mapping.h"
/* PAE Paging or IA-32e Paging */
static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
static void walk_pte(MemoryMappingList *list, AddressSpace *as,
hwaddr pte_start_addr,
int32_t a20_mask, target_ulong start_line_addr)
{
hwaddr pte_addr, start_paddr;
@@ -45,7 +46,7 @@ static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
}
/* 32-bit Paging */
static void walk_pte2(MemoryMappingList *list,
static void walk_pte2(MemoryMappingList *list, AddressSpace *as,
hwaddr pte_start_addr, int32_t a20_mask,
target_ulong start_line_addr)
{
@@ -56,7 +57,7 @@ static void walk_pte2(MemoryMappingList *list,
for (i = 0; i < 1024; i++) {
pte_addr = (pte_start_addr + i * 4) & a20_mask;
pte = ldl_phys(pte_addr);
pte = ldl_phys(as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -77,7 +78,8 @@ static void walk_pte2(MemoryMappingList *list,
/* PAE Paging or IA-32e Paging */
#define PLM4_ADDR_MASK 0xffffffffff000ULL /* selects bits 51:12 */
static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
static void walk_pde(MemoryMappingList *list, AddressSpace *as,
hwaddr pde_start_addr,
int32_t a20_mask, target_ulong start_line_addr)
{
hwaddr pde_addr, pte_start_addr, start_paddr;
@@ -108,12 +110,12 @@ static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
}
pte_start_addr = (pde & PLM4_ADDR_MASK) & a20_mask;
walk_pte(list, pte_start_addr, a20_mask, line_addr);
walk_pte(list, as, pte_start_addr, a20_mask, line_addr);
}
}
/* 32-bit Paging */
static void walk_pde2(MemoryMappingList *list,
static void walk_pde2(MemoryMappingList *list, AddressSpace *as,
hwaddr pde_start_addr, int32_t a20_mask,
bool pse)
{
@@ -124,7 +126,7 @@ static void walk_pde2(MemoryMappingList *list,
for (i = 0; i < 1024; i++) {
pde_addr = (pde_start_addr + i * 4) & a20_mask;
pde = ldl_phys(pde_addr);
pde = ldl_phys(as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -150,12 +152,12 @@ static void walk_pde2(MemoryMappingList *list,
}
pte_start_addr = (pde & ~0xfff) & a20_mask;
walk_pte2(list, pte_start_addr, a20_mask, line_addr);
walk_pte2(list, as, pte_start_addr, a20_mask, line_addr);
}
}
/* PAE Paging */
static void walk_pdpe2(MemoryMappingList *list,
static void walk_pdpe2(MemoryMappingList *list, AddressSpace *as,
hwaddr pdpe_start_addr, int32_t a20_mask)
{
hwaddr pdpe_addr, pde_start_addr;
@@ -173,13 +175,13 @@ static void walk_pdpe2(MemoryMappingList *list,
line_addr = (((unsigned int)i & 0x3) << 30);
pde_start_addr = (pdpe & ~0xfff) & a20_mask;
walk_pde(list, pde_start_addr, a20_mask, line_addr);
walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
}
}
#ifdef TARGET_X86_64
/* IA-32e Paging */
static void walk_pdpe(MemoryMappingList *list,
static void walk_pdpe(MemoryMappingList *list, AddressSpace *as,
hwaddr pdpe_start_addr, int32_t a20_mask,
target_ulong start_line_addr)
{
@@ -211,12 +213,12 @@ static void walk_pdpe(MemoryMappingList *list,
}
pde_start_addr = (pdpe & PLM4_ADDR_MASK) & a20_mask;
walk_pde(list, pde_start_addr, a20_mask, line_addr);
walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
}
}
/* IA-32e Paging */
static void walk_pml4e(MemoryMappingList *list,
static void walk_pml4e(MemoryMappingList *list, AddressSpace *as,
hwaddr pml4e_start_addr, int32_t a20_mask)
{
hwaddr pml4e_addr, pdpe_start_addr;
@@ -234,7 +236,7 @@ static void walk_pml4e(MemoryMappingList *list,
line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48);
pdpe_start_addr = (pml4e & PLM4_ADDR_MASK) & a20_mask;
walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr);
walk_pdpe(list, as, pdpe_start_addr, a20_mask, line_addr);
}
}
#endif
@@ -256,14 +258,14 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
hwaddr pml4e_addr;
pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask;
walk_pml4e(list, pml4e_addr, env->a20_mask);
walk_pml4e(list, cs->as, pml4e_addr, env->a20_mask);
} else
#endif
{
hwaddr pdpe_addr;
pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
walk_pdpe2(list, pdpe_addr, env->a20_mask);
walk_pdpe2(list, cs->as, pdpe_addr, env->a20_mask);
}
} else {
hwaddr pde_addr;
@@ -271,7 +273,7 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
pse = !!(env->cr[4] & CR4_PSE_MASK);
walk_pde2(list, pde_addr, env->a20_mask, pse);
walk_pde2(list, cs->as, pde_addr, env->a20_mask, pse);
}
}
target-i386/helper.c
+5 -4
View File
@@ -515,6 +515,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
int is_write1, int mmu_idx)
{
CPUState *cs = ENV_GET_CPU(env);
uint64_t ptep, pte;
target_ulong pde_addr, pte_addr;
int error_code, is_dirty, prot, page_size, is_write, is_user;
@@ -734,7 +735,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* page directory entry */
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
env->a20_mask;
pde = ldl_phys(pde_addr);
pde = ldl_phys(cs->as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -792,7 +793,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* page directory entry */
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
env->a20_mask;
pte = ldl_phys(pte_addr);
pte = ldl_phys(cs->as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -963,7 +964,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
/* page directory entry */
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
pde = ldl_phys(pde_addr);
pde = ldl_phys(cs->as, pde_addr);
if (!(pde & PG_PRESENT_MASK))
return -1;
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
@@ -972,7 +973,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
} else {
/* page directory entry */
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask;
pte = ldl_phys(pte_addr);
pte = ldl_phys(cs->as, pte_addr);
if (!(pte & PG_PRESENT_MASK))
return -1;
page_size = 4096;

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