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Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210930' into staging

Browse Source 
ppc patch queue for 2021-09-30

Here's the next batch of ppc related patches for qemu-6.2.  Highlights
are:
 * Fixes for several TCG math instructions from the El Dorado Institute
 * A number of improvements to the powernv machine type
 * Support for a new DEVICE_UNPLUG_GUEST_ERROR QAPI event from Daniel
   Barboza
 * Support for the new FORM2 PAPR NUMA representation.  This allows
   more specific NUMA distances, as well as asymmetric configurations
 * Fix for 64-bit decrementer (used on MicroWatt CPUs)
 * Assorted fixes and cleanups
 * A number of updates to MAINTAINERS

Note that the DEVICE_UNPLUG_GUEST_ERROR stuff includes changes to
files outside my normal area, but has suitable Acks.

The MAINTAINERS updates are mostly about marking minor platforms
unmaintained / orphaned, and moving some pieces away from myself and
Greg.  As we move onto other projects, we're going to need to drop
more of the ppc maintainership, though we're hoping we can avoid too
abrupt a change.

# gpg: Signature made Thu 30 Sep 2021 06:42:41 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dg-gitlab/tags/ppc-for-6.2-20210930: (44 commits)
  MAINTAINERS: Demote sPAPR from "Supported" to "Maintained"
  MAINTAINERS: Add information for OpenPIC
  MAINTAINERS: Remove David & Greg as reviewers/co-maintainers of powernv
  MAINTAINERS: Orphan obscure ppc platforms
  MAINTAINERS: Remove David & Greg as reviewers for a number of boards
  MAINTAINERS: Remove machine specific files from ppc TCG CPUs entry
  spapr/xive: Fix kvm_xive_source_reset trace event
  spapr_numa.c: fixes in spapr_numa_FORM2_write_rtas_tables()
  hw/intc: openpic: Clean up the styles
  hw/intc: openpic: Drop Raven related codes
  hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset
  target/ppc: Fix 64-bit decrementer
  target/ppc: Convert debug to trace events (decrementer and IRQ)
  spapr_numa.c: handle auto NUMA node with no distance info
  spapr_numa.c: FORM2 NUMA affinity support
  spapr: move FORM1 verifications to post CAS
  spapr_numa.c: rename numa_assoc_array to FORM1_assoc_array
  spapr_numa.c: parametrize FORM1 macros
  spapr_numa.c: scrap 'legacy_numa' concept
  spapr_numa.c: split FORM1 code into helpers
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2021-09-30 16:13:04 +01:00
parent 98850d84f7 85d887be82
commit fce8f7735f
35 changed files with 747 additions and 451 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+17 -30
View File
@@ -271,8 +271,9 @@ M: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Maintained
F: target/ppc/
F: hw/ppc/
F: include/hw/ppc/
F: hw/ppc/ppc.c
F: hw/ppc/ppc_booke.c
F: include/hw/ppc/ppc.h
F: disas/ppc.c
RISC-V TCG CPUs
@@ -1235,24 +1236,18 @@ F: hw/openrisc/openrisc_sim.c
PowerPC Machines
----------------
405
M: David Gibson <david@gibson.dropbear.id.au>
M: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Odd Fixes
S: Orphan
F: hw/ppc/ppc405_boards.c
Bamboo
M: David Gibson <david@gibson.dropbear.id.au>
M: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Odd Fixes
S: Orphan
F: hw/ppc/ppc440_bamboo.c
e500
M: David Gibson <david@gibson.dropbear.id.au>
M: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Odd Fixes
S: Orphan
F: hw/ppc/e500*
F: hw/gpio/mpc8xxx.c
F: hw/i2c/mpc_i2c.c
@@ -1261,20 +1256,18 @@ F: hw/pci-host/ppce500.c
F: include/hw/ppc/ppc_e500.h
F: include/hw/pci-host/ppce500.h
F: pc-bios/u-boot.e500
F: hw/intc/openpic_kvm.h
F: include/hw/ppc/openpic_kvm.h
mpc8544ds
M: David Gibson <david@gibson.dropbear.id.au>
M: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Odd Fixes
S: Orphan
F: hw/ppc/mpc8544ds.c
F: hw/ppc/mpc8544_guts.c
F: tests/acceptance/ppc_mpc8544ds.py
New World (mac99)
M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Odd Fixes
F: hw/ppc/mac_newworld.c
@@ -1293,8 +1286,6 @@ F: pc-bios/qemu_vga.ndrv
Old World (g3beige)
M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Odd Fixes
F: hw/ppc/mac_oldworld.c
@@ -1308,8 +1299,6 @@ F: pc-bios/qemu_vga.ndrv
PReP
M: Hervé Poussineau <hpoussin@reactos.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Maintained
F: hw/ppc/prep.c
@@ -1328,7 +1317,7 @@ sPAPR
M: David Gibson <david@gibson.dropbear.id.au>
M: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Supported
S: Maintained
F: hw/*/spapr*
F: include/hw/*/spapr*
F: hw/*/xics*
@@ -1344,8 +1333,6 @@ F: tests/acceptance/ppc_pseries.py
PowerNV (Non-Virtualized)
M: Cédric Le Goater <clg@kaod.org>
M: David Gibson <david@gibson.dropbear.id.au>
M: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Maintained
F: hw/ppc/pnv*
@@ -1366,8 +1353,6 @@ F: tests/acceptance/ppc_virtex_ml507.py
sam460ex
M: BALATON Zoltan <balaton@eik.bme.hu>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Maintained
F: hw/ppc/sam460ex.c
@@ -1381,7 +1366,6 @@ F: roms/u-boot-sam460ex
pegasos2
M: BALATON Zoltan <balaton@eik.bme.hu>
R: David Gibson <david@gibson.dropbear.id.au>
L: qemu-ppc@nongnu.org
S: Maintained
F: hw/ppc/pegasos2.c
@@ -1785,9 +1769,8 @@ F: include/hw/acpi/ghes.h
F: docs/specs/acpi_hest_ghes.rst
ppc4xx
M: David Gibson <david@gibson.dropbear.id.au>
L: qemu-ppc@nongnu.org
S: Odd Fixes
S: Orphan
F: hw/ppc/ppc4*.c
F: hw/i2c/ppc4xx_i2c.c
F: include/hw/ppc/ppc4xx.h
@@ -2242,8 +2225,6 @@ T: git https://github.com/philmd/qemu.git fw_cfg-next
XIVE
M: Cédric Le Goater <clg@kaod.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Supported
F: hw/*/*xive*
@@ -2279,6 +2260,12 @@ F: net/can/*
F: hw/net/can/*
F: include/net/can_*.h
OpenPIC interrupt controller
M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
S: Odd Fixes
F: hw/intc/openpic.c
F: include/hw/ppc/openpic.h
Subsystems
----------
Overall Audio backends
docs/about/deprecated.rst
+10
View File
@@ -238,6 +238,16 @@ The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated
(the ISA has never been upstreamed to a compiler toolchain). Therefore
this CPU is also deprecated.
QEMU API (QAPI) events
----------------------
``MEM_UNPLUG_ERROR`` (since 6.2)
''''''''''''''''''''''''''''''''''''''''''''''''''''''''
Use the more generic event ``DEVICE_UNPLUG_GUEST_ERROR`` instead.
System emulator machines
------------------------
docs/system/ppc/powernv.rst
+1 -2
View File
@@ -53,8 +53,7 @@ initramfs ``skiroot``. Source code can be found on GitHub:
https://github.com/open-power.
Prebuilt images of ``skiboot`` and ``skiboot`` are made available on the `OpenPOWER <https://openpower.xyz/job/openpower/job/openpower-op-build/>`__ site. To boot a POWER9 machine, use the `witherspoon <https://openpower.xyz/job/openpower/job/openpower-op-build/label=slave,target=witherspoon/lastSuccessfulBuild/>`__ images. For POWER8, use
the `palmetto <https://openpower.xyz/job/openpower/job/openpower-op-build/label=slave,target=palmetto/lastSuccessfulBuild/>`__ images.
Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the `OpenPOWER <https://github.com/open-power/op-build/releases/>`__ site.
QEMU includes a prebuilt image of ``skiboot`` which is updated when a
more recent version is required by the models.
hw/acpi/memory_hotplug.c
+10 -1
View File
@@ -8,6 +8,7 @@
#include "qapi/error.h"
#include "qapi/qapi-events-acpi.h"
#include "qapi/qapi-events-machine.h"
#include "qapi/qapi-events-qdev.h"
#define MEMORY_SLOTS_NUMBER "MDNR"
#define MEMORY_HOTPLUG_IO_REGION "HPMR"
@@ -178,8 +179,16 @@ static void acpi_memory_hotplug_write(void *opaque, hwaddr addr, uint64_t data,
hotplug_handler_unplug(hotplug_ctrl, dev, &local_err);
if (local_err) {
trace_mhp_acpi_pc_dimm_delete_failed(mem_st->selector);
qapi_event_send_mem_unplug_error(dev->id,
/*
* Send both MEM_UNPLUG_ERROR and DEVICE_UNPLUG_GUEST_ERROR
* while the deprecation of MEM_UNPLUG_ERROR is
* pending.
*/
qapi_event_send_mem_unplug_error(dev->id ? : "",
error_get_pretty(local_err));
qapi_event_send_device_unplug_guest_error(!!dev->id, dev->id,
dev->canonical_path);
error_free(local_err);
break;
}
hw/i386/kvm/i8254.c
+1 -6
View File
@@ -59,11 +59,6 @@ struct KVMPITClass {
DeviceRealize parent_realize;
};
static int64_t abs64(int64_t v)
{
return v < 0 ? -v : v;
}
static void kvm_pit_update_clock_offset(KVMPITState *s)
{
int64_t offset, clock_offset;
@@ -81,7 +76,7 @@ static void kvm_pit_update_clock_offset(KVMPITState *s)
clock_gettime(CLOCK_MONOTONIC, &ts);
offset -= ts.tv_nsec;
offset -= (int64_t)ts.tv_sec * 1000000000;
if (abs64(offset) < abs64(clock_offset)) {
if (uabs64(offset) < uabs64(clock_offset)) {
clock_offset = offset;
}
}
hw/intc/openpic.c
+44 -48
View File
@@ -25,12 +25,8 @@
/*
*
* Based on OpenPic implementations:
* - Intel GW80314 I/O companion chip developer's manual
* - Motorola MPC8245 & MPC8540 user manuals.
* - Motorola MCP750 (aka Raven) programmer manual.
* - Motorola Harrier programmer manuel
*
* Serial interrupts, as implemented in Raven chipset are not supported yet.
* - Motorola Harrier programmer manual
*
*/
@@ -51,7 +47,7 @@
#include "qemu/timer.h"
#include "qemu/error-report.h"
//#define DEBUG_OPENPIC
/* #define DEBUG_OPENPIC */
#ifdef DEBUG_OPENPIC
static const int debug_openpic = 1;
@@ -122,7 +118,8 @@ static FslMpicInfo fsl_mpic_42 = {
#define ILR_INTTGT_CINT 0x01 /* critical */
#define ILR_INTTGT_MCP 0x02 /* machine check */
/* The currently supported INTTGT values happen to be the same as QEMU's
/*
* The currently supported INTTGT values happen to be the same as QEMU's
* openpic output codes, but don't depend on this. The output codes
* could change (unlikely, but...) or support could be added for
* more INTTGT values.
@@ -181,10 +178,11 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
uint32_t val, int idx);
static void openpic_reset(DeviceState *d);
/* Convert between openpic clock ticks and nanosecs. In the hardware the clock
frequency is driven by board inputs to the PIC which the PIC would then
divide by 4 or 8. For now hard code to 25MZ.
*/
/*
* Convert between openpic clock ticks and nanosecs. In the hardware the clock
* frequency is driven by board inputs to the PIC which the PIC would then
* divide by 4 or 8. For now hard code to 25MZ.
*/
#define OPENPIC_TIMER_FREQ_MHZ 25
#define OPENPIC_TIMER_NS_PER_TICK (1000 / OPENPIC_TIMER_FREQ_MHZ)
static inline uint64_t ns_to_ticks(uint64_t ns)
@@ -257,7 +255,8 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
__func__, src->output, n_IRQ, active, was_active,
dst->outputs_active[src->output]);
/* On Freescale MPIC, critical interrupts ignore priority,
/*
* On Freescale MPIC, critical interrupts ignore priority,
* IACK, EOI, etc. Before MPIC v4.1 they also ignore
* masking.
*/
@@ -280,7 +279,8 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
priority = IVPR_PRIORITY(src->ivpr);
/* Even if the interrupt doesn't have enough priority,
/*
* Even if the interrupt doesn't have enough priority,
* it is still raised, in case ctpr is lowered later.
*/
if (active) {
@@ -412,7 +412,8 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
}
if (src->output != OPENPIC_OUTPUT_INT) {
/* Edge-triggered interrupts shouldn't be used
/*
* Edge-triggered interrupts shouldn't be used
* with non-INT delivery, but just in case,
* try to make it do something sane rather than
* cause an interrupt storm. This is close to
@@ -505,7 +506,8 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
{
uint32_t mask;
/* NOTE when implementing newer FSL MPIC models: starting with v4.0,
/*
* NOTE when implementing newer FSL MPIC models: starting with v4.0,
* the polarity bit is read-only on internal interrupts.
*/
mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK |
@@ -515,7 +517,8 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
opp->src[n_IRQ].ivpr =
(opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
/* For FSL internal interrupts, The sense bit is reserved and zero,
/*
* For FSL internal interrupts, The sense bit is reserved and zero,
* and the interrupt is always level-triggered. Timers and IPIs
* have no sense or polarity bits, and are edge-triggered.
*/
@@ -699,16 +702,20 @@ static void qemu_timer_cb(void *opaque)
openpic_set_irq(opp, n_IRQ, 0);
}
/* If enabled is true, arranges for an interrupt to be raised val clocks into
the future, if enabled is false cancels the timer. */
/*
* If enabled is true, arranges for an interrupt to be raised val clocks into
* the future, if enabled is false cancels the timer.
*/
static void openpic_tmr_set_tmr(OpenPICTimer *tmr, uint32_t val, bool enabled)
{
uint64_t ns = ticks_to_ns(val & ~TCCR_TOG);
/* A count of zero causes a timer to be set to expire immediately. This
effectively stops the simulation since the timer is constantly expiring
which prevents guest code execution, so we don't honor that
configuration. On real hardware, this situation would generate an
interrupt on every clock cycle if the interrupt was unmasked. */
/*
* A count of zero causes a timer to be set to expire immediately. This
* effectively stops the simulation since the timer is constantly expiring
* which prevents guest code execution, so we don't honor that
* configuration. On real hardware, this situation would generate an
* interrupt on every clock cycle if the interrupt was unmasked.
*/
if ((ns == 0) || !enabled) {
tmr->qemu_timer_active = false;
tmr->tccr = tmr->tccr & TCCR_TOG;
@@ -721,8 +728,10 @@ static void openpic_tmr_set_tmr(OpenPICTimer *tmr, uint32_t val, bool enabled)
}
}
/* Returns the currrent tccr value, i.e., timer value (in clocks) with
appropriate TOG. */
/*
* Returns the currrent tccr value, i.e., timer value (in clocks) with
* appropriate TOG.
*/
static uint64_t openpic_tmr_get_timer(OpenPICTimer *tmr)
{
uint64_t retval;
@@ -1276,6 +1285,15 @@ static void openpic_reset(DeviceState *d)
break;
}
/* Mask all IPI interrupts for Freescale OpenPIC */
if ((opp->model == OPENPIC_MODEL_FSL_MPIC_20) ||
(opp->model == OPENPIC_MODEL_FSL_MPIC_42)) {
if (i >= opp->irq_ipi0 && i < opp->irq_tim0) {
write_IRQreg_idr(opp, i, 0);
continue;
}
}
write_IRQreg_idr(opp, i, opp->idr_reset);
}
/* Initialise IRQ destinations */
@@ -1304,7 +1322,7 @@ static void openpic_reset(DeviceState *d)
typedef struct MemReg {
const char *name;
MemoryRegionOps const *ops;
hwaddr start_addr;
hwaddr start_addr;
ram_addr_t size;
} MemReg;
@@ -1555,28 +1573,6 @@ static void openpic_realize(DeviceState *dev, Error **errp)
break;
case OPENPIC_MODEL_RAVEN:
opp->nb_irqs = RAVEN_MAX_EXT;
opp->vid = VID_REVISION_1_3;
opp->vir = VIR_GENERIC;
opp->vector_mask = 0xFF;
opp->tfrr_reset = 4160000;
opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK;
opp->idr_reset = 0;
opp->max_irq = RAVEN_MAX_IRQ;
opp->irq_ipi0 = RAVEN_IPI_IRQ;
opp->irq_tim0 = RAVEN_TMR_IRQ;
opp->brr1 = -1;
opp->mpic_mode_mask = GCR_MODE_MIXED;
if (opp->nb_cpus != 1) {
error_setg(errp, "Only UP supported today");
return;
}
map_list(opp, list_le, &list_count);
break;
case OPENPIC_MODEL_KEYLARGO:
opp->nb_irqs = KEYLARGO_MAX_EXT;
opp->vid = VID_REVISION_1_2;
hw/intc/spapr_xive_kvm.c
+2 -2
View File
@@ -236,6 +236,8 @@ int kvmppc_xive_source_reset_one(XiveSource *xsrc, int srcno, Error **errp)
SpaprXive *xive = SPAPR_XIVE(xsrc->xive);
uint64_t state = 0;
trace_kvm_xive_source_reset(srcno);
assert(xive->fd != -1);
if (xive_source_irq_is_lsi(xsrc, srcno)) {
@@ -311,8 +313,6 @@ uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset,
return xive_esb_rw(xsrc, srcno, offset, data, 1);
}
trace_kvm_xive_source_reset(srcno);
/*
* Special Load EOI handling for LSI sources. Q bit is never set
* and the interrupt should be re-triggered if the level is still
hw/intc/xive.c
+6 -20
View File
@@ -27,17 +27,6 @@
* XIVE Thread Interrupt Management context
*/
/*
* Convert a priority number to an Interrupt Pending Buffer (IPB)
* register, which indicates a pending interrupt at the priority
* corresponding to the bit number
*/
static uint8_t priority_to_ipb(uint8_t priority)
{
return priority > XIVE_PRIORITY_MAX ?
0 : 1 << (XIVE_PRIORITY_MAX - priority);
}
/*
* Convert an Interrupt Pending Buffer (IPB) register to a Pending
* Interrupt Priority Register (PIPR), which contains the priority of
@@ -89,7 +78,7 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring)
regs[TM_CPPR] = cppr;
/* Reset the pending buffer bit */
regs[TM_IPB] &= ~priority_to_ipb(cppr);
regs[TM_IPB] &= ~xive_priority_to_ipb(cppr);
regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
/* Drop Exception bit */
@@ -152,11 +141,6 @@ void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)
xive_tctx_notify(tctx, ring);
}
static inline uint32_t xive_tctx_word2(uint8_t *ring)
{
return *((uint32_t *) &ring[TM_WORD2]);
}
/*
* XIVE Thread Interrupt Management Area (TIMA)
*/
@@ -353,7 +337,7 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size)
{
xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff));
xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xff));
}
static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
@@ -1535,7 +1519,8 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
/* handle CPU exception delivery */
if (count) {
trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring);
xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority));
xive_tctx_ipb_update(match.tctx, match.ring,
xive_priority_to_ipb(priority));
}
return !!count;
@@ -1682,7 +1667,8 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
* use. The presenter will resend the interrupt when the vCPU
* is dispatched again on a HW thread.
*/
ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority);
ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) |
xive_priority_to_ipb(priority);
nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb);
xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
hw/ppc/pnv.c
+7 -6
View File
@@ -723,6 +723,8 @@ static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
}
assert(pnv->num_chips > 1);
ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
}
@@ -838,8 +840,7 @@ static void pnv_init(MachineState *machine)
for (i = 0; i < pnv->num_chips; i++) {
char chip_name[32];
Object *chip = OBJECT(qdev_new(chip_typename));
int chip_id = i;
uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, chip_id);
uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
pnv->chips[i] = PNV_CHIP(chip);
@@ -850,9 +851,9 @@ static void pnv_init(MachineState *machine)
&error_fatal);
chip_ram_start += chip_ram_size;
snprintf(chip_name, sizeof(chip_name), "chip[%d]", chip_id);
snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
object_property_add_child(OBJECT(pnv), chip_name, chip);
object_property_set_int(chip, "chip-id", chip_id, &error_fatal);
object_property_set_int(chip, "chip-id", i, &error_fatal);
object_property_set_int(chip, "nr-cores", machine->smp.cores,
&error_fatal);
object_property_set_int(chip, "nr-threads", machine->smp.threads,
@@ -1369,10 +1370,10 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
sizeof(*eq), TYPE_PNV_QUAD,
&error_fatal, NULL);
object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal);
object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
qdev_realize(DEVICE(eq), NULL, &error_fatal);
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
}
}
hw/ppc/pnv_core.c
+2 -2
View File
@@ -407,13 +407,13 @@ static void pnv_quad_realize(DeviceState *dev, Error **errp)
PnvQuad *eq = PNV_QUAD(dev);
char name[32];
snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
eq, name, PNV9_XSCOM_EQ_SIZE);
}
static Property pnv_quad_properties[] = {
DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
DEFINE_PROP_UINT32("quad-id", PnvQuad, quad_id, 0),
DEFINE_PROP_END_OF_LIST(),
};
hw/ppc/pnv_xscom.c
+4
View File
@@ -284,6 +284,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
_FDT(xscom_offset);
g_free(name);
_FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
/*
* On P10, the xscom bus id has been deprecated and the chip id is
* calculated from the "Primary topology table index". See skiboot.
*/
_FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,primary-topology-index",
chip->chip_id)));
_FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
hw/ppc/ppc.c
+75 -136
View File
File diff suppressed because it is too large Load Diff
hw/ppc/spapr.c
+18 -35
View File
@@ -29,6 +29,7 @@
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "qapi/qapi-events-machine.h"
#include "qapi/qapi-events-qdev.h"
#include "qapi/visitor.h"
#include "sysemu/sysemu.h"
#include "sysemu/hostmem.h"
@@ -2752,6 +2753,11 @@ static void spapr_machine_init(MachineState *machine)
spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
/* Do not advertise FORM2 NUMA support for pseries-6.1 and older */
if (!smc->pre_6_2_numa_affinity) {
spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY);
}
/* advertise support for dedicated HP event source to guests */
if (spapr->use_hotplug_event_source) {
spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
@@ -2773,39 +2779,6 @@ static void spapr_machine_init(MachineState *machine)
/* init CPUs */
spapr_init_cpus(spapr);
/*
* check we don't have a memory-less/cpu-less NUMA node
* Firmware relies on the existing memory/cpu topology to provide the
* NUMA topology to the kernel.
* And the linux kernel needs to know the NUMA topology at start
* to be able to hotplug CPUs later.
*/
if (machine->numa_state->num_nodes) {
for (i = 0; i < machine->numa_state->num_nodes; ++i) {
/* check for memory-less node */
if (machine->numa_state->nodes[i].node_mem == 0) {
CPUState *cs;
int found = 0;
/* check for cpu-less node */
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
if (cpu->node_id == i) {
found = 1;
break;
}
}
/* memory-less and cpu-less node */
if (!found) {
error_report(
"Memory-less/cpu-less nodes are not supported (node %d)",
i);
exit(1);
}
}
}
}
spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine);
/* Init numa_assoc_array */
@@ -3686,11 +3659,18 @@ void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev)
/*
* Tell QAPI that something happened and the memory
* hotunplug wasn't successful.
* hotunplug wasn't successful. Keep sending
* MEM_UNPLUG_ERROR even while sending
* DEVICE_UNPLUG_GUEST_ERROR until the deprecation of
* MEM_UNPLUG_ERROR is due.
*/
qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest "
"for device %s", dev->id);
qapi_event_send_mem_unplug_error(dev->id, qapi_error);
qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error);
qapi_event_send_device_unplug_guest_error(!!dev->id, dev->id,
dev->canonical_path);
}
/* Callback to be called during DRC release. */
@@ -4700,8 +4680,11 @@ DEFINE_SPAPR_MACHINE(6_2, "6.2", true);
*/
static void spapr_machine_6_1_class_options(MachineClass *mc)
{
SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
spapr_machine_6_2_class_options(mc);
compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
smc->pre_6_2_numa_affinity = true;
}
DEFINE_SPAPR_MACHINE(6_1, "6.1", false);
hw/ppc/spapr_cpu_core.c
+1
View File
@@ -382,6 +382,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
#ifdef CONFIG_KVM
DEFINE_SPAPR_CPU_CORE_TYPE("host"),
#endif
hw/ppc/spapr_drc.c
+10 -6
View File
@@ -17,6 +17,8 @@
#include "hw/ppc/spapr_drc.h"
#include "qom/object.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qapi/qapi-events-qdev.h"
#include "qapi/visitor.h"
#include "qemu/error-report.h"
#include "hw/ppc/spapr.h" /* for RTAS return codes */
@@ -167,13 +169,15 @@ static uint32_t drc_unisolate_logical(SpaprDrc *drc)
}
drc->unplug_requested = false;
error_report("Device hotunplug rejected by the guest "
"for device %s", drc->dev->id);
/*
* TODO: send a QAPI DEVICE_UNPLUG_ERROR event when
* it is implemented.
*/
if (drc->dev->id) {
error_report("Device hotunplug rejected by the guest "
"for device %s", drc->dev->id);
}
qapi_event_send_device_unplug_guest_error(!!drc->dev->id,
drc->dev->id,
drc->dev->canonical_path);
}
return RTAS_OUT_SUCCESS; /* Nothing to do */
hw/ppc/spapr_hcall.c
+7
View File
@@ -17,6 +17,7 @@
#include "kvm_ppc.h"
#include "hw/ppc/fdt.h"
#include "hw/ppc/spapr_ovec.h"
#include "hw/ppc/spapr_numa.h"
#include "mmu-book3s-v3.h"
#include "hw/mem/memory-device.h"
@@ -1197,6 +1198,12 @@ target_ulong do_client_architecture_support(PowerPCCPU *cpu,
spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00);
spapr_ovec_cleanup(ov1_guest);
/*
* Check for NUMA affinity conditions now that we know which NUMA
* affinity the guest will use.
*/
spapr_numa_associativity_check(spapr);
/*
* Ensure the guest asks for an interrupt mode we support;
* otherwise terminate the boot.
hw/ppc/spapr_numa.c
+314 -65
View File
File diff suppressed because it is too large Load Diff
hw/ppc/trace-events
+20
View File
@@ -97,7 +97,27 @@ vof_claimed(uint64_t start, uint64_t end, uint64_t size) "0x%"PRIx64"..0x%"PRIx6
# ppc.c
ppc_tb_adjust(uint64_t offs1, uint64_t offs2, int64_t diff, int64_t seconds) "adjusted from 0x%"PRIx64" to 0x%"PRIx64", diff %"PRId64" (%"PRId64"s)"
ppc_tb_load(uint64_t tb) "tb 0x%016" PRIx64
ppc_tb_store(uint64_t tb, uint64_t offset) "tb 0x%016" PRIx64 " offset 0x%08" PRIx64
ppc_decr_load(uint64_t tb) "decr 0x%016" PRIx64
ppc_decr_excp(const char *action) "%s decrementer"
ppc_decr_store(uint32_t nr_bits, uint64_t decr, uint64_t value) "%d-bit 0x%016" PRIx64 " => 0x%016" PRIx64
ppc4xx_fit(uint32_t ir, uint64_t tcr, uint64_t tsr) "ir %d TCR 0x%" PRIx64 " TSR 0x%" PRIx64
ppc4xx_pit_stop(void) ""
ppc4xx_pit_start(uint64_t reload) "PIT 0x%016" PRIx64
ppc4xx_pit(uint32_t ar, uint32_t ir, uint64_t tcr, uint64_t tsr, uint64_t reload) "ar %d ir %d TCR 0x%" PRIx64 " TSR 0x%" PRIx64 " PIT 0x%016" PRIx64
ppc4xx_wdt(uint64_t tcr, uint64_t tsr) "TCR 0x%" PRIx64 " TSR 0x%" PRIx64
ppc40x_store_pit(uint64_t value) "val 0x%" PRIx64
ppc40x_set_tb_clk(uint32_t value) "new frequency %" PRIu32
ppc40x_timers_init(uint32_t value) "frequency %" PRIu32
ppc_irq_set(void *env, uint32_t pin, uint32_t level) "env [%p] pin %d level %d"
ppc_irq_set_exit(void *env, uint32_t n_IRQ, uint32_t level, uint32_t pending, uint32_t request) "env [%p] n_IRQ %d level %d => pending 0x%08" PRIx32 " req 0x%08" PRIx32
ppc_irq_set_state(const char *name, uint32_t level) "\"%s\" level %d"
ppc_irq_reset(const char *name) "%s"
ppc_irq_cpu(const char *action) "%s"
# prep_systemio.c
prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
include/hw/ppc/openpic.h
+6 -19
View File
@@ -21,7 +21,6 @@ enum {
typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines;
#define OPENPIC_MODEL_RAVEN 0
#define OPENPIC_MODEL_FSL_MPIC_20 1
#define OPENPIC_MODEL_FSL_MPIC_42 2
#define OPENPIC_MODEL_KEYLARGO 3
@@ -32,13 +31,6 @@ typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines;
#define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \
OPENPIC_MAX_TMR)
/* Raven */
#define RAVEN_MAX_CPU 2
#define RAVEN_MAX_EXT 48
#define RAVEN_MAX_IRQ 64
#define RAVEN_MAX_TMR OPENPIC_MAX_TMR
#define RAVEN_MAX_IPI OPENPIC_MAX_IPI
/* KeyLargo */
#define KEYLARGO_MAX_CPU 4
#define KEYLARGO_MAX_EXT 64
@@ -49,14 +41,6 @@ typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines;
/* Timers don't exist but this makes the code happy... */
#define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI)
/* Interrupt definitions */
#define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
#define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
#define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
#define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
/* First doorbell IRQ */
#define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
typedef struct FslMpicInfo {
int max_ext;
} FslMpicInfo;
@@ -67,7 +51,8 @@ typedef enum IRQType {
IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
} IRQType;
/* Round up to the nearest 64 IRQs so that the queue length
/*
* Round up to the nearest 64 IRQs so that the queue length
* won't change when moving between 32 and 64 bit hosts.
*/
#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
@@ -117,8 +102,10 @@ typedef struct OpenPICTimer {
bool qemu_timer_active; /* Is the qemu_timer is running? */
struct QEMUTimer *qemu_timer;
struct OpenPICState *opp; /* Device timer is part of. */
/* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last
current_count written or read, only defined if qemu_timer_active. */
/*
* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last
* current_count written or read, only defined if qemu_timer_active.
*/
uint64_t origin_time;
} OpenPICTimer;
include/hw/ppc/pnv_core.h
+1 -1
View File
@@ -67,7 +67,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD)
struct PnvQuad {
DeviceState parent_obj;
uint32_t id;
uint32_t quad_id;
MemoryRegion xscom_regs;
};
#endif /* PPC_PNV_CORE_H */

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