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char: make some qemu_chr_fe skip if no driver

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In most cases, front ends do not care about the side effect of
CharBackend, so we can simply skip the checks and call the qemu_chr_fe
functions even without associated CharDriver.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20161022095318.17775-20-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Marc-André Lureau
2016-10-24 15:27:21 +02:00
committed by Paolo Bonzini
parent c39860e6dc
commit fa394ed625
22 changed files with 156 additions and 190 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/arm/pxa2xx.c
+3 -5
View File
@@ -1903,7 +1903,7 @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr,
} else {
ch = ~value;
}
if (s->chr.chr && s->enable && (s->control[0] & (1 << 3))) { /* TXE */
if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
@@ -1975,10 +1975,8 @@ static void pxa2xx_fir_realize(DeviceState *dev, Error **errp)
{
PXA2xxFIrState *s = PXA2XX_FIR(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty,
pxa2xx_fir_rx, pxa2xx_fir_event, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty,
pxa2xx_fir_rx, pxa2xx_fir_event, s, NULL);
}
static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id)
hw/arm/strongarm.c
+6 -10
View File
@@ -1020,9 +1020,7 @@ static void strongarm_uart_update_parameters(StrongARMUARTState *s)
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size;
if (s->chr.chr) {
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
speed, parity, data_bits, stop_bits);
@@ -1239,13 +1237,11 @@ static void strongarm_uart_init(Object *obj)
s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);
s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr,
strongarm_uart_can_receive,
strongarm_uart_receive,
strongarm_uart_event,
s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr,
strongarm_uart_can_receive,
strongarm_uart_receive,
strongarm_uart_event,
s, NULL);
}
static void strongarm_uart_reset(DeviceState *dev)
hw/char/bcm2835_aux.c
+6 -12
View File
@@ -79,9 +79,7 @@ static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
s->read_pos = 0;
}
}
if (s->chr.chr) {
qemu_chr_fe_accept_input(&s->chr);
}
qemu_chr_fe_accept_input(&s->chr);
bcm2835_aux_update(s);
return c;
@@ -168,11 +166,9 @@ static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value,
case AUX_MU_IO_REG:
/* "DLAB bit set means access baudrate register" is NYI */
ch = value;
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
break;
case AUX_MU_IER_REG:
@@ -282,10 +278,8 @@ static void bcm2835_aux_realize(DeviceState *dev, Error **errp)
{
BCM2835AuxState *s = BCM2835_AUX(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
bcm2835_aux_receive, NULL, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
bcm2835_aux_receive, NULL, s, NULL);
}
static Property bcm2835_aux_props[] = {
hw/char/cadence_uart.c
+7 -17
View File
@@ -142,9 +142,7 @@ static void uart_rx_reset(CadenceUARTState *s)
{
s->rx_wpos = 0;
s->rx_count = 0;
if (s->chr.chr) {
qemu_chr_fe_accept_input(&s->chr);
}
qemu_chr_fe_accept_input(&s->chr);
}
static void uart_tx_reset(CadenceUARTState *s)
@@ -156,10 +154,8 @@ static void uart_send_breaks(CadenceUARTState *s)
{
int break_enabled = 1;
if (s->chr.chr) {
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enabled);
}
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enabled);
}
static void uart_parameters_setup(CadenceUARTState *s)
@@ -210,9 +206,7 @@ static void uart_parameters_setup(CadenceUARTState *s)
packet_size += ssp.data_bits + ssp.stop_bits;
s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
if (s->chr.chr) {
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
static int uart_can_receive(void *opaque)
@@ -368,9 +362,7 @@ static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
*c = s->rx_fifo[rx_rpos];
s->rx_count--;
if (s->chr.chr) {
qemu_chr_fe_accept_input(&s->chr);
}
qemu_chr_fe_accept_input(&s->chr);
} else {
*c = 0;
}
@@ -474,10 +466,8 @@ static void cadence_uart_realize(DeviceState *dev, Error **errp)
s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
fifo_trigger_update, s);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
uart_event, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
uart_event, s, NULL);
}
static void cadence_uart_init(Object *obj)
hw/char/digic-uart.c
+5 -9
View File
@@ -76,11 +76,9 @@ static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,
switch (addr) {
case R_TX:
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
break;
case R_ST:
@@ -147,10 +145,8 @@ static void digic_uart_realize(DeviceState *dev, Error **errp)
{
DigicUartState *s = DIGIC_UART(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
static void digic_uart_init(Object *obj)
hw/char/escc.c
+1 -3
View File
@@ -599,9 +599,7 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr,
else
ret = s->rx;
trace_escc_mem_readb_data(CHN_C(s), ret);
if (s->chr.chr) {
qemu_chr_fe_accept_input(&s->chr);
}
qemu_chr_fe_accept_input(&s->chr);
return ret;
default:
break;
hw/char/etraxfs_ser.c
+3 -5
View File
@@ -231,11 +231,9 @@ static void etraxfs_ser_realize(DeviceState *dev, Error **errp)
{
ETRAXSerial *s = ETRAX_SERIAL(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr,
serial_can_receive, serial_receive,
serial_event, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr,
serial_can_receive, serial_receive,
serial_event, s, NULL);
}
static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
hw/char/imx_serial.c
+9 -17
View File
@@ -121,9 +121,7 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
s->usr2 &= ~USR2_RDR;
s->uts1 |= UTS1_RXEMPTY;
imx_update(s);
if (s->chr.chr) {
qemu_chr_fe_accept_input(&s->chr);
}
qemu_chr_fe_accept_input(&s->chr);
}
return c;
@@ -182,11 +180,9 @@ static void imx_serial_write(void *opaque, hwaddr offset,
case 0x10: /* UTXD */
ch = value;
if (s->ucr2 & UCR2_TXEN) {
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->usr1 &= ~USR1_TRDY;
imx_update(s);
s->usr1 |= USR1_TRDY;
@@ -215,9 +211,7 @@ static void imx_serial_write(void *opaque, hwaddr offset,
}
if (value & UCR2_RXEN) {
if (!(s->ucr2 & UCR2_RXEN)) {
if (s->chr.chr) {
qemu_chr_fe_accept_input(&s->chr);
}
qemu_chr_fe_accept_input(&s->chr);
}
}
s->ucr2 = value & 0xffff;
@@ -319,12 +313,10 @@ static void imx_serial_realize(DeviceState *dev, Error **errp)
{
IMXSerialState *s = IMX_SERIAL(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
imx_event, s, NULL);
} else {
DPRINTF("No char dev for uart\n");
}
DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));
qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
imx_event, s, NULL);
}
static void imx_serial_init(Object *obj)
hw/char/ipoctal232.c
+5 -9
View File
@@ -288,9 +288,7 @@ static uint16_t io_read(IPackDevice *ip, uint8_t addr)
if (ch->rx_pending == 0) {
ch->sr &= ~SR_RXRDY;
blk->isr &= ~ISR_RXRDY(channel);
if (ch->dev.chr) {
qemu_chr_fe_accept_input(&ch->dev);
}
qemu_chr_fe_accept_input(&ch->dev);
} else {
ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
}
@@ -357,13 +355,11 @@ static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
case REG_THRa:
case REG_THRb:
if (ch->sr & SR_TXRDY) {
uint8_t thr = reg;
DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
if (ch->dev.chr) {
uint8_t thr = reg;
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&ch->dev, &thr, 1);
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&ch->dev, &thr, 1);
} else {
DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
}
hw/char/lm32_juart.c
+5 -9
View File
@@ -75,11 +75,9 @@ void lm32_juart_set_jtx(DeviceState *d, uint32_t jtx)
trace_lm32_juart_set_jtx(s->jtx);
s->jtx = jtx;
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
void lm32_juart_set_jrx(DeviceState *d, uint32_t jtx)
@@ -120,10 +118,8 @@ static void lm32_juart_realize(DeviceState *dev, Error **errp)
{
LM32JuartState *s = LM32_JUART(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, juart_can_rx, juart_rx,
juart_event, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr, juart_can_rx, juart_rx,
juart_event, s, NULL);
}
static const VMStateDescription vmstate_lm32_juart = {
hw/char/lm32_uart.c
+5 -9
View File
@@ -177,11 +177,9 @@ static void uart_write(void *opaque, hwaddr addr,
addr >>= 2;
switch (addr) {
case R_RXTX:
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
break;
case R_IER:
case R_LCR:
@@ -267,10 +265,8 @@ static void lm32_uart_realize(DeviceState *dev, Error **errp)
{
LM32UartState *s = LM32_UART(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
static const VMStateDescription vmstate_lm32_uart = {
hw/char/mcf_uart.c
+3 -5
View File
@@ -114,11 +114,9 @@ uint64_t mcf_uart_read(void *opaque, hwaddr addr,
static void mcf_uart_do_tx(mcf_uart_state *s)
{
if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
s->sr |= MCF_UART_TxEMP;
}
if (s->tx_enabled) {
hw/char/milkymist-uart.c
+3 -7
View File
@@ -124,9 +124,7 @@ static void uart_write(void *opaque, hwaddr addr, uint64_t value,
addr >>= 2;
switch (addr) {
case R_RXTX:
if (s->chr.chr) {
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->regs[R_STAT] |= STAT_TX_EVT;
break;
case R_DIV:
@@ -200,10 +198,8 @@ static void milkymist_uart_realize(DeviceState *dev, Error **errp)
{
MilkymistUartState *s = MILKYMIST_UART(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
static void milkymist_uart_init(Object *obj)
hw/char/pl011.c
+6 -12
View File
@@ -87,9 +87,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
trace_pl011_read_fifo(s->read_count);
s->rsr = c >> 8;
pl011_update(s);
if (s->chr.chr) {
qemu_chr_fe_accept_input(&s->chr);
}
qemu_chr_fe_accept_input(&s->chr);
r = c;
break;
case 1: /* UARTRSR */
@@ -168,11 +166,9 @@ static void pl011_write(void *opaque, hwaddr offset,
case 0: /* UARTDR */
/* ??? Check if transmitter is enabled. */
ch = value;
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->int_level |= PL011_INT_TX;
pl011_update(s);
break;
@@ -332,10 +328,8 @@ static void pl011_realize(DeviceState *dev, Error **errp)
{
PL011State *s = PL011(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive,
pl011_event, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive,
pl011_event, s, NULL);
}
static void pl011_class_init(ObjectClass *oc, void *data)
hw/char/sclpconsole-lm.c
+2 -4
View File
@@ -312,10 +312,8 @@ static int console_init(SCLPEvent *event)
}
console_available = true;
if (scon->chr.chr) {
qemu_chr_fe_set_handlers(&scon->chr, chr_can_read,
chr_read, NULL, scon, NULL);
}
qemu_chr_fe_set_handlers(&scon->chr, chr_can_read,
chr_read, NULL, scon, NULL);
return 0;
}
hw/char/sclpconsole.c
+2 -4
View File
@@ -227,10 +227,8 @@ static int console_init(SCLPEvent *event)
return -1;
}
console_available = true;
if (scon->chr.chr) {
qemu_chr_fe_set_handlers(&scon->chr, chr_can_read,
chr_read, NULL, scon, NULL);
}
qemu_chr_fe_set_handlers(&scon->chr, chr_can_read,
chr_read, NULL, scon, NULL);
return 0;
}
hw/char/stm32f2xx_usart.c
+7 -15
View File
@@ -97,17 +97,13 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
case USART_SR:
retvalue = s->usart_sr;
s->usart_sr &= ~USART_SR_TC;
if (s->chr.chr) {
qemu_chr_fe_accept_input(&s->chr);
}
qemu_chr_fe_accept_input(&s->chr);
return retvalue;
case USART_DR:
DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
s->usart_sr |= USART_SR_TXE;
s->usart_sr &= ~USART_SR_RXNE;
if (s->chr.chr) {
qemu_chr_fe_accept_input(&s->chr);
}
qemu_chr_fe_accept_input(&s->chr);
qemu_set_irq(s->irq, 0);
return s->usart_dr & 0x3FF;
case USART_BRR:
@@ -152,11 +148,9 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
case USART_DR:
if (value < 0xF000) {
ch = value;
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->usart_sr |= USART_SR_TC;
s->usart_sr &= ~USART_SR_TXE;
}
@@ -212,10 +206,8 @@ static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp)
{
STM32F2XXUsartState *s = STM32F2XX_USART(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive,
stm32f2xx_usart_receive, NULL, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive,
stm32f2xx_usart_receive, NULL, s, NULL);
}
static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
hw/char/virtio-console.c
+2 -4
View File
@@ -108,7 +108,7 @@ static void set_guest_connected(VirtIOSerialPort *port, int guest_connected)
DeviceState *dev = DEVICE(port);
VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_GET_CLASS(port);
if (vcon->chr.chr && !k->is_console) {
if (!k->is_console) {
qemu_chr_fe_set_open(&vcon->chr, guest_connected);
}
@@ -122,9 +122,7 @@ static void guest_writable(VirtIOSerialPort *port)
{
VirtConsole *vcon = VIRTIO_CONSOLE(port);
if (vcon->chr.chr) {
qemu_chr_fe_accept_input(&vcon->chr);
}
qemu_chr_fe_accept_input(&vcon->chr);
}
/* Readiness of the guest to accept data on a port */
hw/char/xen_console.c
+2 -4
View File
@@ -244,10 +244,8 @@ static int con_initialise(struct XenDevice *xendev)
return -1;
xen_be_bind_evtchn(&con->xendev);
if (con->chr.chr) {
qemu_chr_fe_set_handlers(&con->chr, xencons_can_receive,
xencons_receive, NULL, con, NULL);
}
qemu_chr_fe_set_handlers(&con->chr, xencons_can_receive,
xencons_receive, NULL, con, NULL);
xen_be_printf(xendev, 1, "ring mfn %d, remote port %d, local port %d, limit %zd\n",
con->ring_ref,
hw/char/xilinx_uartlite.c
+5 -9
View File
@@ -143,11 +143,9 @@ uart_write(void *opaque, hwaddr addr,
break;
case R_TX:
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->regs[addr] = value;
/* hax. */
@@ -213,10 +211,8 @@ static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
{
XilinxUARTLite *s = XILINX_UARTLITE(dev);
if (s->chr.chr) {
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
static void xilinx_uartlite_init(Object *obj)

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