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target/ppc: Add IBM PPE42 special instructions

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Adds the following instructions exclusively for
IBM PPE42 processors:

  LSKU
  LCXU
  STSKU
  STCXU
  LVD
  LVDU
  LVDX
  STVD
  STVDU
  STVDX
  SLVD
  SRVD
  CMPWBC
  CMPLWBC
  CMPWIBC
  BNBWI
  BNBW
  CLRBWIBC
  CLRWBC
  DCBQ
  RLDICL
  RLDICR
  RLDIMI

A PPE42 GCC compiler is available here:
https://github.com/open-power/ppe42-gcc

For more information on the PPE42 processors please visit:
https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf

Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/20250925201758.652077-7-milesg@linux.ibm.com
Message-ID: <20250925201758.652077-7-milesg@linux.ibm.com>
This commit is contained in:
Glenn Miles
2025-09-28 23:36:13 +05:30
committed by Harsh Prateek Bora
parent 880aa4cb06
commit f7ec91c239
3 changed files with 694 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/ppc/insn32.decode
+62 -4
View File
@@ -58,6 +58,10 @@
%ds_rtp 22:4 !function=times_2
@DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si
%dd_si 3:s13
&DD rt ra si:int64_t
@DD ...... rt:5 ra:5 ............. . .. &DD si=%dd_si
&DX_b vrt b
%dx_b 6:10 16:5 0:1
@DX_b ...... vrt:5 ..... .......... ..... . &DX_b b=%dx_b
@@ -66,6 +70,11 @@
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
%md_sh 1:1 11:5
%md_mb 5:1 6:5
&MD rs ra sh mb rc
@MD ...... rs:5 ra:5 ..... ...... ... . rc:1 &MD sh=%md_sh mb=%md_mb
&VA vrt vra vrb rc
@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
@@ -322,6 +331,13 @@ LDUX 011111 ..... ..... ..... 0000110101 - @X
LQ 111000 ..... ..... ............ ---- @DQ_rtp
LVD 000101 ..... ..... ................ @D
LVDU 001001 ..... ..... ................ @D
LVDX 011111 ..... ..... ..... 0000010001 - @X
LSKU 111010 ..... ..... ............. 0 11 @DD
LCXU 111010 ..... ..... ............. 1 11 @DD
### Fixed-Point Store Instructions
STB 100110 ..... ..... ................ @D
@@ -346,6 +362,11 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
STQ 111110 ..... ..... ..............10 @DS_rtp
STVDU 010110 ..... ..... ................ @D
STVDX 011111 ..... ..... ..... 0010010001 - @X
STSKU 111110 ..... ..... ............. 0 11 @DD
STCXU 111110 ..... ..... ............. 1 11 @DD
### Fixed-Point Compare Instructions
CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
@@ -461,8 +482,14 @@ PRTYD 011111 ..... ..... ----- 0010111010 - @X_sa
BPERMD 011111 ..... ..... ..... 0011111100 - @X
CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
{
SLVD 011111 ..... ..... ..... 0000111011 . @X_rc
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
}
{
SRVD 011111 ..... ..... ..... 1000111011 . @X_rc
CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
}
PDEPD 011111 ..... ..... ..... 0010011100 - @X
PEXTD 011111 ..... ..... ..... 0010111100 - @X
@@ -981,8 +1008,16 @@ LXSSP 111001 ..... ..... .............. 11 @DS
STXSSP 111101 ..... ..... .............. 11 @DS
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
STXVP 000110 ..... ..... ............ 0001 @DQ_TSXP
# STVD PPE instruction overlaps with the LXVP and STXVP instructions
{
STVD 000110 ..... ..... ................ @D
[
LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
STXVP 000110 ..... ..... ............ 0001 @DQ_TSXP
]
}
LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
@@ -1300,3 +1335,26 @@ CLRBHRB 011111 ----- ----- ----- 0110101110 -
## Misc POWER instructions
ATTN 000000 00000 00000 00000 0100000000 0
# Fused compare-branch instructions for PPE only
%fcb_bdx 1:s10 !function=times_4
&FCB px:bool ra rb:uint64_t bdx lk:bool
@FCB ...... .. px:1 .. ra:5 rb:5 .......... lk:1 &FCB bdx=%fcb_bdx
&FCB_bix px:bool bix ra rb:uint64_t bdx lk:bool
@FCB_bix ...... .. px:1 bix:2 ra:5 rb:5 .......... lk:1 &FCB_bix bdx=%fcb_bdx
CMPWBC 000001 00 . .. ..... ..... .......... . @FCB_bix
CMPLWBC 000001 01 . .. ..... ..... .......... . @FCB_bix
CMPWIBC 000001 10 . .. ..... ..... .......... . @FCB_bix
BNBWI 000001 11 . 00 ..... ..... .......... . @FCB
BNBW 000001 11 . 01 ..... ..... .......... . @FCB
CLRBWIBC 000001 11 . 10 ..... ..... .......... . @FCB
CLRBWBC 000001 11 . 11 ..... ..... .......... . @FCB
# Data Cache Block Query for PPE only
DCBQ 011111 ..... ..... ..... 0110010110 - @X
# Rotate Doubleword Instructions for PPE only
RLDICL 011110 ..... ..... ..... ...... 000 . . @MD
RLDICR 011110 ..... ..... ..... ...... 001 . . @MD
RLDIMI 011110 ..... ..... ..... ...... 011 . . @MD
target/ppc/translate.c
+23 -6
View File
@@ -209,6 +209,11 @@ struct DisasContext {
#define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */
#define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */
static inline bool is_ppe(const DisasContext *ctx)
{
return !!(ctx->flags & POWERPC_FLAG_PPE42);
}
/* Return true iff byteswap is needed in a scalar memop */
static inline bool need_byteswap(const DisasContext *ctx)
{
@@ -556,11 +561,8 @@ void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
#endif
/* SPR common to all PowerPC */
/* XER */
void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
static void gen_get_xer(DisasContext *ctx, TCGv dst)
{
TCGv dst = cpu_gpr[gprn];
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
@@ -579,9 +581,16 @@ void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
}
}
void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
/* SPR common to all PowerPC */
/* XER */
void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
{
TCGv dst = cpu_gpr[gprn];
gen_get_xer(ctx, dst);
}
static void gen_set_xer(DisasContext *ctx, TCGv src)
{
TCGv src = cpu_gpr[gprn];
/* Write all flags, while reading back check for isa300 */
tcg_gen_andi_tl(cpu_xer, src,
~((1u << XER_SO) |
@@ -594,6 +603,12 @@ void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
}
void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
{
TCGv src = cpu_gpr[gprn];
gen_set_xer(ctx, src);
}
/* LR */
void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
{
@@ -5755,6 +5770,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
#include "translate/bhrb-impl.c.inc"
#include "translate/ppe-impl.c.inc"
/* Handles lfdp */
static void gen_dform39(DisasContext *ctx)
{
target/ppc/translate/ppe-impl.c.inc
+609
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