mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-smm' into staging
This series implements KVM support for SMM, and lets you enable/disable it through the "smm" property of x86 machine types. # gpg: Signature made Mon Jul 6 17:41:05 2015 BST using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream-smm: pc: add SMM property ich9: add smm_enabled field and arguments pc_piix: rename kvm_enabled to smm_enabled target-i386: register a separate KVM address space including SMRAM regions kvm-all: kvm_irqchip_create is not expected to fail kvm-all: add support for multiple address spaces kvm-all: make KVM's memory listener more generic kvm-all: move internal types to kvm_int.h kvm-all: remove useless typedef kvm-all: put kvm_mem_flags to more work target-i386: add support for SMBASE MSR and SMIs piix4/ich9: do not raise SMI on ACPI enable/disable commands linux-headers: Update to 4.2-rc1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
+3
-2
@@ -192,7 +192,7 @@ static void pm_reset(void *opaque)
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acpi_pm_tmr_reset(&pm->acpi_regs);
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acpi_gpe_reset(&pm->acpi_regs);
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if (kvm_enabled()) {
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if (!pm->smm_enabled) {
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
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* support SMM mode. */
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pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
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@@ -209,7 +209,7 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
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acpi_pm1_evt_power_down(&pm->acpi_regs);
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}
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void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
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void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, bool smm_enabled,
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qemu_irq sci_irq)
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{
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memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
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@@ -231,6 +231,7 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
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"acpi-smi", 8);
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memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
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pm->smm_enabled = smm_enabled;
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pm->irq = sci_irq;
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qemu_register_reset(pm_reset, pm);
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pm->powerdown_notifier.notify = pm_powerdown_req;
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+8
-5
@@ -72,7 +72,7 @@ typedef struct PIIX4PMState {
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qemu_irq irq;
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qemu_irq smi_irq;
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int kvm_enabled;
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int smm_enabled;
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Notifier machine_ready;
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Notifier powerdown_notifier;
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@@ -112,6 +112,9 @@ static void apm_ctrl_changed(uint32_t val, void *arg)
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/* ACPI specs 3.0, 4.7.2.5 */
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acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
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if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
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return;
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}
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if (d->config[0x5b] & (1 << 1)) {
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if (s->smi_irq) {
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@@ -319,7 +322,7 @@ static void piix4_reset(void *opaque)
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pci_conf[0x40] = 0x01; /* PM io base read only bit */
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pci_conf[0x80] = 0;
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if (s->kvm_enabled) {
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if (!s->smm_enabled) {
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/* Mark SMM as already inited (until KVM supports SMM). */
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pci_conf[0x5B] = 0x02;
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}
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@@ -450,7 +453,7 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp)
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/* APM */
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apm_init(dev, &s->apm, apm_ctrl_changed, s);
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if (s->kvm_enabled) {
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if (!s->smm_enabled) {
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
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* support SMM mode. */
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pci_conf[0x5B] = 0x02;
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@@ -501,7 +504,7 @@ Object *piix4_pm_find(void)
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I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq, qemu_irq smi_irq,
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int kvm_enabled, DeviceState **piix4_pm)
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int smm_enabled, DeviceState **piix4_pm)
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{
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DeviceState *dev;
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PIIX4PMState *s;
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@@ -515,7 +518,7 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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s = PIIX4_PM(dev);
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s->irq = sci_irq;
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s->smi_irq = smi_irq;
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s->kvm_enabled = kvm_enabled;
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s->smm_enabled = smm_enabled;
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if (xen_enabled()) {
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s->use_acpi_pci_hotplug = false;
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}
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@@ -1768,6 +1768,48 @@ static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque,
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visit_type_OnOffAuto(v, &pcms->vmport, name, errp);
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}
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bool pc_machine_is_smm_enabled(PCMachineState *pcms)
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{
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bool smm_available = false;
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if (pcms->smm == ON_OFF_AUTO_OFF) {
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return false;
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}
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if (tcg_enabled() || qtest_enabled()) {
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smm_available = true;
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} else if (kvm_enabled()) {
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smm_available = kvm_has_smm();
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}
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if (smm_available) {
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return true;
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}
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if (pcms->smm == ON_OFF_AUTO_ON) {
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error_report("System Management Mode not supported by this hypervisor.");
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exit(1);
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}
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return false;
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}
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static void pc_machine_get_smm(Object *obj, Visitor *v, void *opaque,
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const char *name, Error **errp)
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{
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PCMachineState *pcms = PC_MACHINE(obj);
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OnOffAuto smm = pcms->smm;
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visit_type_OnOffAuto(v, &smm, name, errp);
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}
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static void pc_machine_set_smm(Object *obj, Visitor *v, void *opaque,
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const char *name, Error **errp)
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{
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PCMachineState *pcms = PC_MACHINE(obj);
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visit_type_OnOffAuto(v, &pcms->smm, name, errp);
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}
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static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp)
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{
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PCMachineState *pcms = PC_MACHINE(obj);
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@@ -1792,6 +1834,15 @@ static void pc_machine_initfn(Object *obj)
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"Maximum ram below the 4G boundary (32bit boundary)",
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NULL);
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pcms->smm = ON_OFF_AUTO_AUTO;
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object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto",
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pc_machine_get_smm,
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pc_machine_set_smm,
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NULL, NULL, NULL);
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object_property_set_description(obj, PC_MACHINE_SMM,
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"Enable SMM (pc & q35)",
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NULL);
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pcms->vmport = ON_OFF_AUTO_AUTO;
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object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto",
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pc_machine_get_vmport,
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+6
-1
@@ -287,7 +287,8 @@ static void pc_init1(MachineState *machine)
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/* TODO: Populate SPD eeprom data. */
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smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
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gsi[9], smi_irq,
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kvm_enabled(), &piix4_pm);
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pc_machine_is_smm_enabled(pc_machine),
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&piix4_pm);
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smbus_eeprom_init(smbus, 8, NULL, 0);
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object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
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@@ -306,7 +307,11 @@ static void pc_init1(MachineState *machine)
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static void pc_compat_2_3(MachineState *machine)
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{
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PCMachineState *pcms = PC_MACHINE(machine);
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savevm_skip_section_footers();
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if (kvm_enabled()) {
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pcms->smm = ON_OFF_AUTO_OFF;
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}
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}
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static void pc_compat_2_2(MachineState *machine)
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+5
-1
@@ -253,7 +253,7 @@ static void pc_q35_init(MachineState *machine)
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(pc_machine->vmport != ON_OFF_AUTO_ON), 0xff0104);
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/* connect pm stuff to lpc */
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ich9_lpc_pm_init(lpc);
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ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pc_machine));
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/* ahci and SATA device, for q35 1 ahci controller is built-in */
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ahci = pci_create_simple_multifunction(host_bus,
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@@ -290,7 +290,11 @@ static void pc_q35_init(MachineState *machine)
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static void pc_compat_2_3(MachineState *machine)
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{
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PCMachineState *pcms = PC_MACHINE(machine);
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savevm_skip_section_footers();
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if (kvm_enabled()) {
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pcms->smm = ON_OFF_AUTO_OFF;
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}
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}
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static void pc_compat_2_2(MachineState *machine)
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+7
-2
@@ -357,11 +357,13 @@ static void ich9_set_sci(void *opaque, int irq_num, int level)
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}
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}
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void ich9_lpc_pm_init(PCIDevice *lpc_pci)
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void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
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{
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ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
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qemu_irq sci_irq;
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ich9_pm_init(lpc_pci, &lpc->pm, qemu_allocate_irq(ich9_set_sci, lpc, 0));
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sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
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ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
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ich9_lpc_reset(&lpc->d.qdev);
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}
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@@ -375,6 +377,9 @@ static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
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acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
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val == ICH9_APM_ACPI_ENABLE,
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val == ICH9_APM_ACPI_DISABLE);
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if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) {
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return;
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}
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/* SMI_EN = PMBASE + 30. SMI control and enable register */
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if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
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@@ -54,10 +54,11 @@ typedef struct ICH9LPCPMRegs {
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uint8_t disable_s3;
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uint8_t disable_s4;
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uint8_t s4_val;
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uint8_t smm_enabled;
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} ICH9LPCPMRegs;
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void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
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qemu_irq sci_irq);
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bool smm_enabled, qemu_irq sci_irq);
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void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
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extern const VMStateDescription vmstate_ich9_pm;
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@@ -17,7 +17,7 @@
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void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
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int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
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PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
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void ich9_lpc_pm_init(PCIDevice *pci_lpc);
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void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
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I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
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#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
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@@ -37,6 +37,7 @@ struct PCMachineState {
|
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|
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uint64_t max_ram_below_4g;
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OnOffAuto vmport;
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OnOffAuto smm;
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bool enforce_aligned_dimm;
|
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};
|
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|
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@@ -44,6 +45,7 @@ struct PCMachineState {
|
||||
#define PC_MACHINE_MEMHP_REGION_SIZE "hotplug-memory-region-size"
|
||||
#define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
|
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#define PC_MACHINE_VMPORT "vmport"
|
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#define PC_MACHINE_SMM "smm"
|
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#define PC_MACHINE_ENFORCE_ALIGNED_DIMM "enforce-aligned-dimm"
|
||||
|
||||
/**
|
||||
@@ -155,6 +157,7 @@ void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
|
||||
/* pc.c */
|
||||
extern int fd_bootchk;
|
||||
|
||||
bool pc_machine_is_smm_enabled(PCMachineState *pcms);
|
||||
void pc_register_ferr_irq(qemu_irq irq);
|
||||
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
|
||||
|
||||
@@ -214,7 +217,7 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
|
||||
|
||||
I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
||||
qemu_irq sci_irq, qemu_irq smi_irq,
|
||||
int kvm_enabled, DeviceState **piix4_pm);
|
||||
int smm_enabled, DeviceState **piix4_pm);
|
||||
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
|
||||
|
||||
/* hpet.c */
|
||||
|
||||
@@ -367,7 +367,8 @@ struct input_keymap_entry {
|
||||
#define KEY_MSDOS 151
|
||||
#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
|
||||
#define KEY_SCREENLOCK KEY_COFFEE
|
||||
#define KEY_DIRECTION 153
|
||||
#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */
|
||||
#define KEY_DIRECTION KEY_ROTATE_DISPLAY
|
||||
#define KEY_CYCLEWINDOWS 154
|
||||
#define KEY_MAIL 155
|
||||
#define KEY_BOOKMARKS 156 /* AC Bookmarks */
|
||||
@@ -700,6 +701,10 @@ struct input_keymap_entry {
|
||||
#define KEY_NUMERIC_9 0x209
|
||||
#define KEY_NUMERIC_STAR 0x20a
|
||||
#define KEY_NUMERIC_POUND 0x20b
|
||||
#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */
|
||||
#define KEY_NUMERIC_B 0x20d
|
||||
#define KEY_NUMERIC_C 0x20e
|
||||
#define KEY_NUMERIC_D 0x20f
|
||||
|
||||
#define KEY_CAMERA_FOCUS 0x210
|
||||
#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */
|
||||
@@ -971,7 +976,8 @@ struct input_keymap_entry {
|
||||
*/
|
||||
#define MT_TOOL_FINGER 0
|
||||
#define MT_TOOL_PEN 1
|
||||
#define MT_TOOL_MAX 1
|
||||
#define MT_TOOL_PALM 2
|
||||
#define MT_TOOL_MAX 2
|
||||
|
||||
/*
|
||||
* Values describing the status of a force-feedback effect
|
||||
|
||||
@@ -26,6 +26,7 @@
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE. */
|
||||
#include "standard-headers/linux/types.h"
|
||||
#include "standard-headers/linux/virtio_types.h"
|
||||
#include "standard-headers/linux/virtio_ids.h"
|
||||
#include "standard-headers/linux/virtio_config.h"
|
||||
|
||||
|
||||
@@ -38,6 +38,8 @@
|
||||
#ifndef VIRTIO_GPU_HW_H
|
||||
#define VIRTIO_GPU_HW_H
|
||||
|
||||
#include "standard-headers/linux/types.h"
|
||||
|
||||
enum virtio_gpu_ctrl_type {
|
||||
VIRTIO_GPU_UNDEFINED = 0,
|
||||
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Internal definitions for a target's KVM support
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef QEMU_KVM_INT_H
|
||||
#define QEMU_KVM_INT_H
|
||||
|
||||
#include "sysemu/sysemu.h"
|
||||
#include "sysemu/accel.h"
|
||||
#include "sysemu/kvm.h"
|
||||
|
||||
typedef struct KVMSlot
|
||||
{
|
||||
hwaddr start_addr;
|
||||
ram_addr_t memory_size;
|
||||
void *ram;
|
||||
int slot;
|
||||
int flags;
|
||||
} KVMSlot;
|
||||
|
||||
typedef struct KVMMemoryListener {
|
||||
MemoryListener listener;
|
||||
KVMSlot *slots;
|
||||
int as_id;
|
||||
} KVMMemoryListener;
|
||||
|
||||
#define TYPE_KVM_ACCEL ACCEL_CLASS_NAME("kvm")
|
||||
|
||||
#define KVM_STATE(obj) \
|
||||
OBJECT_CHECK(KVMState, (obj), TYPE_KVM_ACCEL)
|
||||
|
||||
void kvm_memory_listener_register(KVMState *s, KVMMemoryListener *kml,
|
||||
AddressSpace *as, int as_id);
|
||||
|
||||
#endif
|
||||
@@ -199,6 +199,17 @@
|
||||
#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
|
||||
#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
|
||||
|
||||
/* Hyper-V guest crash notification MSR's */
|
||||
#define HV_X64_MSR_CRASH_P0 0x40000100
|
||||
#define HV_X64_MSR_CRASH_P1 0x40000101
|
||||
#define HV_X64_MSR_CRASH_P2 0x40000102
|
||||
#define HV_X64_MSR_CRASH_P3 0x40000103
|
||||
#define HV_X64_MSR_CRASH_P4 0x40000104
|
||||
#define HV_X64_MSR_CRASH_CTL 0x40000105
|
||||
#define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63)
|
||||
#define HV_X64_MSR_CRASH_PARAMS \
|
||||
(1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
|
||||
|
||||
#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
|
||||
#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
|
||||
#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
|
||||
|
||||
@@ -897,7 +897,7 @@ struct kvm_xen_hvm_config {
|
||||
*
|
||||
* KVM_IRQFD_FLAG_RESAMPLE indicates resamplefd is valid and specifies
|
||||
* the irqfd to operate in resampling mode for level triggered interrupt
|
||||
* emlation. See Documentation/virtual/kvm/api.txt.
|
||||
* emulation. See Documentation/virtual/kvm/api.txt.
|
||||
*/
|
||||
#define KVM_IRQFD_FLAG_RESAMPLE (1 << 1)
|
||||
|
||||
|
||||
@@ -36,6 +36,8 @@
|
||||
/* Two-stage IOMMU */
|
||||
#define VFIO_TYPE1_NESTING_IOMMU 6 /* Implies v2 */
|
||||
|
||||
#define VFIO_SPAPR_TCE_v2_IOMMU 7
|
||||
|
||||
/*
|
||||
* The IOCTL interface is designed for extensibility by embedding the
|
||||
* structure length (argsz) and flags into structures passed between
|
||||
@@ -442,6 +444,23 @@ struct vfio_iommu_type1_dma_unmap {
|
||||
|
||||
/* -------- Additional API for SPAPR TCE (Server POWERPC) IOMMU -------- */
|
||||
|
||||
/*
|
||||
* The SPAPR TCE DDW info struct provides the information about
|
||||
* the details of Dynamic DMA window capability.
|
||||
*
|
||||
* @pgsizes contains a page size bitmask, 4K/64K/16M are supported.
|
||||
* @max_dynamic_windows_supported tells the maximum number of windows
|
||||
* which the platform can create.
|
||||
* @levels tells the maximum number of levels in multi-level IOMMU tables;
|
||||
* this allows splitting a table into smaller chunks which reduces
|
||||
* the amount of physically contiguous memory required for the table.
|
||||
*/
|
||||
struct vfio_iommu_spapr_tce_ddw_info {
|
||||
__u64 pgsizes; /* Bitmap of supported page sizes */
|
||||
__u32 max_dynamic_windows_supported;
|
||||
__u32 levels;
|
||||
};
|
||||
|
||||
/*
|
||||
* The SPAPR TCE info struct provides the information about the PCI bus
|
||||
* address ranges available for DMA, these values are programmed into
|
||||
@@ -452,14 +471,17 @@ struct vfio_iommu_type1_dma_unmap {
|
||||
* addresses too so the window works as a filter rather than an offset
|
||||
* for IOVA addresses.
|
||||
*
|
||||
* A flag will need to be added if other page sizes are supported,
|
||||
* so as defined here, it is always 4k.
|
||||
* Flags supported:
|
||||
* - VFIO_IOMMU_SPAPR_INFO_DDW: informs the userspace that dynamic DMA windows
|
||||
* (DDW) support is present. @ddw is only supported when DDW is present.
|
||||
*/
|
||||
struct vfio_iommu_spapr_tce_info {
|
||||
__u32 argsz;
|
||||
__u32 flags; /* reserved for future use */
|
||||
__u32 flags;
|
||||
#define VFIO_IOMMU_SPAPR_INFO_DDW (1 << 0) /* DDW supported */
|
||||
__u32 dma32_window_start; /* 32 bit window start (bytes) */
|
||||
__u32 dma32_window_size; /* 32 bit window size (bytes) */
|
||||
struct vfio_iommu_spapr_tce_ddw_info ddw;
|
||||
};
|
||||
|
||||
#define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12)
|
||||
@@ -470,12 +492,23 @@ struct vfio_iommu_spapr_tce_info {
|
||||
* - unfreeze IO/DMA for frozen PE;
|
||||
* - read PE state;
|
||||
* - reset PE;
|
||||
* - configure PE.
|
||||
* - configure PE;
|
||||
* - inject EEH error.
|
||||
*/
|
||||
struct vfio_eeh_pe_err {
|
||||
__u32 type;
|
||||
__u32 func;
|
||||
__u64 addr;
|
||||
__u64 mask;
|
||||
};
|
||||
|
||||
struct vfio_eeh_pe_op {
|
||||
__u32 argsz;
|
||||
__u32 flags;
|
||||
__u32 op;
|
||||
union {
|
||||
struct vfio_eeh_pe_err err;
|
||||
};
|
||||
};
|
||||
|
||||
#define VFIO_EEH_PE_DISABLE 0 /* Disable EEH functionality */
|
||||
@@ -492,9 +525,70 @@ struct vfio_eeh_pe_op {
|
||||
#define VFIO_EEH_PE_RESET_HOT 6 /* Assert hot reset */
|
||||
#define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 /* Assert fundamental reset */
|
||||
#define VFIO_EEH_PE_CONFIGURE 8 /* PE configuration */
|
||||
#define VFIO_EEH_PE_INJECT_ERR 9 /* Inject EEH error */
|
||||
|
||||
#define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21)
|
||||
|
||||
/**
|
||||
* VFIO_IOMMU_SPAPR_REGISTER_MEMORY - _IOW(VFIO_TYPE, VFIO_BASE + 17, struct vfio_iommu_spapr_register_memory)
|
||||
*
|
||||
* Registers user space memory where DMA is allowed. It pins
|
||||
* user pages and does the locked memory accounting so
|
||||
* subsequent VFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA calls
|
||||
* get faster.
|
||||
*/
|
||||
struct vfio_iommu_spapr_register_memory {
|
||||
__u32 argsz;
|
||||
__u32 flags;
|
||||
__u64 vaddr; /* Process virtual address */
|
||||
__u64 size; /* Size of mapping (bytes) */
|
||||
};
|
||||
#define VFIO_IOMMU_SPAPR_REGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 17)
|
||||
|
||||
/**
|
||||
* VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY - _IOW(VFIO_TYPE, VFIO_BASE + 18, struct vfio_iommu_spapr_register_memory)
|
||||
*
|
||||
* Unregisters user space memory registered with
|
||||
* VFIO_IOMMU_SPAPR_REGISTER_MEMORY.
|
||||
* Uses vfio_iommu_spapr_register_memory for parameters.
|
||||
*/
|
||||
#define VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 18)
|
||||
|
||||
/**
|
||||
* VFIO_IOMMU_SPAPR_TCE_CREATE - _IOWR(VFIO_TYPE, VFIO_BASE + 19, struct vfio_iommu_spapr_tce_create)
|
||||
*
|
||||
* Creates an additional TCE table and programs it (sets a new DMA window)
|
||||
* to every IOMMU group in the container. It receives page shift, window
|
||||
* size and number of levels in the TCE table being created.
|
||||
*
|
||||
* It allocates and returns an offset on a PCI bus of the new DMA window.
|
||||
*/
|
||||
struct vfio_iommu_spapr_tce_create {
|
||||
__u32 argsz;
|
||||
__u32 flags;
|
||||
/* in */
|
||||
__u32 page_shift;
|
||||
__u64 window_size;
|
||||
__u32 levels;
|
||||
/* out */
|
||||
__u64 start_addr;
|
||||
};
|
||||
#define VFIO_IOMMU_SPAPR_TCE_CREATE _IO(VFIO_TYPE, VFIO_BASE + 19)
|
||||
|
||||
/**
|
||||
* VFIO_IOMMU_SPAPR_TCE_REMOVE - _IOW(VFIO_TYPE, VFIO_BASE + 20, struct vfio_iommu_spapr_tce_remove)
|
||||
*
|
||||
* Unprograms a TCE table from all groups in the container and destroys it.
|
||||
* It receives a PCI bus offset as a window id.
|
||||
*/
|
||||
struct vfio_iommu_spapr_tce_remove {
|
||||
__u32 argsz;
|
||||
__u32 flags;
|
||||
/* in */
|
||||
__u64 start_addr;
|
||||
};
|
||||
#define VFIO_IOMMU_SPAPR_TCE_REMOVE _IO(VFIO_TYPE, VFIO_BASE + 20)
|
||||
|
||||
/* ***************************************************************** */
|
||||
|
||||
#endif /* VFIO_H */
|
||||
|
||||
@@ -1,192 +0,0 @@
|
||||
/*
|
||||
* Virtio PCI driver
|
||||
*
|
||||
* This module allows virtio devices to be used over a virtual PCI device.
|
||||
* This can be used with QEMU based VMMs like KVM or Xen.
|
||||
*
|
||||
* Copyright IBM Corp. 2007
|
||||
*
|
||||
* Authors:
|
||||
* Anthony Liguori <aliguori@us.ibm.com>
|
||||
*
|
||||
* This header is BSD licensed so anyone can use the definitions to implement
|
||||
* compatible drivers/servers.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of IBM nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_VIRTIO_PCI_H
|
||||
#define _LINUX_VIRTIO_PCI_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#ifndef VIRTIO_PCI_NO_LEGACY
|
||||
|
||||
/* A 32-bit r/o bitmask of the features supported by the host */
|
||||
#define VIRTIO_PCI_HOST_FEATURES 0
|
||||
|
||||
/* A 32-bit r/w bitmask of features activated by the guest */
|
||||
#define VIRTIO_PCI_GUEST_FEATURES 4
|
||||
|
||||
/* A 32-bit r/w PFN for the currently selected queue */
|
||||
#define VIRTIO_PCI_QUEUE_PFN 8
|
||||
|
||||
/* A 16-bit r/o queue size for the currently selected queue */
|
||||
#define VIRTIO_PCI_QUEUE_NUM 12
|
||||
|
||||
/* A 16-bit r/w queue selector */
|
||||
#define VIRTIO_PCI_QUEUE_SEL 14
|
||||
|
||||
/* A 16-bit r/w queue notifier */
|
||||
#define VIRTIO_PCI_QUEUE_NOTIFY 16
|
||||
|
||||
/* An 8-bit device status register. */
|
||||
#define VIRTIO_PCI_STATUS 18
|
||||
|
||||
/* An 8-bit r/o interrupt status register. Reading the value will return the
|
||||
* current contents of the ISR and will also clear it. This is effectively
|
||||
* a read-and-acknowledge. */
|
||||
#define VIRTIO_PCI_ISR 19
|
||||
|
||||
/* MSI-X registers: only enabled if MSI-X is enabled. */
|
||||
/* A 16-bit vector for configuration changes. */
|
||||
#define VIRTIO_MSI_CONFIG_VECTOR 20
|
||||
/* A 16-bit vector for selected queue notifications. */
|
||||
#define VIRTIO_MSI_QUEUE_VECTOR 22
|
||||
|
||||
/* The remaining space is defined by each driver as the per-driver
|
||||
* configuration space */
|
||||
#define VIRTIO_PCI_CONFIG_OFF(msix_enabled) ((msix_enabled) ? 24 : 20)
|
||||
/* Deprecated: please use VIRTIO_PCI_CONFIG_OFF instead */
|
||||
#define VIRTIO_PCI_CONFIG(dev) VIRTIO_PCI_CONFIG_OFF((dev)->msix_enabled)
|
||||
|
||||
/* Virtio ABI version, this must match exactly */
|
||||
#define VIRTIO_PCI_ABI_VERSION 0
|
||||
|
||||
/* How many bits to shift physical queue address written to QUEUE_PFN.
|
||||
* 12 is historical, and due to x86 page size. */
|
||||
#define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12
|
||||
|
||||
/* The alignment to use between consumer and producer parts of vring.
|
||||
* x86 pagesize again. */
|
||||
#define VIRTIO_PCI_VRING_ALIGN 4096
|
||||
|
||||
#endif /* VIRTIO_PCI_NO_LEGACY */
|
||||
|
||||
/* The bit of the ISR which indicates a device configuration change. */
|
||||
#define VIRTIO_PCI_ISR_CONFIG 0x2
|
||||
/* Vector value used to disable MSI for queue */
|
||||
#define VIRTIO_MSI_NO_VECTOR 0xffff
|
||||
|
||||
#ifndef VIRTIO_PCI_NO_MODERN
|
||||
|
||||
/* IDs for different capabilities. Must all exist. */
|
||||
|
||||
/* Common configuration */
|
||||
#define VIRTIO_PCI_CAP_COMMON_CFG 1
|
||||
/* Notifications */
|
||||
#define VIRTIO_PCI_CAP_NOTIFY_CFG 2
|
||||
/* ISR access */
|
||||
#define VIRTIO_PCI_CAP_ISR_CFG 3
|
||||
/* Device specific confiuration */
|
||||
#define VIRTIO_PCI_CAP_DEVICE_CFG 4
|
||||
|
||||
/* This is the PCI capability header: */
|
||||
struct virtio_pci_cap {
|
||||
__u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */
|
||||
__u8 cap_next; /* Generic PCI field: next ptr. */
|
||||
__u8 cap_len; /* Generic PCI field: capability length */
|
||||
__u8 cfg_type; /* Identifies the structure. */
|
||||
__u8 bar; /* Where to find it. */
|
||||
__u8 padding[3]; /* Pad to full dword. */
|
||||
__le32 offset; /* Offset within bar. */
|
||||
__le32 length; /* Length of the structure, in bytes. */
|
||||
};
|
||||
|
||||
struct virtio_pci_notify_cap {
|
||||
struct virtio_pci_cap cap;
|
||||
__le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */
|
||||
};
|
||||
|
||||
/* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */
|
||||
struct virtio_pci_common_cfg {
|
||||
/* About the whole device. */
|
||||
__le32 device_feature_select; /* read-write */
|
||||
__le32 device_feature; /* read-only */
|
||||
__le32 guest_feature_select; /* read-write */
|
||||
__le32 guest_feature; /* read-write */
|
||||
__le16 msix_config; /* read-write */
|
||||
__le16 num_queues; /* read-only */
|
||||
__u8 device_status; /* read-write */
|
||||
__u8 config_generation; /* read-only */
|
||||
|
||||
/* About a specific virtqueue. */
|
||||
__le16 queue_select; /* read-write */
|
||||
__le16 queue_size; /* read-write, power of 2. */
|
||||
__le16 queue_msix_vector; /* read-write */
|
||||
__le16 queue_enable; /* read-write */
|
||||
__le16 queue_notify_off; /* read-only */
|
||||
__le32 queue_desc_lo; /* read-write */
|
||||
__le32 queue_desc_hi; /* read-write */
|
||||
__le32 queue_avail_lo; /* read-write */
|
||||
__le32 queue_avail_hi; /* read-write */
|
||||
__le32 queue_used_lo; /* read-write */
|
||||
__le32 queue_used_hi; /* read-write */
|
||||
};
|
||||
|
||||
/* Macro versions of offsets for the Old Timers! */
|
||||
#define VIRTIO_PCI_CAP_VNDR 0
|
||||
#define VIRTIO_PCI_CAP_NEXT 1
|
||||
#define VIRTIO_PCI_CAP_LEN 2
|
||||
#define VIRTIO_PCI_CAP_CFG_TYPE 3
|
||||
#define VIRTIO_PCI_CAP_BAR 4
|
||||
#define VIRTIO_PCI_CAP_OFFSET 8
|
||||
#define VIRTIO_PCI_CAP_LENGTH 12
|
||||
|
||||
#define VIRTIO_PCI_NOTIFY_CAP_MULT 16
|
||||
|
||||
|
||||
#define VIRTIO_PCI_COMMON_DFSELECT 0
|
||||
#define VIRTIO_PCI_COMMON_DF 4
|
||||
#define VIRTIO_PCI_COMMON_GFSELECT 8
|
||||
#define VIRTIO_PCI_COMMON_GF 12
|
||||
#define VIRTIO_PCI_COMMON_MSIX 16
|
||||
#define VIRTIO_PCI_COMMON_NUMQ 18
|
||||
#define VIRTIO_PCI_COMMON_STATUS 20
|
||||
#define VIRTIO_PCI_COMMON_CFGGENERATION 21
|
||||
#define VIRTIO_PCI_COMMON_Q_SELECT 22
|
||||
#define VIRTIO_PCI_COMMON_Q_SIZE 24
|
||||
#define VIRTIO_PCI_COMMON_Q_MSIX 26
|
||||
#define VIRTIO_PCI_COMMON_Q_ENABLE 28
|
||||
#define VIRTIO_PCI_COMMON_Q_NOFF 30
|
||||
#define VIRTIO_PCI_COMMON_Q_DESCLO 32
|
||||
#define VIRTIO_PCI_COMMON_Q_DESCHI 36
|
||||
#define VIRTIO_PCI_COMMON_Q_AVAILLO 40
|
||||
#define VIRTIO_PCI_COMMON_Q_AVAILHI 44
|
||||
#define VIRTIO_PCI_COMMON_Q_USEDLO 48
|
||||
#define VIRTIO_PCI_COMMON_Q_USEDHI 52
|
||||
|
||||
#endif /* VIRTIO_PCI_NO_MODERN */
|
||||
|
||||
#endif
|
||||
@@ -314,6 +314,7 @@
|
||||
|
||||
#define MSR_P6_PERFCTR0 0xc1
|
||||
|
||||
#define MSR_IA32_SMBASE 0x9e
|
||||
#define MSR_MTRRcap 0xfe
|
||||
#define MSR_MTRRcap_VCNT 8
|
||||
#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
|
||||
|
||||
@@ -18,6 +18,11 @@ bool kvm_allows_irq0_override(void)
|
||||
}
|
||||
|
||||
#ifndef __OPTIMIZE__
|
||||
bool kvm_has_smm(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* This function is only called inside conditionals which we
|
||||
* rely on the compiler to optimize out when CONFIG_KVM is not
|
||||
* defined.
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user