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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

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* target/riscv: clean up supported MMU modes, declarative CPU definitions,
  remove .instance_post_init (reviewed by Alistair)
* qom: reverse order of instance_post_init calls
* qapi/misc-target: doc and standard improvements for SGX
* hw/pci-host/gt64120: Fix endianness handling
* i386/hvf: Make CPUID_HT supported
* i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported

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# gpg: Signature made Tue 20 May 2025 03:16:27 EDT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (35 commits)
  qom: reverse order of instance_post_init calls
  target/riscv: remove .instance_post_init
  target/riscv: convert Xiangshan Nanhu to RISCVCPUDef
  target/riscv: convert Ventana V1 to RISCVCPUDef
  target/riscv: convert TT Ascalon to RISCVCPUDef
  target/riscv: convert THead C906 to RISCVCPUDef
  target/riscv: generalize custom CSR functionality
  target/riscv: th: make CSR insertion test a bit more intuitive
  target/riscv: convert SiFive U models to RISCVCPUDef
  target/riscv: convert ibex CPU models to RISCVCPUDef
  target/riscv: convert SiFive E CPU models to RISCVCPUDef
  target/riscv: convert dynamic CPU models to RISCVCPUDef
  target/riscv: convert bare CPU models to RISCVCPUDef
  target/riscv: convert profile CPU models to RISCVCPUDef
  target/riscv: convert abstract CPU classes to RISCVCPUDef
  target/riscv: add more RISCVCPUDef fields
  target/riscv: include default value in cpu_cfg_fields.h.inc
  target/riscv: move RISCVCPUConfig fields to a header file
  target/riscv: merge riscv_cpu_class_init with the class_base function
  target/riscv: store RISCVCPUDef struct directly in the class
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
2025-05-20 10:26:30 -04:00
parent 2af4a82ab2 220c739903
commit f0737158b4
26 changed files with 821 additions and 874 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/i386/sgx-stub.c
+2 -2
View File
@@ -10,13 +10,13 @@ void sgx_epc_build_srat(GArray *table_data)
{
}
SGXInfo *qmp_query_sgx(Error **errp)
SgxInfo *qmp_query_sgx(Error **errp)
{
error_setg(errp, "SGX support is not compiled in");
return NULL;
}
SGXInfo *qmp_query_sgx_capabilities(Error **errp)
SgxInfo *qmp_query_sgx_capabilities(Error **errp)
{
error_setg(errp, "SGX support is not compiled in");
return NULL;
hw/i386/sgx.c
+16 -16
View File
@@ -84,10 +84,10 @@ static uint64_t sgx_calc_section_metric(uint64_t low, uint64_t high)
((high & MAKE_64BIT_MASK(0, 20)) << 32);
}
static SGXEPCSectionList *sgx_calc_host_epc_sections(void)
static SgxEpcSectionList *sgx_calc_host_epc_sections(void)
{
SGXEPCSectionList *head = NULL, **tail = &head;
SGXEPCSection *section;
SgxEpcSectionList *head = NULL, **tail = &head;
SgxEpcSection *section;
uint32_t i, type;
uint32_t eax, ebx, ecx, edx;
uint32_t j = 0;
@@ -104,7 +104,7 @@ static SGXEPCSectionList *sgx_calc_host_epc_sections(void)
break;
}
section = g_new0(SGXEPCSection, 1);
section = g_new0(SgxEpcSection, 1);
section->node = j++;
section->size = sgx_calc_section_metric(ecx, edx);
QAPI_LIST_APPEND(tail, section);
@@ -153,9 +153,9 @@ static void sgx_epc_reset(void *opaque)
}
}
SGXInfo *qmp_query_sgx_capabilities(Error **errp)
SgxInfo *qmp_query_sgx_capabilities(Error **errp)
{
SGXInfo *info = NULL;
SgxInfo *info = NULL;
uint32_t eax, ebx, ecx, edx;
Error *local_err = NULL;
@@ -166,7 +166,7 @@ SGXInfo *qmp_query_sgx_capabilities(Error **errp)
return NULL;
}
info = g_new0(SGXInfo, 1);
info = g_new0(SgxInfo, 1);
host_cpuid(0x7, 0, &eax, &ebx, &ecx, &edx);
info->sgx = ebx & (1U << 2) ? true : false;
@@ -183,17 +183,17 @@ SGXInfo *qmp_query_sgx_capabilities(Error **errp)
return info;
}
static SGXEPCSectionList *sgx_get_epc_sections_list(void)
static SgxEpcSectionList *sgx_get_epc_sections_list(void)
{
GSList *device_list = sgx_epc_get_device_list();
SGXEPCSectionList *head = NULL, **tail = &head;
SGXEPCSection *section;
SgxEpcSectionList *head = NULL, **tail = &head;
SgxEpcSection *section;
for (; device_list; device_list = device_list->next) {
DeviceState *dev = device_list->data;
Object *obj = OBJECT(dev);
section = g_new0(SGXEPCSection, 1);
section = g_new0(SgxEpcSection, 1);
section->node = object_property_get_uint(obj, SGX_EPC_NUMA_NODE_PROP,
&error_abort);
section->size = object_property_get_uint(obj, SGX_EPC_SIZE_PROP,
@@ -205,9 +205,9 @@ static SGXEPCSectionList *sgx_get_epc_sections_list(void)
return head;
}
SGXInfo *qmp_query_sgx(Error **errp)
SgxInfo *qmp_query_sgx(Error **errp)
{
SGXInfo *info = NULL;
SgxInfo *info = NULL;
X86MachineState *x86ms;
PCMachineState *pcms =
(PCMachineState *)object_dynamic_cast(qdev_get_machine(),
@@ -223,7 +223,7 @@ SGXInfo *qmp_query_sgx(Error **errp)
return NULL;
}
info = g_new0(SGXInfo, 1);
info = g_new0(SgxInfo, 1);
info->sgx = true;
info->sgx1 = true;
@@ -237,8 +237,8 @@ SGXInfo *qmp_query_sgx(Error **errp)
void hmp_info_sgx(Monitor *mon, const QDict *qdict)
{
Error *err = NULL;
SGXEPCSectionList *section_list, *section;
g_autoptr(SGXInfo) info = qmp_query_sgx(&err);
SgxEpcSectionList *section_list, *section;
g_autoptr(SgxInfo) info = qmp_query_sgx(&err);
uint64_t size = 0;
if (err) {
hw/pci-host/gt64120.c
+48 -34
View File
@@ -320,38 +320,6 @@ static void gt64120_isd_mapping(GT64120State *s)
memory_region_transaction_commit();
}
static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
{
/* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc00 */
static const MemoryRegionOps *pci_host_data_ops[] = {
&pci_host_data_be_ops, &pci_host_data_le_ops
};
PCIHostState *phb = PCI_HOST_BRIDGE(s);
memory_region_transaction_begin();
/*
* The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal
* Command Register determines how data transactions from the CPU to/from
* PCI are handled along with the setting of the Endianness bit in the CPU
* Configuration Register. See:
* - Table 16: 32-bit PCI Transaction Endianness
* - Table 158: PCI_0 Command, Offset: 0xc00
*/
if (memory_region_is_mapped(&phb->data_mem)) {
memory_region_del_subregion(&s->ISD_mem, &phb->data_mem);
object_unparent(OBJECT(&phb->data_mem));
}
memory_region_init_io(&phb->data_mem, OBJECT(phb),
pci_host_data_ops[s->regs[GT_PCI0_CMD] & 1],
s, "pci-conf-data", 4);
memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2,
&phb->data_mem, 1);
memory_region_transaction_commit();
}
static void gt64120_pci_mapping(GT64120State *s)
{
memory_region_transaction_begin();
@@ -645,7 +613,6 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_PCI0_CMD:
case GT_PCI1_CMD:
s->regs[saddr] = val & 0x0401fc0f;
gt64120_update_pci_cfgdata_mapping(s);
break;
case GT_PCI0_TOR:
case GT_PCI0_BS_SCS10:
@@ -1024,6 +991,48 @@ static const MemoryRegionOps isd_mem_ops = {
},
};
static bool bswap(const GT64120State *s)
{
PCIHostState *phb = PCI_HOST_BRIDGE(s);
/*check for bus == 0 && device == 0, Bits 11:15 = Device , Bits 16:23 = Bus*/
bool is_phb_dev0 = extract32(phb->config_reg, 11, 13) == 0;
bool le_mode = FIELD_EX32(s->regs[GT_PCI0_CMD], GT_PCI0_CMD, MByteSwap);
/* Only swap for non-bridge devices in big-endian mode */
return !le_mode && !is_phb_dev0;
}
static uint64_t gt64120_pci_data_read(void *opaque, hwaddr addr, unsigned size)
{
GT64120State *s = opaque;
uint32_t val = pci_host_data_le_ops.read(opaque, addr, size);
if (bswap(s)) {
val = bswap32(val);
}
return val;
}
static void gt64120_pci_data_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
GT64120State *s = opaque;
if (bswap(s)) {
val = bswap32(val);
}
pci_host_data_le_ops.write(opaque, addr, val, size);
}
static const MemoryRegionOps gt64120_pci_data_ops = {
.read = gt64120_pci_data_read,
.write = gt64120_pci_data_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void gt64120_reset(DeviceState *dev)
{
GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
@@ -1178,7 +1187,6 @@ static void gt64120_reset(DeviceState *dev)
gt64120_isd_mapping(s);
gt64120_pci_mapping(s);
gt64120_update_pci_cfgdata_mapping(s);
}
static void gt64120_realize(DeviceState *dev, Error **errp)
@@ -1202,6 +1210,12 @@ static void gt64120_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2,
&phb->conf_mem, 1);
memory_region_init_io(&phb->data_mem, OBJECT(phb),
&gt64120_pci_data_ops,
s, "pci-conf-data", 4);
memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2,
&phb->data_mem, 1);
/*
* The whole address space decoded by the GT-64120A doesn't generate
hw/pci/pci_host.c
-6
View File
@@ -217,12 +217,6 @@ const MemoryRegionOps pci_host_data_le_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
const MemoryRegionOps pci_host_data_be_ops = {
.read = pci_host_data_read,
.write = pci_host_data_write,
.endianness = DEVICE_BIG_ENDIAN,
};
static bool pci_host_needed(void *opaque)
{
PCIHostState *s = opaque;
hw/riscv/boot.c
+1 -1
View File
@@ -37,7 +37,7 @@
bool riscv_is_32bit(RISCVHartArrayState *harts)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]);
return mcc->misa_mxl_max == MXL_RV32;
return mcc->def->misa_mxl_max == MXL_RV32;
}
/*
hw/riscv/virt-acpi-build.c
+7 -8
View File
@@ -287,7 +287,7 @@ static void build_rhct(GArray *table_data,
uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
RISCVCPU *cpu = &s->soc[0].harts[0];
uint32_t mmu_offset = 0;
uint8_t satp_mode_max;
bool rv32 = riscv_cpu_is_32bit(cpu);
g_autofree char *isa = NULL;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -307,7 +307,7 @@ static void build_rhct(GArray *table_data,
num_rhct_nodes++;
}
if (cpu->cfg.satp_mode.supported != 0) {
if (!rv32 && cpu->cfg.max_satp_mode >= VM_1_10_SV39) {
num_rhct_nodes++;
}
@@ -367,22 +367,21 @@ static void build_rhct(GArray *table_data,
}
/* MMU node structure */
if (cpu->cfg.satp_mode.supported != 0) {
satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
if (!rv32 && cpu->cfg.max_satp_mode >= VM_1_10_SV39) {
mmu_offset = table_data->len - table.table_offset;
build_append_int_noprefix(table_data, 2, 2); /* Type */
build_append_int_noprefix(table_data, 8, 2); /* Length */
build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
build_append_int_noprefix(table_data, 0, 1); /* Reserved */
/* MMU Type */
if (satp_mode_max == VM_1_10_SV57) {
if (cpu->cfg.max_satp_mode == VM_1_10_SV57) {
build_append_int_noprefix(table_data, 2, 1); /* Sv57 */
} else if (satp_mode_max == VM_1_10_SV48) {
} else if (cpu->cfg.max_satp_mode == VM_1_10_SV48) {
build_append_int_noprefix(table_data, 1, 1); /* Sv48 */
} else if (satp_mode_max == VM_1_10_SV39) {
} else if (cpu->cfg.max_satp_mode == VM_1_10_SV39) {
build_append_int_noprefix(table_data, 0, 1); /* Sv39 */
} else {
assert(1);
g_assert_not_reached();
}
}
hw/riscv/virt.c
+2 -3
View File
@@ -237,10 +237,10 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
uint32_t cpu_phandle;
MachineState *ms = MACHINE(s);
bool is_32_bit = riscv_is_32bit(&s->soc[0]);
uint8_t satp_mode_max;
for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
int8_t satp_mode_max = cpu_ptr->cfg.max_satp_mode;
g_autofree char *cpu_name = NULL;
g_autofree char *core_name = NULL;
g_autofree char *intc_name = NULL;
@@ -252,8 +252,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
s->soc[socket].hartid_base + cpu);
qemu_fdt_add_subnode(ms->fdt, cpu_name);
if (cpu_ptr->cfg.satp_mode.supported != 0) {
satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map);
if (satp_mode_max != -1) {
sv_name = g_strdup_printf("riscv,%s",
satp_mode_str(satp_mode_max, is_32_bit));
qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);
include/hw/pci-host/dino.h
-4
View File
@@ -109,10 +109,6 @@ static const uint32_t reg800_keep_bits[DINO800_REGS] = {
struct DinoState {
PCIHostState parent_obj;
/*
* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
* so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops.
*/
uint32_t config_reg_dino; /* keep original copy, including 2 lowest bits */
uint32_t iar0;
include/hw/pci/pci_host.h
-1
View File
@@ -68,6 +68,5 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len);
extern const MemoryRegionOps pci_host_conf_le_ops;
extern const MemoryRegionOps pci_host_conf_be_ops;
extern const MemoryRegionOps pci_host_data_le_ops;
extern const MemoryRegionOps pci_host_data_be_ops;
#endif /* PCI_HOST_H */
include/qom/object.h
+2 -1
View File
@@ -445,7 +445,8 @@ struct Object
* class will have already been initialized so the type is only responsible
* for initializing its own members.
* @instance_post_init: This function is called to finish initialization of
* an object, after all @instance_init functions were called.
* an object, after all @instance_init functions were called, as well as
* @instance_post_init functions for the parent classes.
* @instance_finalize: This function is called during object destruction. This
* is called before the parent @instance_finalize function has been called.
* An object should only free the members that are unique to its type in this
qapi/misc-target.json
+13 -13
View File
@@ -319,9 +319,9 @@
'if': 'TARGET_ARM' }
##
# @SGXEPCSection:
# @SgxEpcSection:
#
# Information about intel SGX EPC section info
# Information about intel SGX EPC section
#
# @node: the numa node
#
@@ -329,12 +329,12 @@
#
# Since: 7.0
##
{ 'struct': 'SGXEPCSection',
{ 'struct': 'SgxEpcSection',
'data': { 'node': 'int',
'size': 'uint64'}}
##
# @SGXInfo:
# @SgxInfo:
#
# Information about intel Safe Guard eXtension (SGX) support
#
@@ -346,24 +346,24 @@
#
# @flc: true if FLC is supported
#
# @sections: The EPC sections info for guest (Since: 7.0)
# @sections: The EPC sections information (Since: 7.0)
#
# Since: 6.2
##
{ 'struct': 'SGXInfo',
{ 'struct': 'SgxInfo',
'data': { 'sgx': 'bool',
'sgx1': 'bool',
'sgx2': 'bool',
'flc': 'bool',
'sections': ['SGXEPCSection']},
'sections': ['SgxEpcSection']},
'if': 'TARGET_I386' }
##
# @query-sgx:
#
# Returns information about SGX
# Returns information about configured SGX capabilities of guest
#
# Returns: @SGXInfo
# Returns: @SgxInfo
#
# Since: 6.2
#
@@ -375,14 +375,14 @@
# "sections": [{"node": 0, "size": 67108864},
# {"node": 1, "size": 29360128}]} }
##
{ 'command': 'query-sgx', 'returns': 'SGXInfo', 'if': 'TARGET_I386' }
{ 'command': 'query-sgx', 'returns': 'SgxInfo', 'if': 'TARGET_I386' }
##
# @query-sgx-capabilities:
#
# Returns information from host SGX capabilities
# Returns information about SGX capabilities of host
#
# Returns: @SGXInfo
# Returns: @SgxInfo
#
# Since: 6.2
#
@@ -394,7 +394,7 @@
# "section" : [{"node": 0, "size": 67108864},
# {"node": 1, "size": 29360128}]} }
##
{ 'command': 'query-sgx-capabilities', 'returns': 'SGXInfo', 'if': 'TARGET_I386' }
{ 'command': 'query-sgx-capabilities', 'returns': 'SgxInfo', 'if': 'TARGET_I386' }
##
qom/object.c
+4 -4
View File
@@ -431,13 +431,13 @@ static void object_init_with_type(Object *obj, TypeImpl *ti)
static void object_post_init_with_type(Object *obj, TypeImpl *ti)
{
if (ti->instance_post_init) {
ti->instance_post_init(obj);
}
if (type_has_parent(ti)) {
object_post_init_with_type(obj, type_get_parent(ti));
}
if (ti->instance_post_init) {
ti->instance_post_init(obj);
}
}
bool object_apply_global_props(Object *obj, const GPtrArray *props,
target/i386/cpu.c
+5 -3
View File
@@ -776,11 +776,12 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE | \
CPUID_HT)
/* partly implemented:
CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
/* missing:
CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_TM, CPUID_PBE */
/*
* Kernel-only features that can be shown to usermode programs even if
@@ -848,7 +849,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES)
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES | \
CPUID_EXT3_CMP_LEG)
#define TCG_EXT4_FEATURES 0
target/i386/hvf/x86_cpuid.c
+1 -1
View File
@@ -73,7 +73,7 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX |
CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS;
CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_HT;
ecx &= CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID |
CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE |
target/riscv/cpu-qom.h
+2
View File
@@ -44,9 +44,11 @@
#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U RISCV_CPU_TYPE_NAME("sifive-u")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
target/riscv/cpu.c
+468 -546
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File diff suppressed because it is too large Load Diff
target/riscv/cpu.h
+37 -5
View File
@@ -499,6 +499,19 @@ struct CPUArchState {
uint64_t rnmi_excpvec;
};
/*
* map is a 16-bit bitmap: the most significant set bit in map is the maximum
* satp mode that is supported. It may be chosen by the user and must respect
* what qemu implements (valid_1_10_32/64) and what the hw is capable of
* (supported bitmap below).
*
* init is a 16-bit bitmap used to make sure the user selected a correct
* configuration as per the specification.
*/
typedef struct {
uint16_t map, init;
} RISCVSATPModes;
/*
* RISCVCPU:
* @env: #CPURISCVState
@@ -515,6 +528,7 @@ struct ArchCPU {
/* Configuration Settings */
RISCVCPUConfig cfg;
RISCVSATPModes satp_modes;
QEMUTimer *pmu_timer;
/* A bitmask of Available programmable counters */
@@ -524,6 +538,19 @@ struct ArchCPU {
const GPtrArray *decoders;
};
typedef struct RISCVCSR RISCVCSR;
typedef struct RISCVCPUDef {
RISCVMXL misa_mxl_max; /* max mxl for this cpu */
RISCVCPUProfile *profile;
uint32_t misa_ext;
int priv_spec;
int32_t vext_spec;
RISCVCPUConfig cfg;
bool bare;
const RISCVCSR *custom_csrs;
} RISCVCPUDef;
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
@@ -536,7 +563,7 @@ struct RISCVCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
RISCVMXL misa_mxl_max; /* max mxl for this cpu */
RISCVCPUDef *def;
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
@@ -869,6 +896,12 @@ typedef struct {
uint32_t min_priv_ver;
} riscv_csr_operations;
struct RISCVCSR {
int csrno;
bool (*insertion_test)(RISCVCPU *cpu);
riscv_csr_operations csr_ops;
};
/* CSR function table constants */
enum {
CSR_TABLE_SIZE = 0x1000
@@ -923,18 +956,17 @@ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops);
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
target_ulong riscv_new_csr_seed(target_ulong new_value,
target_ulong write_mask);
uint8_t satp_mode_max_from_map(uint32_t map);
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
/* Implemented in th_csr.c */
void th_register_custom_csrs(RISCVCPU *cpu);
/* In th_csr.c */
extern const RISCVCSR th_csr_list[];
const char *priv_spec_to_str(int priv_version);
#endif /* RISCV_CPU_H */
target/riscv/cpu_cfg.h
+3 -175
View File
@@ -21,182 +21,10 @@
#ifndef RISCV_CPU_CFG_H
#define RISCV_CPU_CFG_H
/*
* map is a 16-bit bitmap: the most significant set bit in map is the maximum
* satp mode that is supported. It may be chosen by the user and must respect
* what qemu implements (valid_1_10_32/64) and what the hw is capable of
* (supported bitmap below).
*
* init is a 16-bit bitmap used to make sure the user selected a correct
* configuration as per the specification.
*
* supported is a 16-bit bitmap used to reflect the hw capabilities.
*/
typedef struct {
uint16_t map, init, supported;
} RISCVSATPMap;
struct RISCVCPUConfig {
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
bool ext_zbkb;
bool ext_zbkc;
bool ext_zbkx;
bool ext_zbs;
bool ext_zca;
bool ext_zcb;
bool ext_zcd;
bool ext_zce;
bool ext_zcf;
bool ext_zcmp;
bool ext_zcmt;
bool ext_zk;
bool ext_zkn;
bool ext_zknd;
bool ext_zkne;
bool ext_zknh;
bool ext_zkr;
bool ext_zks;
bool ext_zksed;
bool ext_zksh;
bool ext_zkt;
bool ext_zifencei;
bool ext_zicntr;
bool ext_zicsr;
bool ext_zicbom;
bool ext_zicbop;
bool ext_zicboz;
bool ext_zicfilp;
bool ext_zicfiss;
bool ext_zicond;
bool ext_zihintntl;
bool ext_zihintpause;
bool ext_zihpm;
bool ext_zimop;
bool ext_zcmop;
bool ext_ztso;
bool ext_smstateen;
bool ext_sstc;
bool ext_smcdeleg;
bool ext_ssccfg;
bool ext_smcntrpmf;
bool ext_smcsrind;
bool ext_sscsrind;
bool ext_ssdbltrp;
bool ext_smdbltrp;
bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
bool ext_svvptc;
bool ext_svukte;
bool ext_zdinx;
bool ext_zaamo;
bool ext_zacas;
bool ext_zama16b;
bool ext_zabha;
bool ext_zalrsc;
bool ext_zawrs;
bool ext_zfa;
bool ext_zfbfmin;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zfinx;
bool ext_zhinx;
bool ext_zhinxmin;
bool ext_zve32f;
bool ext_zve32x;
bool ext_zve64f;
bool ext_zve64d;
bool ext_zve64x;
bool ext_zvbb;
bool ext_zvbc;
bool ext_zvkb;
bool ext_zvkg;
bool ext_zvkned;
bool ext_zvknha;
bool ext_zvknhb;
bool ext_zvksed;
bool ext_zvksh;
bool ext_zvkt;
bool ext_zvkn;
bool ext_zvknc;
bool ext_zvkng;
bool ext_zvks;
bool ext_zvksc;
bool ext_zvksg;
bool ext_zmmul;
bool ext_zvfbfmin;
bool ext_zvfbfwma;
bool ext_zvfh;
bool ext_zvfhmin;
bool ext_smaia;
bool ext_ssaia;
bool ext_smctr;
bool ext_ssctr;
bool ext_sscofpmf;
bool ext_smepmp;
bool ext_smrnmi;
bool ext_ssnpm;
bool ext_smnpm;
bool ext_smmpm;
bool ext_sspm;
bool ext_supm;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
bool rvv_vl_half_avl;
uint32_t mvendorid;
uint64_t marchid;
uint64_t mimpid;
/* Named features */
bool ext_svade;
bool ext_zic64b;
bool ext_ssstateen;
bool ext_sha;
/*
* Always 'true' booleans for named features
* TCG always implement/can't be user disabled,
* based on spec version.
*/
bool has_priv_1_13;
bool has_priv_1_12;
bool has_priv_1_11;
/* Always enabled for TCG if has_priv_1_11 */
bool ext_ziccrse;
/* Vendor-specific custom extensions */
bool ext_xtheadba;
bool ext_xtheadbb;
bool ext_xtheadbs;
bool ext_xtheadcmo;
bool ext_xtheadcondmov;
bool ext_xtheadfmemidx;
bool ext_xtheadfmv;
bool ext_xtheadmac;
bool ext_xtheadmemidx;
bool ext_xtheadmempair;
bool ext_xtheadsync;
bool ext_XVentanaCondOps;
uint32_t pmu_mask;
uint16_t vlenb;
uint16_t elen;
uint16_t cbom_blocksize;
uint16_t cbop_blocksize;
uint16_t cboz_blocksize;
bool mmu;
bool pmp;
bool debug;
bool misa_w;
bool short_isa_string;
RISCVSATPMap satp_mode;
#define BOOL_FIELD(x) bool x;
#define TYPED_FIELD(type, x, default) type x;
#include "cpu_cfg_fields.h.inc"
};
typedef struct RISCVCPUConfig RISCVCPUConfig;
target/riscv/cpu_cfg_fields.h.inc
+170
View File
@@ -0,0 +1,170 @@
/*
* Required definitions before including this file:
*
* #define BOOL_FIELD(x)
* #define TYPED_FIELD(type, x, default)
*/
BOOL_FIELD(ext_zba)
BOOL_FIELD(ext_zbb)
BOOL_FIELD(ext_zbc)
BOOL_FIELD(ext_zbkb)
BOOL_FIELD(ext_zbkc)
BOOL_FIELD(ext_zbkx)
BOOL_FIELD(ext_zbs)
BOOL_FIELD(ext_zca)
BOOL_FIELD(ext_zcb)
BOOL_FIELD(ext_zcd)
BOOL_FIELD(ext_zce)
BOOL_FIELD(ext_zcf)
BOOL_FIELD(ext_zcmp)
BOOL_FIELD(ext_zcmt)
BOOL_FIELD(ext_zk)
BOOL_FIELD(ext_zkn)
BOOL_FIELD(ext_zknd)
BOOL_FIELD(ext_zkne)
BOOL_FIELD(ext_zknh)
BOOL_FIELD(ext_zkr)
BOOL_FIELD(ext_zks)
BOOL_FIELD(ext_zksed)
BOOL_FIELD(ext_zksh)
BOOL_FIELD(ext_zkt)
BOOL_FIELD(ext_zifencei)
BOOL_FIELD(ext_zicntr)
BOOL_FIELD(ext_zicsr)
BOOL_FIELD(ext_zicbom)
BOOL_FIELD(ext_zicbop)
BOOL_FIELD(ext_zicboz)
BOOL_FIELD(ext_zicfilp)
BOOL_FIELD(ext_zicfiss)
BOOL_FIELD(ext_zicond)
BOOL_FIELD(ext_zihintntl)
BOOL_FIELD(ext_zihintpause)
BOOL_FIELD(ext_zihpm)
BOOL_FIELD(ext_zimop)
BOOL_FIELD(ext_zcmop)
BOOL_FIELD(ext_ztso)
BOOL_FIELD(ext_smstateen)
BOOL_FIELD(ext_sstc)
BOOL_FIELD(ext_smcdeleg)
BOOL_FIELD(ext_ssccfg)
BOOL_FIELD(ext_smcntrpmf)
BOOL_FIELD(ext_smcsrind)
BOOL_FIELD(ext_sscsrind)
BOOL_FIELD(ext_ssdbltrp)
BOOL_FIELD(ext_smdbltrp)
BOOL_FIELD(ext_svadu)
BOOL_FIELD(ext_svinval)
BOOL_FIELD(ext_svnapot)
BOOL_FIELD(ext_svpbmt)
BOOL_FIELD(ext_svvptc)
BOOL_FIELD(ext_svukte)
BOOL_FIELD(ext_zdinx)
BOOL_FIELD(ext_zaamo)
BOOL_FIELD(ext_zacas)
BOOL_FIELD(ext_zama16b)
BOOL_FIELD(ext_zabha)
BOOL_FIELD(ext_zalrsc)
BOOL_FIELD(ext_zawrs)
BOOL_FIELD(ext_zfa)
BOOL_FIELD(ext_zfbfmin)
BOOL_FIELD(ext_zfh)
BOOL_FIELD(ext_zfhmin)
BOOL_FIELD(ext_zfinx)
BOOL_FIELD(ext_zhinx)
BOOL_FIELD(ext_zhinxmin)
BOOL_FIELD(ext_zve32f)
BOOL_FIELD(ext_zve32x)
BOOL_FIELD(ext_zve64f)
BOOL_FIELD(ext_zve64d)
BOOL_FIELD(ext_zve64x)
BOOL_FIELD(ext_zvbb)
BOOL_FIELD(ext_zvbc)
BOOL_FIELD(ext_zvkb)
BOOL_FIELD(ext_zvkg)
BOOL_FIELD(ext_zvkned)
BOOL_FIELD(ext_zvknha)
BOOL_FIELD(ext_zvknhb)
BOOL_FIELD(ext_zvksed)
BOOL_FIELD(ext_zvksh)
BOOL_FIELD(ext_zvkt)
BOOL_FIELD(ext_zvkn)
BOOL_FIELD(ext_zvknc)
BOOL_FIELD(ext_zvkng)
BOOL_FIELD(ext_zvks)
BOOL_FIELD(ext_zvksc)
BOOL_FIELD(ext_zvksg)
BOOL_FIELD(ext_zmmul)
BOOL_FIELD(ext_zvfbfmin)
BOOL_FIELD(ext_zvfbfwma)
BOOL_FIELD(ext_zvfh)
BOOL_FIELD(ext_zvfhmin)
BOOL_FIELD(ext_smaia)
BOOL_FIELD(ext_ssaia)
BOOL_FIELD(ext_smctr)
BOOL_FIELD(ext_ssctr)
BOOL_FIELD(ext_sscofpmf)
BOOL_FIELD(ext_smepmp)
BOOL_FIELD(ext_smrnmi)
BOOL_FIELD(ext_ssnpm)
BOOL_FIELD(ext_smnpm)
BOOL_FIELD(ext_smmpm)
BOOL_FIELD(ext_sspm)
BOOL_FIELD(ext_supm)
BOOL_FIELD(rvv_ta_all_1s)
BOOL_FIELD(rvv_ma_all_1s)
BOOL_FIELD(rvv_vl_half_avl)
/* Named features */
BOOL_FIELD(ext_svade)
BOOL_FIELD(ext_zic64b)
BOOL_FIELD(ext_ssstateen)
BOOL_FIELD(ext_sha)
/*
* Always 'true' booleans for named features
* TCG always implement/can't be user disabled,
* based on spec version.
*/
BOOL_FIELD(has_priv_1_13)
BOOL_FIELD(has_priv_1_12)
BOOL_FIELD(has_priv_1_11)
/* Always enabled for TCG if has_priv_1_11 */
BOOL_FIELD(ext_ziccrse)
/* Vendor-specific custom extensions */
BOOL_FIELD(ext_xtheadba)
BOOL_FIELD(ext_xtheadbb)
BOOL_FIELD(ext_xtheadbs)
BOOL_FIELD(ext_xtheadcmo)
BOOL_FIELD(ext_xtheadcondmov)
BOOL_FIELD(ext_xtheadfmemidx)
BOOL_FIELD(ext_xtheadfmv)
BOOL_FIELD(ext_xtheadmac)
BOOL_FIELD(ext_xtheadmemidx)
BOOL_FIELD(ext_xtheadmempair)
BOOL_FIELD(ext_xtheadsync)
BOOL_FIELD(ext_XVentanaCondOps)
BOOL_FIELD(mmu)
BOOL_FIELD(pmp)
BOOL_FIELD(debug)
BOOL_FIELD(misa_w)
BOOL_FIELD(short_isa_string)
TYPED_FIELD(uint32_t, mvendorid, 0)
TYPED_FIELD(uint64_t, marchid, 0)
TYPED_FIELD(uint64_t, mimpid, 0)
TYPED_FIELD(uint32_t, pmu_mask, 0)
TYPED_FIELD(uint16_t, vlenb, 0)
TYPED_FIELD(uint16_t, elen, 0)
TYPED_FIELD(uint16_t, cbom_blocksize, 0)
TYPED_FIELD(uint16_t, cbop_blocksize, 0)
TYPED_FIELD(uint16_t, cboz_blocksize, 0)
TYPED_FIELD(int8_t, max_satp_mode, -1)
#undef BOOL_FIELD
#undef TYPED_FIELD
target/riscv/csr.c
+8 -3
View File
@@ -40,7 +40,7 @@ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
*ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
}
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops)
{
csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
}
@@ -1912,8 +1912,13 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
static bool validate_vm(CPURISCVState *env, target_ulong vm)
{
uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.map;
return get_field(mode_supported, (1 << vm));
bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
RISCVCPU *cpu = env_archcpu(env);
int satp_mode_supported_max = cpu->cfg.max_satp_mode;
const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
assert(satp_mode_supported_max >= 0);
return vm <= satp_mode_supported_max && valid_vm[vm];
}
static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xatp,

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