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hw/arm: Replace TABs for spaces in OMAP board and device code

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In hw/arm and include/hw/arm, some source files for the OMAP SoC
and the sx1 boards that are our only remaining OMAP boards still
have hard-coded tabs (almost entirely used for the indent on
inline comments, not for actual code indent).

Replace the tabs with spaces using vim :retab. I used 4 spaces
except in some defines and comments where I tried to put
everything aligned in the same column for better readability.

This commit is a purely whitespace-only change.

Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com>
Message-id: 20250505131130.82206-1-santimonserr@gmail.com
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/373
[PMM: expanded commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Santiago Monserrat Campanello
2025-05-14 14:29:47 +01:00
committed by Peter Maydell
parent 6414b7709d
commit edf838289b
11 changed files with 1399 additions and 1399 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/arm/omap1.c
+508 -508
View File
File diff suppressed because it is too large Load Diff
hw/arm/omap_sx1.c
+1 -1
View File
@@ -1,7 +1,7 @@
/* omap_sx1.c Support for the Siemens SX1 smartphone emulation.
*
* Copyright (C) 2008
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com>
*
* based on PalmOne's (TM) PDAs support (palm.c)
hw/dma/omap_dma.c
+167 -167
View File
File diff suppressed because it is too large Load Diff
hw/gpio/omap_gpio.c
+14 -14
View File
@@ -80,25 +80,25 @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
}
switch (offset) {
case 0x00: /* DATA_INPUT */
case 0x00: /* DATA_INPUT */
return s->inputs & s->pins;
case 0x04: /* DATA_OUTPUT */
case 0x04: /* DATA_OUTPUT */
return s->outputs;
case 0x08: /* DIRECTION_CONTROL */
case 0x08: /* DIRECTION_CONTROL */
return s->dir;
case 0x0c: /* INTERRUPT_CONTROL */
case 0x0c: /* INTERRUPT_CONTROL */
return s->edge;
case 0x10: /* INTERRUPT_MASK */
case 0x10: /* INTERRUPT_MASK */
return s->mask;
case 0x14: /* INTERRUPT_STATUS */
case 0x14: /* INTERRUPT_STATUS */
return s->ints;
case 0x18: /* PIN_CONTROL (not in OMAP310) */
case 0x18: /* PIN_CONTROL (not in OMAP310) */
OMAP_BAD_REG(addr);
return s->pins;
}
@@ -121,11 +121,11 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
}
switch (offset) {
case 0x00: /* DATA_INPUT */
case 0x00: /* DATA_INPUT */
OMAP_RO_REG(addr);
return;
case 0x04: /* DATA_OUTPUT */
case 0x04: /* DATA_OUTPUT */
diff = (s->outputs ^ value) & ~s->dir;
s->outputs = value;
while ((ln = ctz32(diff)) != 32) {
@@ -135,7 +135,7 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
}
break;
case 0x08: /* DIRECTION_CONTROL */
case 0x08: /* DIRECTION_CONTROL */
diff = s->outputs & (s->dir ^ value);
s->dir = value;
@@ -147,21 +147,21 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
}
break;
case 0x0c: /* INTERRUPT_CONTROL */
case 0x0c: /* INTERRUPT_CONTROL */
s->edge = value;
break;
case 0x10: /* INTERRUPT_MASK */
case 0x10: /* INTERRUPT_MASK */
s->mask = value;
break;
case 0x14: /* INTERRUPT_STATUS */
case 0x14: /* INTERRUPT_STATUS */
s->ints &= ~value;
if (!s->ints)
qemu_irq_lower(s->irq);
break;
case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
OMAP_BAD_REG(addr);
s->pins = value;
break;
hw/i2c/omap_i2c.c
+89 -89
View File
@@ -55,16 +55,16 @@ struct OMAPI2CState {
uint16_t test;
};
#define OMAP2_INTR_REV 0x34
#define OMAP2_GC_REV 0x34
#define OMAP2_INTR_REV 0x34
#define OMAP2_GC_REV 0x34
static void omap_i2c_interrupts_update(OMAPI2CState *s)
{
qemu_set_irq(s->irq, s->stat & s->mask);
if ((s->dma >> 15) & 1) /* RDMA_EN */
qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
if ((s->dma >> 7) & 1) /* XDMA_EN */
qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
if ((s->dma >> 15) & 1) /* RDMA_EN */
qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
if ((s->dma >> 7) & 1) /* XDMA_EN */
qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
}
static void omap_i2c_fifo_run(OMAPI2CState *s)
@@ -74,25 +74,25 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
if (!i2c_bus_busy(s->bus))
return;
if ((s->control >> 2) & 1) { /* RM */
if ((s->control >> 1) & 1) { /* STP */
if ((s->control >> 2) & 1) { /* RM */
if ((s->control >> 1) & 1) { /* STP */
i2c_end_transfer(s->bus);
s->control &= ~(1 << 1); /* STP */
s->control &= ~(1 << 1); /* STP */
s->count_cur = s->count;
s->txlen = 0;
} else if ((s->control >> 9) & 1) { /* TRX */
} else if ((s->control >> 9) & 1) { /* TRX */
while (ack && s->txlen)
ack = (i2c_send(s->bus,
(s->fifo >> ((-- s->txlen) << 3)) &
0xff) >= 0);
s->stat |= 1 << 4; /* XRDY */
s->stat |= 1 << 4; /* XRDY */
} else {
while (s->rxlen < 4)
s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
s->stat |= 1 << 3; /* RRDY */
s->stat |= 1 << 3; /* RRDY */
}
} else {
if ((s->control >> 9) & 1) { /* TRX */
if ((s->control >> 9) & 1) { /* TRX */
while (ack && s->count_cur && s->txlen) {
ack = (i2c_send(s->bus,
(s->fifo >> ((-- s->txlen) << 3)) &
@@ -100,12 +100,12 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
s->count_cur --;
}
if (ack && s->count_cur)
s->stat |= 1 << 4; /* XRDY */
s->stat |= 1 << 4; /* XRDY */
else
s->stat &= ~(1 << 4); /* XRDY */
s->stat &= ~(1 << 4); /* XRDY */
if (!s->count_cur) {
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
}
} else {
while (s->count_cur && s->rxlen < 4) {
@@ -113,26 +113,26 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
s->count_cur --;
}
if (s->rxlen)
s->stat |= 1 << 3; /* RRDY */
s->stat |= 1 << 3; /* RRDY */
else
s->stat &= ~(1 << 3); /* RRDY */
s->stat &= ~(1 << 3); /* RRDY */
}
if (!s->count_cur) {
if ((s->control >> 1) & 1) { /* STP */
if ((s->control >> 1) & 1) { /* STP */
i2c_end_transfer(s->bus);
s->control &= ~(1 << 1); /* STP */
s->control &= ~(1 << 1); /* STP */
s->count_cur = s->count;
s->txlen = 0;
} else {
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
}
}
}
s->stat |= (!ack) << 1; /* NACK */
s->stat |= (!ack) << 1; /* NACK */
if (!ack)
s->control &= ~(1 << 1); /* STP */
s->control &= ~(1 << 1); /* STP */
}
static void omap_i2c_reset(DeviceState *dev)
@@ -163,16 +163,16 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
uint16_t ret;
switch (offset) {
case 0x00: /* I2C_REV */
return s->revision; /* REV */
case 0x00: /* I2C_REV */
return s->revision; /* REV */
case 0x04: /* I2C_IE */
case 0x04: /* I2C_IE */
return s->mask;
case 0x08: /* I2C_STAT */
case 0x08: /* I2C_STAT */
return s->stat | (i2c_bus_busy(s->bus) << 12);
case 0x0c: /* I2C_IV */
case 0x0c: /* I2C_IV */
if (s->revision >= OMAP2_INTR_REV)
break;
ret = ctz32(s->stat & s->mask);
@@ -185,18 +185,18 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
omap_i2c_interrupts_update(s);
return ret;
case 0x10: /* I2C_SYSS */
return (s->control >> 15) & 1; /* I2C_EN */
case 0x10: /* I2C_SYSS */
return (s->control >> 15) & 1; /* I2C_EN */
case 0x14: /* I2C_BUF */
case 0x14: /* I2C_BUF */
return s->dma;
case 0x18: /* I2C_CNT */
return s->count_cur; /* DCOUNT */
case 0x18: /* I2C_CNT */
return s->count_cur; /* DCOUNT */
case 0x1c: /* I2C_DATA */
case 0x1c: /* I2C_DATA */
ret = 0;
if (s->control & (1 << 14)) { /* BE */
if (s->control & (1 << 14)) { /* BE */
ret |= ((s->fifo >> 0) & 0xff) << 8;
ret |= ((s->fifo >> 8) & 0xff) << 0;
} else {
@@ -204,7 +204,7 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
ret |= ((s->fifo >> 0) & 0xff) << 0;
}
if (s->rxlen == 1) {
s->stat |= 1 << 15; /* SBD */
s->stat |= 1 << 15; /* SBD */
s->rxlen = 0;
} else if (s->rxlen > 1) {
if (s->rxlen > 2)
@@ -214,41 +214,41 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
/* XXX: remote access (qualifier) error - what's that? */
}
if (!s->rxlen) {
s->stat &= ~(1 << 3); /* RRDY */
if (((s->control >> 10) & 1) && /* MST */
((~s->control >> 9) & 1)) { /* TRX */
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
s->stat &= ~(1 << 3); /* RRDY */
if (((s->control >> 10) & 1) && /* MST */
((~s->control >> 9) & 1)) { /* TRX */
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
}
}
s->stat &= ~(1 << 11); /* ROVR */
s->stat &= ~(1 << 11); /* ROVR */
omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s);
return ret;
case 0x20: /* I2C_SYSC */
case 0x20: /* I2C_SYSC */
return 0;
case 0x24: /* I2C_CON */
case 0x24: /* I2C_CON */
return s->control;
case 0x28: /* I2C_OA */
case 0x28: /* I2C_OA */
return s->addr[0];
case 0x2c: /* I2C_SA */
case 0x2c: /* I2C_SA */
return s->addr[1];
case 0x30: /* I2C_PSC */
case 0x30: /* I2C_PSC */
return s->divider;
case 0x34: /* I2C_SCLL */
case 0x34: /* I2C_SCLL */
return s->times[0];
case 0x38: /* I2C_SCLH */
case 0x38: /* I2C_SCLH */
return s->times[1];
case 0x3c: /* I2C_SYSTEST */
if (s->test & (1 << 15)) { /* ST_EN */
case 0x3c: /* I2C_SYSTEST */
if (s->test & (1 << 15)) { /* ST_EN */
s->test ^= 0xa;
return s->test;
} else
@@ -267,17 +267,17 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
int nack;
switch (offset) {
case 0x00: /* I2C_REV */
case 0x0c: /* I2C_IV */
case 0x10: /* I2C_SYSS */
case 0x00: /* I2C_REV */
case 0x0c: /* I2C_IV */
case 0x10: /* I2C_SYSS */
OMAP_RO_REG(addr);
return;
case 0x04: /* I2C_IE */
case 0x04: /* I2C_IE */
s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
break;
case 0x08: /* I2C_STAT */
case 0x08: /* I2C_STAT */
if (s->revision < OMAP2_INTR_REV) {
OMAP_RO_REG(addr);
return;
@@ -288,40 +288,40 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
omap_i2c_interrupts_update(s);
break;
case 0x14: /* I2C_BUF */
case 0x14: /* I2C_BUF */
s->dma = value & 0x8080;
if (value & (1 << 15)) /* RDMA_EN */
s->mask &= ~(1 << 3); /* RRDY_IE */
if (value & (1 << 7)) /* XDMA_EN */
s->mask &= ~(1 << 4); /* XRDY_IE */
if (value & (1 << 15)) /* RDMA_EN */
s->mask &= ~(1 << 3); /* RRDY_IE */
if (value & (1 << 7)) /* XDMA_EN */
s->mask &= ~(1 << 4); /* XRDY_IE */
break;
case 0x18: /* I2C_CNT */
s->count = value; /* DCOUNT */
case 0x18: /* I2C_CNT */
s->count = value; /* DCOUNT */
break;
case 0x1c: /* I2C_DATA */
case 0x1c: /* I2C_DATA */
if (s->txlen > 2) {
/* XXX: remote access (qualifier) error - what's that? */
break;
}
s->fifo <<= 16;
s->txlen += 2;
if (s->control & (1 << 14)) { /* BE */
if (s->control & (1 << 14)) { /* BE */
s->fifo |= ((value >> 8) & 0xff) << 8;
s->fifo |= ((value >> 0) & 0xff) << 0;
} else {
s->fifo |= ((value >> 0) & 0xff) << 8;
s->fifo |= ((value >> 8) & 0xff) << 0;
}
s->stat &= ~(1 << 10); /* XUDF */
s->stat &= ~(1 << 10); /* XUDF */
if (s->txlen > 2)
s->stat &= ~(1 << 4); /* XRDY */
s->stat &= ~(1 << 4); /* XRDY */
omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s);
break;
case 0x20: /* I2C_SYSC */
case 0x20: /* I2C_SYSC */
if (s->revision < OMAP2_INTR_REV) {
OMAP_BAD_REG(addr);
return;
@@ -332,9 +332,9 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
}
break;
case 0x24: /* I2C_CON */
case 0x24: /* I2C_CON */
s->control = value & 0xcf87;
if (~value & (1 << 15)) { /* I2C_EN */
if (~value & (1 << 15)) { /* I2C_EN */
if (s->revision < OMAP2_INTR_REV) {
omap_i2c_reset(DEVICE(s));
}
@@ -351,14 +351,14 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
__func__);
break;
}
if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
(~value >> 9) & 1); /* TRX */
s->stat |= nack << 1; /* NACK */
s->control &= ~(1 << 0); /* STT */
if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
(~value >> 9) & 1); /* TRX */
s->stat |= nack << 1; /* NACK */
s->control &= ~(1 << 0); /* STT */
s->fifo = 0;
if (nack)
s->control &= ~(1 << 1); /* STP */
s->control &= ~(1 << 1); /* STP */
else {
s->count_cur = s->count;
omap_i2c_fifo_run(s);
@@ -367,34 +367,34 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
}
break;
case 0x28: /* I2C_OA */
case 0x28: /* I2C_OA */
s->addr[0] = value & 0x3ff;
break;
case 0x2c: /* I2C_SA */
case 0x2c: /* I2C_SA */
s->addr[1] = value & 0x3ff;
break;
case 0x30: /* I2C_PSC */
case 0x30: /* I2C_PSC */
s->divider = value;
break;
case 0x34: /* I2C_SCLL */
case 0x34: /* I2C_SCLL */
s->times[0] = value;
break;
case 0x38: /* I2C_SCLH */
case 0x38: /* I2C_SCLH */
s->times[1] = value;
break;
case 0x3c: /* I2C_SYSTEST */
case 0x3c: /* I2C_SYSTEST */
s->test = value & 0xf80f;
if (value & (1 << 11)) /* SBB */
if (value & (1 << 11)) /* SBB */
if (s->revision >= OMAP2_INTR_REV) {
s->stat |= 0x3f;
omap_i2c_interrupts_update(s);
}
if (value & (1 << 15)) { /* ST_EN */
if (value & (1 << 15)) { /* ST_EN */
qemu_log_mask(LOG_UNIMP,
"%s: System Test not supported\n", __func__);
}
@@ -413,7 +413,7 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x1c: /* I2C_DATA */
case 0x1c: /* I2C_DATA */
if (s->txlen > 2) {
/* XXX: remote access (qualifier) error - what's that? */
break;
@@ -421,9 +421,9 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
s->fifo <<= 8;
s->txlen += 1;
s->fifo |= value & 0xff;
s->stat &= ~(1 << 10); /* XUDF */
s->stat &= ~(1 << 10); /* XUDF */
if (s->txlen > 2)
s->stat &= ~(1 << 4); /* XRDY */
s->stat &= ~(1 << 4); /* XRDY */
omap_i2c_fifo_run(s);
omap_i2c_interrupts_update(s);
break;
hw/intc/omap_intc.c
+77 -77
View File
@@ -102,8 +102,8 @@ static inline void omap_inth_update(OMAPIntcState *s, int is_fiq)
}
}
#define INT_FALLING_EDGE 0
#define INT_LOW_LEVEL 1
#define INT_FALLING_EDGE 0
#define INT_LOW_LEVEL 1
static void omap_set_intr(void *opaque, int irq, int req)
{
@@ -142,13 +142,13 @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
offset &= 0xff;
switch (offset) {
case 0x00: /* ITR */
case 0x00: /* ITR */
return bank->irqs;
case 0x04: /* MIR */
case 0x04: /* MIR */
return bank->mask;
case 0x10: /* SIR_IRQ_CODE */
case 0x10: /* SIR_IRQ_CODE */
case 0x14: /* SIR_FIQ_CODE */
if (bank_no != 0)
break;
@@ -159,49 +159,49 @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
bank->irqs &= ~(1 << i);
return line_no;
case 0x18: /* CONTROL_REG */
case 0x18: /* CONTROL_REG */
if (bank_no != 0)
break;
return 0;
case 0x1c: /* ILR0 */
case 0x20: /* ILR1 */
case 0x24: /* ILR2 */
case 0x28: /* ILR3 */
case 0x2c: /* ILR4 */
case 0x30: /* ILR5 */
case 0x34: /* ILR6 */
case 0x38: /* ILR7 */
case 0x3c: /* ILR8 */
case 0x40: /* ILR9 */
case 0x44: /* ILR10 */
case 0x48: /* ILR11 */
case 0x4c: /* ILR12 */
case 0x50: /* ILR13 */
case 0x54: /* ILR14 */
case 0x58: /* ILR15 */
case 0x5c: /* ILR16 */
case 0x60: /* ILR17 */
case 0x64: /* ILR18 */
case 0x68: /* ILR19 */
case 0x6c: /* ILR20 */
case 0x70: /* ILR21 */
case 0x74: /* ILR22 */
case 0x78: /* ILR23 */
case 0x7c: /* ILR24 */
case 0x80: /* ILR25 */
case 0x84: /* ILR26 */
case 0x88: /* ILR27 */
case 0x8c: /* ILR28 */
case 0x90: /* ILR29 */
case 0x94: /* ILR30 */
case 0x98: /* ILR31 */
case 0x1c: /* ILR0 */
case 0x20: /* ILR1 */
case 0x24: /* ILR2 */
case 0x28: /* ILR3 */
case 0x2c: /* ILR4 */
case 0x30: /* ILR5 */
case 0x34: /* ILR6 */
case 0x38: /* ILR7 */
case 0x3c: /* ILR8 */
case 0x40: /* ILR9 */
case 0x44: /* ILR10 */
case 0x48: /* ILR11 */
case 0x4c: /* ILR12 */
case 0x50: /* ILR13 */
case 0x54: /* ILR14 */
case 0x58: /* ILR15 */
case 0x5c: /* ILR16 */
case 0x60: /* ILR17 */
case 0x64: /* ILR18 */
case 0x68: /* ILR19 */
case 0x6c: /* ILR20 */
case 0x70: /* ILR21 */
case 0x74: /* ILR22 */
case 0x78: /* ILR23 */
case 0x7c: /* ILR24 */
case 0x80: /* ILR25 */
case 0x84: /* ILR26 */
case 0x88: /* ILR27 */
case 0x8c: /* ILR28 */
case 0x90: /* ILR29 */
case 0x94: /* ILR30 */
case 0x98: /* ILR31 */
i = (offset - 0x1c) >> 2;
return (bank->priority[i] << 2) |
(((bank->sens_edge >> i) & 1) << 1) |
((bank->fiq >> i) & 1);
case 0x9c: /* ISR */
case 0x9c: /* ISR */
return 0x00000000;
}
@@ -219,24 +219,24 @@ static void omap_inth_write(void *opaque, hwaddr addr,
offset &= 0xff;
switch (offset) {
case 0x00: /* ITR */
case 0x00: /* ITR */
/* Important: ignore the clearing if the IRQ is level-triggered and
the input bit is 1 */
bank->irqs &= value | (bank->inputs & bank->sens_edge);
return;
case 0x04: /* MIR */
case 0x04: /* MIR */
bank->mask = value;
omap_inth_update(s, 0);
omap_inth_update(s, 1);
return;
case 0x10: /* SIR_IRQ_CODE */
case 0x14: /* SIR_FIQ_CODE */
case 0x10: /* SIR_IRQ_CODE */
case 0x14: /* SIR_FIQ_CODE */
OMAP_RO_REG(addr);
break;
case 0x18: /* CONTROL_REG */
case 0x18: /* CONTROL_REG */
if (bank_no != 0)
break;
if (value & 2) {
@@ -251,38 +251,38 @@ static void omap_inth_write(void *opaque, hwaddr addr,
}
return;
case 0x1c: /* ILR0 */
case 0x20: /* ILR1 */
case 0x24: /* ILR2 */
case 0x28: /* ILR3 */
case 0x2c: /* ILR4 */
case 0x30: /* ILR5 */
case 0x34: /* ILR6 */
case 0x38: /* ILR7 */
case 0x3c: /* ILR8 */
case 0x40: /* ILR9 */
case 0x44: /* ILR10 */
case 0x48: /* ILR11 */
case 0x4c: /* ILR12 */
case 0x50: /* ILR13 */
case 0x54: /* ILR14 */
case 0x58: /* ILR15 */
case 0x5c: /* ILR16 */
case 0x60: /* ILR17 */
case 0x64: /* ILR18 */
case 0x68: /* ILR19 */
case 0x6c: /* ILR20 */
case 0x70: /* ILR21 */
case 0x74: /* ILR22 */
case 0x78: /* ILR23 */
case 0x7c: /* ILR24 */
case 0x80: /* ILR25 */
case 0x84: /* ILR26 */
case 0x88: /* ILR27 */
case 0x8c: /* ILR28 */
case 0x90: /* ILR29 */
case 0x94: /* ILR30 */
case 0x98: /* ILR31 */
case 0x1c: /* ILR0 */
case 0x20: /* ILR1 */
case 0x24: /* ILR2 */
case 0x28: /* ILR3 */
case 0x2c: /* ILR4 */
case 0x30: /* ILR5 */
case 0x34: /* ILR6 */
case 0x38: /* ILR7 */
case 0x3c: /* ILR8 */
case 0x40: /* ILR9 */
case 0x44: /* ILR10 */
case 0x48: /* ILR11 */
case 0x4c: /* ILR12 */
case 0x50: /* ILR13 */
case 0x54: /* ILR14 */
case 0x58: /* ILR15 */
case 0x5c: /* ILR16 */
case 0x60: /* ILR17 */
case 0x64: /* ILR18 */
case 0x68: /* ILR19 */
case 0x6c: /* ILR20 */
case 0x70: /* ILR21 */
case 0x74: /* ILR22 */
case 0x78: /* ILR23 */
case 0x7c: /* ILR24 */
case 0x80: /* ILR25 */
case 0x84: /* ILR26 */
case 0x88: /* ILR27 */
case 0x8c: /* ILR28 */
case 0x90: /* ILR29 */
case 0x94: /* ILR30 */
case 0x98: /* ILR31 */
i = (offset - 0x1c) >> 2;
bank->priority[i] = (value >> 2) & 0x1f;
bank->sens_edge &= ~(1 << i);
@@ -291,7 +291,7 @@ static void omap_inth_write(void *opaque, hwaddr addr,
bank->fiq |= (value & 1) << i;
return;
case 0x9c: /* ISR */
case 0x9c: /* ISR */
for (i = 0; i < 32; i ++)
if (value & (1 << i)) {
omap_set_intr(s, 32 * bank_no + i, 1);
hw/misc/omap_clk.c
+235 -235
View File
File diff suppressed because it is too large Load Diff
hw/timer/pxa2xx_timer.c
+38 -38
View File
@@ -19,41 +19,41 @@
#include "qom/object.h"
#include "system/watchdog.h"
#define OSMR0 0x00
#define OSMR1 0x04
#define OSMR2 0x08
#define OSMR3 0x0c
#define OSMR4 0x80
#define OSMR5 0x84
#define OSMR6 0x88
#define OSMR7 0x8c
#define OSMR8 0x90
#define OSMR9 0x94
#define OSMR10 0x98
#define OSMR11 0x9c
#define OSCR 0x10 /* OS Timer Count */
#define OSCR4 0x40
#define OSCR5 0x44
#define OSCR6 0x48
#define OSCR7 0x4c
#define OSCR8 0x50
#define OSCR9 0x54
#define OSCR10 0x58
#define OSCR11 0x5c
#define OSSR 0x14 /* Timer status register */
#define OWER 0x18
#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
#define OMCR4 0xc0 /* OS Match Control registers */
#define OMCR5 0xc4
#define OMCR6 0xc8
#define OMCR7 0xcc
#define OMCR8 0xd0
#define OMCR9 0xd4
#define OMCR10 0xd8
#define OMCR11 0xdc
#define OSNR 0x20
#define OSMR0 0x00
#define OSMR1 0x04
#define OSMR2 0x08
#define OSMR3 0x0c
#define OSMR4 0x80
#define OSMR5 0x84
#define OSMR6 0x88
#define OSMR7 0x8c
#define OSMR8 0x90
#define OSMR9 0x94
#define OSMR10 0x98
#define OSMR11 0x9c
#define OSCR 0x10 /* OS Timer Count */
#define OSCR4 0x40
#define OSCR5 0x44
#define OSCR6 0x48
#define OSCR7 0x4c
#define OSCR8 0x50
#define OSCR9 0x54
#define OSCR10 0x58
#define OSCR11 0x5c
#define OSSR 0x14 /* Timer status register */
#define OWER 0x18
#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
#define OMCR4 0xc0 /* OS Match Control registers */
#define OMCR5 0xc4
#define OMCR6 0xc8
#define OMCR7 0xcc
#define OMCR8 0xd0
#define OMCR9 0xd4
#define OMCR10 0xd8
#define OMCR11 0xdc
#define OSNR 0x20
#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
static int pxa2xx_timer4_freq[8] = {
[0] = 0,
@@ -106,7 +106,7 @@ struct PXA2xxTimerInfo {
PXA2xxTimer4 tm4[8];
};
#define PXA2XX_TIMER_HAVE_TM4 0
#define PXA2XX_TIMER_HAVE_TM4 0
static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
{
@@ -230,7 +230,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
NANOSECONDS_PER_SECOND);
case OIER:
return s->irq_enabled;
case OSSR: /* Status register */
case OSSR: /* Status register */
return s->events;
case OWER:
return s->reset3;
@@ -336,7 +336,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
case OIER:
s->irq_enabled = value & 0xfff;
break;
case OSSR: /* Status register */
case OSSR: /* Status register */
value &= s->events;
s->events &= ~value;
for (i = 0; i < 4; i ++, value >>= 1)
@@ -345,7 +345,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
qemu_irq_lower(s->irq4);
break;
case OWER: /* XXX: Reset on OSMR3 match? */
case OWER: /* XXX: Reset on OSMR3 match? */
s->reset3 = value;
break;
case OMCR7: tm ++;
include/hw/arm/omap.h
+267 -267
View File
File diff suppressed because it is too large Load Diff
include/hw/arm/sharpsl.h
+1 -1
View File
@@ -11,7 +11,7 @@
/* zaurus.c */
#define SL_PXA_PARAM_BASE 0xa0000a00
#define SL_PXA_PARAM_BASE 0xa0000a00
void sl_bootparam_write(hwaddr ptr);
#endif
include/hw/arm/soc_dma.h
+2 -2
View File
@@ -54,7 +54,7 @@ struct soc_dma_ch_s {
int bytes;
/* Initialised by the DMA module, call soc_dma_ch_update after writing. */
enum soc_dma_access_type type[2];
hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
/* Private */
void *paddr[2];
soc_dma_io_t io_fn[2];
@@ -70,7 +70,7 @@ struct soc_dma_ch_s {
struct soc_dma_s {
/* Following fields are set by the SoC DMA module and can be used
* by anybody. */
uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
qemu_irq *drq;
void *opaque;
int64_t freq;