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Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into staging

Browse Source 
Misc hardware patch queue

HW emulation:
- PMBus fixes and tests (Titus)
- IDE fixes and tests (Fiona)
- New ADM1266 sensor (Titus)
- Better error propagation in PCI-ISA i82378 (Philippe)
- Declare SD model QOM types using DEFINE_TYPES macro (Philippe)

Topology:
- Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu)

Monitor:
- Synchronize CPU state in 'info lapic' (Dongli Zhang)

QOM:
- Have 'cpu-qom.h' target-agnostic (Philippe)
- Move ArchCPUClass definition to each target's cpu.h (Philippe)
- Call object_class_is_abstract once in cpu_class_by_name (Philippe)

UI:
- Use correct key names in titles on MacOS / SDL2 (Adrian)

MIPS:
- Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe)

Nios2:
- Create IRQs *after* vCPU is realized (Philippe)

PPC:
- Restrict KVM objects to system emulation (Philippe)
- Move target-specific definitions out of 'cpu-qom.h' (Philippe)

S390X:
- Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe)

X86:
- HVF & KVM cleanups (Philippe)

Various targets:
- Use env_archcpu() to optimize (Philippe)

Misc:
- Few global variable shadowing removed (Philippe)
- Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe)
- Remove few more 'softmmu' mentions (Philippe)
- Fix and cleanup in vl.c (Akihiko & Marc-André)
- Resource leak fix in dump (Zongmin Zhou)
- MAINTAINERS updates (Thomas, Daniel)

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# gpg: Signature made Tue 07 Nov 2023 20:15:29 HKT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'misc-cpus-20231107' of https://github.com/philmd/qemu: (75 commits)
  dump: Add close fd on error return to avoid resource leak
  ui/sdl2: use correct key names in win title on mac
  MAINTAINERS: Add more guest-agent related files to the corresponding section
  MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section
  MAINTAINERS: update libvirt devel mailing list address
  MAINTAINERS: Add the CAN documentation file to the CAN section
  MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section
  hw/sd: Declare QOM types using DEFINE_TYPES() macro
  hw/i2c: pmbus: reset page register for out of range reads
  hw/i2c: pmbus: immediately clear faults on request
  tests/qtest: add tests for ADM1266
  hw/sensor: add ADM1266 device model
  hw/i2c: pmbus: add VCAP register
  hw/i2c: pmbus: add fan support
  hw/i2c: pmbus: add vout mode bitfields
  hw/i2c: pmbus add support for block receive
  tests/qtest: ahci-test: add test exposing reset issue with pending callback
  hw/ide: reset: cancel async DMA operation before resetting state
  hw/cpu: Update the comments of nr_cores and nr_dies
  system/cpus: Fix CPUState.nr_cores' calculation
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
2023-11-08 08:32:26 +08:00
parent 462ad017ed 95a40c4450
commit ed1d873caa
134 changed files with 1722 additions and 1085 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+9 -3
View File
@@ -859,8 +859,10 @@ M: Hao Wu <wuhaotsh@google.com>
L: qemu-arm@nongnu.org
S: Supported
F: hw/*/npcm*
F: hw/sensor/adm1266.c
F: include/hw/*/npcm*
F: tests/qtest/npcm*
F: tests/qtest/adm1266-test.c
F: pc-bios/npcm7xx_bootrom.bin
F: roms/vbootrom
F: docs/system/arm/nuvoton.rst
@@ -1615,6 +1617,7 @@ F: hw/intc/sh_intc.c
F: hw/pci-host/sh_pci.c
F: hw/timer/sh_timer.c
F: include/hw/sh4/sh_intc.h
F: include/hw/timer/tmu012.h
Shix
R: Yoshinori Sato <ysato@users.sourceforge.jp>
@@ -1772,7 +1775,7 @@ F: include/hw/southbridge/ich9.h
F: include/hw/southbridge/piix.h
F: hw/isa/apm.c
F: include/hw/isa/apm.h
F: tests/unit/test-x86-cpuid.c
F: tests/unit/test-x86-topo.c
F: tests/qtest/test-x86-cpuid-compat.c
PC Chipset
@@ -1858,6 +1861,7 @@ M: Max Filippov <jcmvbkbc@gmail.com>
S: Maintained
F: hw/xtensa/xtfpga.c
F: hw/net/opencores_eth.c
F: include/hw/xtensa/mx_pic.h
Devices
-------
@@ -2594,6 +2598,7 @@ W: https://canbus.pages.fel.cvut.cz/
F: net/can/*
F: hw/net/can/*
F: include/net/can_*.h
F: docs/system/devices/can.rst
OpenPIC interrupt controller
M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
@@ -3149,10 +3154,11 @@ M: Michael Roth <michael.roth@amd.com>
M: Konstantin Kostiuk <kkostiuk@redhat.com>
S: Maintained
F: qga/
F: contrib/systemd/qemu-guest-agent.service
F: docs/interop/qemu-ga.rst
F: docs/interop/qemu-ga-ref.rst
F: scripts/qemu-guest-agent/
F: tests/unit/test-qga.c
F: tests/*/test-qga*
T: git https://github.com/mdroth/qemu.git qga
QEMU Guest Agent Win32
@@ -4062,7 +4068,7 @@ F: gitdm.config
F: contrib/gitdm/*
Incompatible changes
R: libvir-list@redhat.com
R: devel@lists.libvirt.org
F: docs/about/deprecated.rst
Build System
accel/stubs/tcg-stub.c
-4
View File
@@ -22,10 +22,6 @@ void tlb_set_dirty(CPUState *cpu, vaddr vaddr)
{
}
void tcg_flush_jmp_cache(CPUState *cpu)
{
}
int probe_access_flags(CPUArchState *env, vaddr addr, int size,
MMUAccessType access_type, int mmu_idx,
bool nonfault, void **phost, uintptr_t retaddr)
accel/tcg/cputlb.c
+1
View File
@@ -24,6 +24,7 @@
#include "exec/memory.h"
#include "exec/cpu_ldst.h"
#include "exec/cputlb.h"
#include "exec/tb-flush.h"
#include "exec/memory-internal.h"
#include "exec/ram_addr.h"
#include "tcg/tcg.h"
accel/tcg/tcg-accel-ops.c
+9
View File
@@ -34,6 +34,7 @@
#include "qemu/timer.h"
#include "exec/exec-all.h"
#include "exec/hwaddr.h"
#include "exec/tb-flush.h"
#include "exec/gdbstub.h"
#include "tcg-accel-ops.h"
@@ -77,6 +78,13 @@ int tcg_cpus_exec(CPUState *cpu)
return ret;
}
static void tcg_cpu_reset_hold(CPUState *cpu)
{
tcg_flush_jmp_cache(cpu);
tlb_flush(cpu);
}
/* mask must never be zero, except for A20 change call */
void tcg_handle_interrupt(CPUState *cpu, int mask)
{
@@ -205,6 +213,7 @@ static void tcg_accel_ops_init(AccelOpsClass *ops)
}
}
ops->cpu_reset_hold = tcg_cpu_reset_hold;
ops->supports_guest_debug = tcg_supports_guest_debug;
ops->insert_breakpoint = tcg_insert_breakpoint;
ops->remove_breakpoint = tcg_remove_breakpoint;
accel/tcg/translate-all.c
-8
View File
@@ -673,11 +673,3 @@ void tcg_flush_jmp_cache(CPUState *cpu)
qatomic_set(&jc->array[i].tb, NULL);
}
}
/* This is a wrapper for common code that can not use CONFIG_SOFTMMU */
void tcg_flush_softmmu_tlb(CPUState *cs)
{
#ifdef CONFIG_SOFTMMU
tlb_flush(cs);
#endif
}
accel/tcg/user-exec-stub.c
+4
View File
@@ -14,6 +14,10 @@ void qemu_init_vcpu(CPUState *cpu)
{
}
void cpu_exec_reset_hold(CPUState *cpu)
{
}
/* User mode emulation does not support record/replay yet. */
bool replay_exception(void)
bsd-user/main.c
+1 -1
View File
@@ -118,7 +118,7 @@ void fork_end(int child)
*/
CPU_FOREACH_SAFE(cpu, next_cpu) {
if (cpu != thread_cpu) {
QTAILQ_REMOVE_RCU(&cpus, cpu, node);
QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node);
}
}
mmap_fork_end(child);
cpu-common.c
+3 -3
View File
@@ -73,7 +73,7 @@ static int cpu_get_free_index(void)
return max_cpu_index;
}
CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
CPUTailQ cpus_queue = QTAILQ_HEAD_INITIALIZER(cpus_queue);
static unsigned int cpu_list_generation_id;
unsigned int cpu_list_generation_id_get(void)
@@ -90,7 +90,7 @@ void cpu_list_add(CPUState *cpu)
} else {
assert(!cpu_index_auto_assigned);
}
QTAILQ_INSERT_TAIL_RCU(&cpus, cpu, node);
QTAILQ_INSERT_TAIL_RCU(&cpus_queue, cpu, node);
cpu_list_generation_id++;
}
@@ -102,7 +102,7 @@ void cpu_list_remove(CPUState *cpu)
return;
}
QTAILQ_REMOVE_RCU(&cpus, cpu, node);
QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu_list_generation_id++;
}
cpu-target.c
+4 -2
View File
@@ -131,13 +131,13 @@ const VMStateDescription vmstate_cpu_common = {
};
#endif
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
/* cache the cpu class for the hotpath */
cpu->cc = CPU_GET_CLASS(cpu);
if (!accel_cpu_common_realize(cpu, errp)) {
return;
return false;
}
/* Wait until cpu initialization complete before exposing cpu. */
@@ -159,6 +159,8 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
return true;
}
void cpu_exec_unrealizefn(CPUState *cpu)
dump/dump.c
+1
View File
@@ -2160,6 +2160,7 @@ void qmp_dump_guest_memory(bool paging, const char *protocol,
return;
}
if (kdump_raw && lseek(fd, 0, SEEK_CUR) == (off_t) -1) {
close(fd);
error_setg(errp, "kdump-raw formats require a seekable file");
return;
}
hw/arm/Kconfig
+1
View File
@@ -491,6 +491,7 @@ config NPCM7XX
default y
depends on TCG && ARM
select A9MPCORE
select ADM1266
select ADM1272
select ARM_GIC
select SMBUS
hw/core/cpu-common.c
+12 -7
View File
@@ -136,10 +136,7 @@ static void cpu_common_reset_hold(Object *obj)
cpu->crash_occurred = false;
cpu->cflags_next_tb = -1;
if (tcg_enabled()) {
tcg_flush_jmp_cache(cpu);
tcg_flush_softmmu_tlb(cpu);
}
cpu_exec_reset_hold(cpu);
}
static bool cpu_common_has_work(CPUState *cs)
@@ -149,10 +146,18 @@ static bool cpu_common_has_work(CPUState *cs)
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
{
CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
ObjectClass *oc;
CPUClass *cc;
assert(cpu_model && cc->class_by_name);
return cc->class_by_name(cpu_model);
oc = object_class_by_name(typename);
cc = CPU_CLASS(oc);
assert(cc->class_by_name);
assert(cpu_model);
oc = cc->class_by_name(cpu_model);
if (oc == NULL || object_class_is_abstract(oc)) {
return NULL;
}
return oc;
}
static void cpu_common_parse_features(const char *typename, char *features,
hw/core/loader.c
+2 -2
View File
@@ -1070,7 +1070,7 @@ static void *rom_set_mr(Rom *rom, Object *owner, const char *name, bool ro)
ssize_t rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex,
bool option_rom, MemoryRegion *mr,
bool has_option_rom, MemoryRegion *mr,
AddressSpace *as)
{
MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
@@ -1139,7 +1139,7 @@ ssize_t rom_add_file(const char *file, const char *fw_dir,
basename);
snprintf(devpath, sizeof(devpath), "/rom@%s", fw_file_name);
if ((!option_rom || mc->option_rom_has_mr) && mc->rom_file_has_mr) {
if ((!has_option_rom || mc->option_rom_has_mr) && mc->rom_file_has_mr) {
data = rom_set_mr(rom, OBJECT(fw_cfg), devpath, true);
} else {
data = rom->data;
hw/i2c/pmbus_device.c
+227 -10
View File
@@ -102,7 +102,6 @@ void pmbus_send_string(PMBusDevice *pmdev, const char *data)
}
size_t len = strlen(data);
g_assert(len > 0);
g_assert(len + pmdev->out_buf_len < SMBUS_DATA_MAX_LEN);
pmdev->out_buf[len + pmdev->out_buf_len] = len;
@@ -112,6 +111,35 @@ void pmbus_send_string(PMBusDevice *pmdev, const char *data)
pmdev->out_buf_len += len + 1;
}
uint8_t pmbus_receive_block(PMBusDevice *pmdev, uint8_t *dest, size_t len)
{
/* dest may contain data from previous writes */
memset(dest, 0, len);
/* Exclude command code from return value */
pmdev->in_buf++;
pmdev->in_buf_len--;
/* The byte after the command code denotes the length */
uint8_t sent_len = pmdev->in_buf[0];
if (sent_len != pmdev->in_buf_len - 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: length mismatch. Expected %d bytes, got %d bytes\n",
__func__, sent_len, pmdev->in_buf_len - 1);
}
/* exclude length byte */
pmdev->in_buf++;
pmdev->in_buf_len--;
if (pmdev->in_buf_len < len) {
len = pmdev->in_buf_len;
}
memcpy(dest, pmdev->in_buf, len);
return len;
}
static uint64_t pmbus_receive_uint(PMBusDevice *pmdev)
{
@@ -472,6 +500,54 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd)
}
break;
case PMBUS_FAN_CONFIG_1_2: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].fan_config_1_2);
} else {
goto passthough;
}
break;
case PMBUS_FAN_COMMAND_1: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].fan_command_1);
} else {
goto passthough;
}
break;
case PMBUS_FAN_COMMAND_2: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].fan_command_2);
} else {
goto passthough;
}
break;
case PMBUS_FAN_CONFIG_3_4: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].fan_config_3_4);
} else {
goto passthough;
}
break;
case PMBUS_FAN_COMMAND_3: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].fan_command_3);
} else {
goto passthough;
}
break;
case PMBUS_FAN_COMMAND_4: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].fan_command_4);
} else {
goto passthough;
}
break;
case PMBUS_VOUT_OV_FAULT_LIMIT: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_VOUT) {
pmbus_send16(pmdev, pmdev->pages[index].vout_ov_fault_limit);
@@ -782,6 +858,22 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd)
pmbus_send8(pmdev, pmdev->pages[index].status_mfr_specific);
break;
case PMBUS_STATUS_FANS_1_2: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].status_fans_1_2);
} else {
goto passthough;
}
break;
case PMBUS_STATUS_FANS_3_4: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].status_fans_3_4);
} else {
goto passthough;
}
break;
case PMBUS_READ_EIN: /* Read-Only block 5 bytes */
if (pmdev->pages[index].page_flags & PB_HAS_EIN) {
pmbus_send(pmdev, pmdev->pages[index].read_ein, 5);
@@ -814,6 +906,14 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd)
}
break;
case PMBUS_READ_VCAP: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_VCAP) {
pmbus_send16(pmdev, pmdev->pages[index].read_vcap);
} else {
goto passthough;
}
break;
case PMBUS_READ_VOUT: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_VOUT) {
pmbus_send16(pmdev, pmdev->pages[index].read_vout);
@@ -854,6 +954,54 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd)
}
break;
case PMBUS_READ_FAN_SPEED_1: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_1);
} else {
goto passthough;
}
break;
case PMBUS_READ_FAN_SPEED_2: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_2);
} else {
goto passthough;
}
break;
case PMBUS_READ_FAN_SPEED_3: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_3);
} else {
goto passthough;
}
break;
case PMBUS_READ_FAN_SPEED_4: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_4);
} else {
goto passthough;
}
break;
case PMBUS_READ_DUTY_CYCLE: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_duty_cycle);
} else {
goto passthough;
}
break;
case PMBUS_READ_FREQUENCY: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_frequency);
} else {
goto passthough;
}
break;
case PMBUS_READ_POUT: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_POUT) {
pmbus_send16(pmdev, pmdev->pages[index].read_pout);
@@ -1096,12 +1244,26 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len)
pmdev->in_buf = buf;
pmdev->code = buf[0]; /* PMBus command code */
if (pmdev->code == PMBUS_CLEAR_FAULTS) {
pmbus_clear_faults(pmdev);
}
if (len == 1) { /* Single length writes are command codes only */
return 0;
}
if (pmdev->code == PMBUS_PAGE) {
pmdev->page = pmbus_receive8(pmdev);
if (pmdev->page > pmdev->num_pages - 1 && pmdev->page != PB_ALL_PAGES) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: page %u is out of range\n",
__func__, pmdev->page);
pmdev->page = 0; /* undefined behaviour - reset to page 0 */
pmbus_cml_error(pmdev);
return PMBUS_ERR_BYTE;
}
return 0;
}
@@ -1115,15 +1277,6 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len)
return 0;
}
if (pmdev->page > pmdev->num_pages - 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: page %u is out of range\n",
__func__, pmdev->page);
pmdev->page = 0; /* undefined behaviour - reset to page 0 */
pmbus_cml_error(pmdev);
return PMBUS_ERR_BYTE;
}
index = pmdev->page;
switch (pmdev->code) {
@@ -1277,6 +1430,54 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len)
}
break;
case PMBUS_FAN_CONFIG_1_2: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_config_1_2 = pmbus_receive8(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_FAN_COMMAND_1: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_command_1 = pmbus_receive16(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_FAN_COMMAND_2: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_command_2 = pmbus_receive16(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_FAN_CONFIG_3_4: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_config_3_4 = pmbus_receive8(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_FAN_COMMAND_3: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_command_3 = pmbus_receive16(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_FAN_COMMAND_4: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_command_4 = pmbus_receive16(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_VOUT_OV_FAULT_LIMIT: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_VOUT) {
pmdev->pages[index].vout_ov_fault_limit = pmbus_receive16(pmdev);
@@ -1582,6 +1783,22 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len)
pmdev->pages[index].status_mfr_specific = pmbus_receive8(pmdev);
break;
case PMBUS_STATUS_FANS_1_2: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].status_fans_1_2);
} else {
goto passthrough;
}
break;
case PMBUS_STATUS_FANS_3_4: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].status_fans_3_4);
} else {
goto passthrough;
}
break;
case PMBUS_PAGE_PLUS_READ: /* Block Read-only */
case PMBUS_CAPABILITY: /* Read-Only byte */
case PMBUS_COEFFICIENTS: /* Read-only block 5 bytes */
hw/ide/core.c
+7 -7
View File
@@ -2515,19 +2515,19 @@ static void ide_dummy_transfer_stop(IDEState *s)
void ide_bus_reset(IDEBus *bus)
{
bus->unit = 0;
bus->cmd = 0;
ide_reset(&bus->ifs[0]);
ide_reset(&bus->ifs[1]);
ide_clear_hob(bus);
/* pending async DMA */
/* pending async DMA - needs the IDEState before it is reset */
if (bus->dma->aiocb) {
trace_ide_bus_reset_aio();
blk_aio_cancel(bus->dma->aiocb);
bus->dma->aiocb = NULL;
}
bus->unit = 0;
bus->cmd = 0;
ide_reset(&bus->ifs[0]);
ide_reset(&bus->ifs[1]);
ide_clear_hob(bus);
/* reset dma provider too */
if (bus->dma->ops->reset) {
bus->dma->ops->reset(bus->dma);
hw/isa/i82378.c
+3 -1
View File
@@ -105,7 +105,9 @@ static void i82378_realize(PCIDevice *pci, Error **errp)
/* speaker */
pcspk = isa_new(TYPE_PC_SPEAKER);
object_property_set_link(OBJECT(pcspk), "pit", OBJECT(pit), &error_fatal);
isa_realize_and_unref(pcspk, isabus, &error_fatal);
if (!isa_realize_and_unref(pcspk, isabus, errp)) {
return;
}
/* 2 82C37 (dma) */
isa_create_simple(isabus, "i82374");
hw/ppc/e500.c
+4
View File
@@ -834,6 +834,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
IrqLines *irqs, Error **errp)
{
#ifdef CONFIG_KVM
DeviceState *dev;
CPUState *cs;
@@ -854,6 +855,9 @@ static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
}
return dev;
#else
g_assert_not_reached();
#endif
}
static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
hw/s390x/css.c
+2 -1
View File
@@ -644,8 +644,9 @@ void css_conditional_io_interrupt(SubchDev *sch)
}
}
int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode)
int css_do_sic(S390CPU *cpu, uint8_t isc, uint16_t mode)
{
CPUS390XState *env = &cpu->env;
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = s390_get_flic_class(fs);
int r;
hw/s390x/sclp.c
+4 -3
View File
@@ -269,9 +269,9 @@ static void sclp_execute(SCLPDevice *sclp, SCCB *sccb, uint32_t code)
* service_interrupt call.
*/
#define SCLP_PV_DUMMY_ADDR 0x4000
int sclp_service_call_protected(CPUS390XState *env, uint64_t sccb,
uint32_t code)
int sclp_service_call_protected(S390CPU *cpu, uint64_t sccb, uint32_t code)
{
CPUS390XState *env = &cpu->env;
SCLPDevice *sclp = get_sclp_device();
SCLPDeviceClass *sclp_c = SCLP_GET_CLASS(sclp);
SCCBHeader header;
@@ -296,8 +296,9 @@ out_write:
return 0;
}
int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code)
int sclp_service_call(S390CPU *cpu, uint64_t sccb, uint32_t code)
{
CPUS390XState *env = &cpu->env;
SCLPDevice *sclp = get_sclp_device();
SCLPDeviceClass *sclp_c = SCLP_GET_CLASS(sclp);
SCCBHeader header;
hw/sd/aspeed_sdhci.c
+8 -11
View File
@@ -198,16 +198,13 @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
device_class_set_props(dc, aspeed_sdhci_properties);
}
static const TypeInfo aspeed_sdhci_info = {
.name = TYPE_ASPEED_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AspeedSDHCIState),
.class_init = aspeed_sdhci_class_init,
static const TypeInfo aspeed_sdhci_types[] = {
{
.name = TYPE_ASPEED_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AspeedSDHCIState),
.class_init = aspeed_sdhci_class_init,
},
};
static void aspeed_sdhci_register_types(void)
{
type_register_static(&aspeed_sdhci_info);
}
type_init(aspeed_sdhci_register_types)
DEFINE_TYPES(aspeed_sdhci_types)

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