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Merge tag 'pull-target-arm-20241029' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

Browse Source 
target-arm queue:
 * arm/kvm: add support for MTE
 * docs/system/cpu-hotplug: Update example's socket-id/core-id
 * target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr
 * target/arm: Don't assert in regime_is_user() for E10 mmuidx values
 * hw/sd/omap_mmc: Fix breakage of OMAP MMC controller
 * tests/functional: Add functional tests for collie, sx1
 * scripts/symlink-install-tree.py: Fix MESONINTROSPECT parsing
 * docs/system/arm: Document remaining undocumented boards
 * target/arm: Fix arithmetic underflow in SETM instruction
 * docs/devel/reset: Fix minor grammatical error
 * target/arm: kvm: require KVM_CAP_DEVICE_CTRL

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# gpg: Signature made Tue 29 Oct 2024 15:08:54 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20241029' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: kvm: require KVM_CAP_DEVICE_CTRL
  docs/devel/reset: Fix minor grammatical error
  target/arm: Fix arithmetic underflow in SETM instruction
  docs/system/target-arm.rst: Remove "many boards are undocumented" note
  docs/system/arm: Add placeholder docs for mcimx6ul-evk and mcimx7d-sabre
  docs/system/arm: Add placeholder doc for xlnx-zcu102 board
  docs/system/arm: Add placeholder doc for exynos4 boards
  docs/system/arm: Split fby35 out from aspeed.rst
  docs/system/arm: Don't use wildcard '*-bmc' in doc titles
  docs/system/arm/stm32: List olimex-stm32-h405 in document title
  scripts/symlink-install-tree.py: Fix MESONINTROSPECT parsing
  tests/functional: Add a functional test for the sx1 board
  tests/functional: Add a functional test for the collie board
  hw/sd/omap_mmc: Don't use sd_cmd_type_t
  target/arm: Don't assert in regime_is_user() for E10 mmuidx values
  target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr
  docs/system/cpu-hotplug: Update example's socket-id/core-id
  arm/kvm: add support for MTE

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2024-10-31 13:28:57 +00:00
parent e4bad9cc5e 84f298ea3e
commit ea8ae47bdd
28 changed files with 428 additions and 213 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+6
View File
@@ -716,6 +716,7 @@ L: qemu-arm@nongnu.org
S: Odd Fixes
F: hw/*/exynos*
F: include/hw/*/exynos*
F: docs/system/arm/exynos.rst
Calxeda Highbank
M: Rob Herring <robh@kernel.org>
@@ -790,6 +791,7 @@ F: hw/arm/fsl-imx6ul.c
F: hw/misc/imx6ul_ccm.c
F: include/hw/arm/fsl-imx6ul.h
F: include/hw/misc/imx6ul_ccm.h
F: docs/system/arm/mcimx6ul-evk.rst
MCIMX7D SABRE / i.MX7
M: Peter Maydell <peter.maydell@linaro.org>
@@ -803,6 +805,7 @@ F: include/hw/arm/fsl-imx7.h
F: include/hw/misc/imx7_*.h
F: hw/pci-host/designware.c
F: include/hw/pci-host/designware.h
F: docs/system/arm/mcimx7d-sabre.rst
MPS2 / MPS3
M: Peter Maydell <peter.maydell@linaro.org>
@@ -929,6 +932,7 @@ F: hw/arm/strongarm*
F: hw/gpio/zaurus.c
F: include/hw/arm/sharpsl.h
F: docs/system/arm/collie.rst
F: tests/functional/test_arm_collie.py
Stellaris
M: Peter Maydell <peter.maydell@linaro.org>
@@ -1016,6 +1020,7 @@ F: include/hw/ssi/xilinx_spips.h
F: hw/display/dpcd.c
F: include/hw/display/dpcd.h
F: docs/system/arm/xlnx-versal-virt.rst
F: docs/system/arm/xlnx-zcu102.rst
Xilinx Versal OSPI
M: Francisco Iglesias <francisco.iglesias@amd.com>
@@ -1122,6 +1127,7 @@ F: include/hw/*/*aspeed*
F: hw/net/ftgmac100.c
F: include/hw/net/ftgmac100.h
F: docs/system/arm/aspeed.rst
F: docs/system/arm/fby35.rst
F: tests/*/*aspeed*
F: tests/*/*ast2700*
F: hw/arm/fby35.c
docs/devel/reset.rst
+2 -2
View File
@@ -286,8 +286,8 @@ every reset child of the given resettable object. All children must be
resettable too. Additional parameters (a reset type and an opaque pointer) must
be passed to the callback too.
In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located
``DeviceState`` and ``BusState`` structure. ``child_foreach()`` is implemented
In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located in the
``DeviceState`` and ``BusState`` structures. ``child_foreach()`` is implemented
to follow the bus hierarchy; for a bus, it calls the function on every child
device; for a device, it calls the function on every bus child. When we reset
the main system bus, we reset the whole machine bus tree.
docs/system/arm/aspeed.rst
+2 -50
View File
@@ -1,5 +1,5 @@
Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``)
===================================================================================
Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
========================================================================================================================================================================================================================================================================================================================================================================================================
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
Aspeed evaluation boards. They are based on different releases of the
@@ -257,51 +257,3 @@ To boot a kernel directly from a Zephyr build tree:
$ qemu-system-arm -M ast1030-evb -nographic \
-kernel zephyr.elf
Facebook Yosemite v3.5 Platform and CraterLake Server (``fby35``)
==================================================================
Facebook has a series of multi-node compute server designs named
Yosemite. The most recent version released was
`Yosemite v3 <https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf>`__.
Yosemite v3.5 is an iteration on this design, and is very similar: there's a
baseboard with a BMC, and 4 server slots. The new server board design termed
"CraterLake" includes a Bridge IC (BIC), with room for expansion boards to
include various compute accelerators (video, inferencing, etc). At the moment,
only the first server slot's BIC is included.
Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds
can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__
for an example.
In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC
runs `OpenBMC <https://github.com/facebook/openbmc>`__, and the BIC runs
`OpenBIC <https://github.com/facebook/openbic>`__.
Firmware images can be retrieved from the Github releases or built from the
source code, see the README's for instructions on that. This image uses the
"fby35" machine recipe from OpenBMC, and the "yv35-cl" target from OpenBIC.
Some reference images can also be found here:
.. code-block:: bash
$ wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
$ wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
Since this machine has multiple SoC's, each with their own serial console, the
recommended way to run it is to allocate a pseudoterminal for each serial
console and let the monitor use stdio. Also, starting in a paused state is
useful because it allows you to attach to the pseudoterminals before the boot
process starts.
.. code-block:: bash
$ qemu-system-arm -machine fby35 \
-drive file=fby35.mtd,format=raw,if=mtd \
-device loader,file=Y35BCL.elf,addr=0,cpu-num=2 \
-serial pty -serial pty -serial mon:stdio \
-display none -S
$ screen /dev/tty0 # In a separate TMUX pane, terminal window, etc.
$ screen /dev/tty1
$ (qemu) c # Start the boot process once screen is setup.
docs/system/arm/exynos.rst
+9
View File
@@ -0,0 +1,9 @@
Exynos4 boards (``nuri``, ``smdkc210``)
=======================================
These are machines which use the Samsung Exynos4210 SoC, which has Cortex-A9 CPUs.
``nuri`` models the Samsung NURI board.
``smdkc210`` models the Samsung SMDKC210 board.
docs/system/arm/fby35.rst
+47
View File
@@ -0,0 +1,47 @@
Facebook Yosemite v3.5 Platform and CraterLake Server (``fby35``)
==================================================================
Facebook has a series of multi-node compute server designs named
Yosemite. The most recent version released was
`Yosemite v3 <https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf>`__.
Yosemite v3.5 is an iteration on this design, and is very similar: there's a
baseboard with a BMC, and 4 server slots. The new server board design termed
"CraterLake" includes a Bridge IC (BIC), with room for expansion boards to
include various compute accelerators (video, inferencing, etc). At the moment,
only the first server slot's BIC is included.
Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds
can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__
for an example.
In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC
runs `OpenBMC <https://github.com/facebook/openbmc>`__, and the BIC runs
`OpenBIC <https://github.com/facebook/openbic>`__.
Firmware images can be retrieved from the Github releases or built from the
source code, see the README's for instructions on that. This image uses the
"fby35" machine recipe from OpenBMC, and the "yv35-cl" target from OpenBIC.
Some reference images can also be found here:
.. code-block:: bash
$ wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
$ wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
Since this machine has multiple SoC's, each with their own serial console, the
recommended way to run it is to allocate a pseudoterminal for each serial
console and let the monitor use stdio. Also, starting in a paused state is
useful because it allows you to attach to the pseudoterminals before the boot
process starts.
.. code-block:: bash
$ qemu-system-arm -machine fby35 \
-drive file=fby35.mtd,format=raw,if=mtd \
-device loader,file=Y35BCL.elf,addr=0,cpu-num=2 \
-serial pty -serial pty -serial mon:stdio \
-display none -S
$ screen /dev/tty0 # In a separate TMUX pane, terminal window, etc.
$ screen /dev/tty1
$ (qemu) c # Start the boot process once screen is setup.
docs/system/arm/mcimx6ul-evk.rst
+5
View File
@@ -0,0 +1,5 @@
NXP MCIMX6UL-EVK (``mcimx6ul-evk``)
===================================
The ``mcimx6ul-evk`` machine models the NXP i.MX6UltraLite Evaluation Kit
MCIMX6UL-EVK development board. It has a single Cortex-A7 CPU.
docs/system/arm/mcimx7d-sabre.rst
+5
View File
@@ -0,0 +1,5 @@
NXP MCIMX7D Sabre (``mcimx7d-sabre``)
=====================================
The ``mcimx7d-sabre`` machine models the NXP SABRE Board MCIMX7SABRE,
based an an i.MX7Dual SoC.
docs/system/arm/nuvoton.rst
+2 -2
View File
@@ -1,5 +1,5 @@
Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
================================================================
Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj``)
=====================================================================================================
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
designed to be used as Baseboard Management Controllers (BMCs) in various
docs/system/arm/stm32.rst
+2 -2
View File
@@ -1,5 +1,5 @@
STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``)
========================================================================================
STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vldiscovery``)
===============================================================================================================
The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
STMicroelectronics.
docs/system/arm/xlnx-zcu102.rst
+19
View File
@@ -0,0 +1,19 @@
Xilinx ZynqMP ZCU102 (``xlnx-zcu102``)
======================================
The ``xlnx-zcu102`` board models the Xilinx ZynqMP ZCU102 board.
This board has 4 Cortex-A53 CPUs and 2 Cortex-R5F CPUs.
Machine-specific options
""""""""""""""""""""""""
The following machine-specific options are supported:
secure
Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
Arm Security Extensions (TrustZone). The default is ``off``.
virtualization
Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
Arm Virtualization Extensions. The default is ``off``.
docs/system/cpu-hotplug.rst
+27 -29
View File
@@ -33,23 +33,23 @@ vCPU hotplug
{
"return": [
{
"type": "IvyBridge-IBRS-x86_64-cpu",
"vcpus-count": 1,
"props": {
"socket-id": 1,
"core-id": 0,
"core-id": 1,
"socket-id": 0,
"thread-id": 0
}
},
"type": "IvyBridge-IBRS-x86_64-cpu",
"vcpus-count": 1
},
{
"props": {
"core-id": 0,
"socket-id": 0,
"thread-id": 0
},
"qom-path": "/machine/unattached/device[0]",
"type": "IvyBridge-IBRS-x86_64-cpu",
"vcpus-count": 1,
"props": {
"socket-id": 0,
"core-id": 0,
"thread-id": 0
}
"vcpus-count": 1
}
]
}
@@ -58,18 +58,18 @@ vCPU hotplug
(4) The ``query-hotpluggable-cpus`` command returns an object for CPUs
that are present (containing a "qom-path" member) or which may be
hot-plugged (no "qom-path" member). From its output in step (3), we
can see that ``IvyBridge-IBRS-x86_64-cpu`` is present in socket 0,
while hot-plugging a CPU into socket 1 requires passing the listed
can see that ``IvyBridge-IBRS-x86_64-cpu`` is present in socket 0 core 0,
while hot-plugging a CPU into socket 0 core 1 requires passing the listed
properties to QMP ``device_add``::
(QEMU) device_add id=cpu-2 driver=IvyBridge-IBRS-x86_64-cpu socket-id=1 core-id=0 thread-id=0
(QEMU) device_add id=cpu-2 driver=IvyBridge-IBRS-x86_64-cpu socket-id=0 core-id=1 thread-id=0
{
"execute": "device_add",
"arguments": {
"socket-id": 1,
"core-id": 1,
"driver": "IvyBridge-IBRS-x86_64-cpu",
"id": "cpu-2",
"core-id": 0,
"socket-id": 0,
"thread-id": 0
}
}
@@ -83,34 +83,32 @@ vCPU hotplug
(QEMU) query-cpus-fast
{
"execute": "query-cpus-fast",
"arguments": {}
"execute": "query-cpus-fast",
}
{
"return": [
{
"qom-path": "/machine/unattached/device[0]",
"target": "x86_64",
"thread-id": 11534,
"cpu-index": 0,
"props": {
"socket-id": 0,
"core-id": 0,
"socket-id": 0,
"thread-id": 0
},
"arch": "x86"
"qom-path": "/machine/unattached/device[0]",
"target": "x86_64",
"thread-id": 28957
},
{
"qom-path": "/machine/peripheral/cpu-2",
"target": "x86_64",
"thread-id": 12106,
"cpu-index": 1,
"props": {
"socket-id": 1,
"core-id": 0,
"core-id": 1,
"socket-id": 0,
"thread-id": 0
},
"arch": "x86"
"qom-path": "/machine/peripheral/cpu-2",
"target": "x86_64",
"thread-id": 29095
}
]
}
@@ -123,10 +121,10 @@ From the 'qmp-shell', invoke the QMP ``device_del`` command::
(QEMU) device_del id=cpu-2
{
"execute": "device_del",
"arguments": {
"id": "cpu-2"
}
"execute": "device_del",
}
{
"return": {}
docs/system/target-arm.rst
+5 -4
View File
@@ -63,10 +63,6 @@ large amounts of RAM. It also supports 64-bit CPUs.
Board-specific documentation
============================
Unfortunately many of the Arm boards QEMU supports are currently
undocumented; you can get a complete list by running
``qemu-system-aarch64 --machine help``.
..
This table of contents should be kept sorted alphabetically
by the title text of each file, which isn't the same ordering
@@ -90,11 +86,15 @@ undocumented; you can get a complete list by running
arm/digic
arm/cubieboard
arm/emcraft-sf2
arm/exynos
arm/fby35
arm/musicpal
arm/kzm
arm/nrf
arm/nuvoton
arm/imx25-pdk
arm/mcimx6ul-evk
arm/mcimx7d-sabre
arm/orangepi
arm/raspi
arm/collie
@@ -105,6 +105,7 @@ undocumented; you can get a complete list by running
arm/xenpvh
arm/xlnx-versal-virt
arm/xlnx-zynq
arm/xlnx-zcu102
Emulated CPU architecture support
=================================
hw/arm/virt.c
+44 -32
View File
@@ -2213,7 +2213,7 @@ static void machvirt_init(MachineState *machine)
exit(1);
}
if (vms->mte && (kvm_enabled() || hvf_enabled())) {
if (vms->mte && hvf_enabled()) {
error_report("mach-virt: %s does not support providing "
"MTE to the guest CPU",
current_accel_name());
@@ -2283,39 +2283,51 @@ static void machvirt_init(MachineState *machine)
}
if (vms->mte) {
/* Create the memory region only once, but link to all cpus. */
if (!tag_sysmem) {
/*
* The property exists only if MemTag is supported.
* If it is, we must allocate the ram to back that up.
*/
if (!object_property_find(cpuobj, "tag-memory")) {
error_report("MTE requested, but not supported "
"by the guest CPU");
if (tcg_enabled()) {
/* Create the memory region only once, but link to all cpus. */
if (!tag_sysmem) {
/*
* The property exists only if MemTag is supported.
* If it is, we must allocate the ram to back that up.
*/
if (!object_property_find(cpuobj, "tag-memory")) {
error_report("MTE requested, but not supported "
"by the guest CPU");
exit(1);
}
tag_sysmem = g_new(MemoryRegion, 1);
memory_region_init(tag_sysmem, OBJECT(machine),
"tag-memory", UINT64_MAX / 32);
if (vms->secure) {
secure_tag_sysmem = g_new(MemoryRegion, 1);
memory_region_init(secure_tag_sysmem, OBJECT(machine),
"secure-tag-memory",
UINT64_MAX / 32);
/* As with ram, secure-tag takes precedence over tag. */
memory_region_add_subregion_overlap(secure_tag_sysmem,
0, tag_sysmem, -1);
}
}
object_property_set_link(cpuobj, "tag-memory",
OBJECT(tag_sysmem), &error_abort);
if (vms->secure) {
object_property_set_link(cpuobj, "secure-tag-memory",
OBJECT(secure_tag_sysmem),
&error_abort);
}
} else if (kvm_enabled()) {
if (!kvm_arm_mte_supported()) {
error_report("MTE requested, but not supported by KVM");
exit(1);
}
tag_sysmem = g_new(MemoryRegion, 1);
memory_region_init(tag_sysmem, OBJECT(machine),
"tag-memory", UINT64_MAX / 32);
if (vms->secure) {
secure_tag_sysmem = g_new(MemoryRegion, 1);
memory_region_init(secure_tag_sysmem, OBJECT(machine),
"secure-tag-memory", UINT64_MAX / 32);
/* As with ram, secure-tag takes precedence over tag. */
memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
tag_sysmem, -1);
}
}
object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
&error_abort);
if (vms->secure) {
object_property_set_link(cpuobj, "secure-tag-memory",
OBJECT(secure_tag_sysmem),
&error_abort);
kvm_arm_enable_mte(cpuobj, &error_abort);
} else {
error_report("MTE requested, but not supported ");
exit(1);
}
}
hw/intc/arm_gic_kvm.c
+1 -8
View File
@@ -547,17 +547,10 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true,
&error_abort);
}
} else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) {
} else {
error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
error_append_hint(errp,
"Perhaps the host CPU does not support GICv2?\n");
} else if (ret != -ENODEV && ret != -ENOTSUP) {
/*
* Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that
* ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE",
* and that we will get a GICv2 via KVM_CREATE_IRQCHIP.
*/
error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
return;
}
hw/sd/omap_mmc.c
+16 -6
View File
@@ -103,6 +103,7 @@ static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
}
}
/* These must match the encoding of the MMC_CMD Response field */
typedef enum {
sd_nore = 0, /* no response */
sd_r1, /* normal response command */
@@ -112,8 +113,17 @@ typedef enum {
sd_r1b = -1,
} sd_rsp_type_t;
/* These must match the encoding of the MMC_CMD Type field */
typedef enum {
SD_TYPE_BC = 0, /* broadcast -- no response */
SD_TYPE_BCR = 1, /* broadcast with response */
SD_TYPE_AC = 2, /* addressed -- no data transfer */
SD_TYPE_ADTC = 3, /* addressed with data transfer */
} MMCCmdType;
static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
MMCCmdType type, int busy,
sd_rsp_type_t resptype, int init)
{
uint32_t rspstatus, mask;
int rsplen, timeout;
@@ -128,7 +138,7 @@ static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
if (resptype == sd_r1 && busy)
resptype = sd_r1b;
if (type == sd_adtc) {
if (type == SD_TYPE_ADTC) {
host->fifo_start = 0;
host->fifo_len = 0;
host->transfer = 1;
@@ -433,10 +443,10 @@ static void omap_mmc_write(void *opaque, hwaddr offset,
for (i = 0; i < 8; i ++)
s->rsp[i] = 0x0000;
omap_mmc_command(s, value & 63, (value >> 15) & 1,
(sd_cmd_type_t) ((value >> 12) & 3),
(value >> 11) & 1,
(sd_rsp_type_t) ((value >> 8) & 7),
(value >> 7) & 1);
(MMCCmdType)((value >> 12) & 3),
(value >> 11) & 1,
(sd_rsp_type_t) ((value >> 8) & 7),
(value >> 7) & 1);
omap_mmc_update(s);
break;
hw/sd/sd.c
+8
View File
@@ -71,6 +71,14 @@ typedef enum {
sd_illegal = -2,
} sd_rsp_type_t;
typedef enum {
sd_spi,
sd_bc, /* broadcast -- no response */
sd_bcr, /* broadcast with response */
sd_ac, /* addressed -- no data transfer */
sd_adtc, /* addressed with data transfer */
} sd_cmd_type_t;
enum SDCardModes {
sd_inactive,
sd_card_identification_mode,
include/hw/sd/sd.h
-8
View File
@@ -75,14 +75,6 @@ typedef enum {
UHS_III = 3, /* currently not supported */
} sd_uhs_mode_t;
typedef enum {
sd_spi,
sd_bc, /* broadcast -- no response */
sd_bcr, /* broadcast with response */
sd_ac, /* addressed -- no data transfer */
sd_adtc, /* addressed with data transfer */
} sd_cmd_type_t;
typedef struct {
uint8_t cmd;
uint32_t arg;
scripts/symlink-install-tree.py
+2 -1
View File
@@ -4,6 +4,7 @@ from pathlib import PurePath
import errno
import json
import os
import shlex
import subprocess
import sys
@@ -14,7 +15,7 @@ def destdir_join(d1: str, d2: str) -> str:
return str(PurePath(d1, *PurePath(d2).parts[1:]))
introspect = os.environ.get('MESONINTROSPECT')
out = subprocess.run([*introspect.split(' '), '--installed'],
out = subprocess.run([*shlex.split(introspect), '--installed'],
stdout=subprocess.PIPE, check=True).stdout
for source, dest in json.loads(out).items():
bundle_dest = destdir_join('qemu-bundle', dest)
target/arm/cpu.c
+11 -3
View File
@@ -2390,14 +2390,22 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
#ifndef CONFIG_USER_ONLY
/*
* If we do not have tag-memory provided by the machine,
* reduce MTE support to instructions enabled at EL0.
* If we run with TCG and do not have tag-memory provided by
* the machine, then reduce MTE support to instructions enabled at EL0.
* This matches Cortex-A710 BROADCASTMTE input being LOW.
*/
if (cpu->tag_memory == NULL) {
if (tcg_enabled() && cpu->tag_memory == NULL) {
cpu->isar.id_aa64pfr1 =
FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
}
/*
* If MTE is supported by the host, however it should not be
* enabled on the guest (i.e mte=off), clear guest's MTE bits."
*/
if (kvm_enabled() && !cpu->kvm_mte) {
FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
}
#endif
}
target/arm/cpu.h
+2
View File
@@ -922,6 +922,8 @@ struct ArchCPU {
/* CPU has memory protection unit */
bool has_mpu;
/* CPU has MTE enabled in KVM mode */
bool kvm_mte;
/* PMSAv7 MPU number of supported regions */
uint32_t pmsav7_dregion;
/* PMSAv8 MPU number of supported hyp regions */

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