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target/arm: Split out mmuidx.h from cpu.h
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20251008215613.300150-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
committed by
Peter Maydell
Peter Maydell
parent
e1e2f08b43
commit
e886dccc82
+1
-206
@@ -33,6 +33,7 @@
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#include "target/arm/multiprocessing.h"
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#include "target/arm/gtimer.h"
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#include "target/arm/cpu-sysregs.h"
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#include "target/arm/mmuidx.h"
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#define EXCP_UDEF 1 /* undefined instruction */
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#define EXCP_SWI 2 /* software interrupt */
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@@ -2301,212 +2302,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
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#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
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/* ARM has the following "translation regimes" (as the ARM ARM calls them):
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*
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* If EL3 is 64-bit:
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* + NonSecure EL1 & 0 stage 1
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* + NonSecure EL1 & 0 stage 2
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* + NonSecure EL2
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* + NonSecure EL2 & 0 (ARMv8.1-VHE)
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* + Secure EL1 & 0 stage 1
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* + Secure EL1 & 0 stage 2 (FEAT_SEL2)
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* + Secure EL2 (FEAT_SEL2)
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* + Secure EL2 & 0 (FEAT_SEL2)
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* + Realm EL1 & 0 stage 1 (FEAT_RME)
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* + Realm EL1 & 0 stage 2 (FEAT_RME)
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* + Realm EL2 (FEAT_RME)
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* + EL3
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* If EL3 is 32-bit:
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* + NonSecure PL1 & 0 stage 1
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* + NonSecure PL1 & 0 stage 2
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* + NonSecure PL2
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* + Secure PL1 & 0
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* (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
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*
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* For QEMU, an mmu_idx is not quite the same as a translation regime because:
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* 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
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* because they may differ in access permissions even if the VA->PA map is
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* the same
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* 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
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* translation, which means that we have one mmu_idx that deals with two
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* concatenated translation regimes [this sort of combined s1+2 TLB is
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* architecturally permitted]
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* 3. we don't need to allocate an mmu_idx to translations that we won't be
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* handling via the TLB. The only way to do a stage 1 translation without
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* the immediate stage 2 translation is via the ATS or AT system insns,
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* which can be slow-pathed and always do a page table walk.
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* The only use of stage 2 translations is either as part of an s1+2
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* lookup or when loading the descriptors during a stage 1 page table walk,
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* and in both those cases we don't use the TLB.
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* 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
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* translation regimes, because they map reasonably well to each other
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* and they can't both be active at the same time.
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* 5. we want to be able to use the TLB for accesses done as part of a
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* stage1 page table walk, rather than having to walk the stage2 page
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* table over and over.
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* 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
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* Never (PAN) bit within PSTATE.
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* 7. we fold together most secure and non-secure regimes for A-profile,
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* because there are no banked system registers for aarch64, so the
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* process of switching between secure and non-secure is
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* already heavyweight.
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* 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure,
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* because both are in use simultaneously for Secure EL2.
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*
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* This gives us the following list of cases:
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*
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* EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2)
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* EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2)
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* EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN)
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* EL0 EL2&0
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* EL2 EL2&0
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* EL2 EL2&0 +PAN
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* EL2 (aka NS PL2)
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* EL3 (aka AArch32 S PL1 PL1&0)
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* AArch32 S PL0 PL1&0 (we call this EL30_0)
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* AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN)
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* Stage2 Secure
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* Stage2 NonSecure
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* plus one TLB per Physical address space: S, NS, Realm, Root
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*
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* for a total of 16 different mmu_idx.
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*
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* R profile CPUs have an MPU, but can use the same set of MMU indexes
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* as A profile. They only need to distinguish EL0 and EL1 (and
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* EL2 for cores like the Cortex-R52).
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*
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* M profile CPUs are rather different as they do not have a true MMU.
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* They have the following different MMU indexes:
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* User
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* Privileged
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* User, execution priority negative (ie the MPU HFNMIENA bit may apply)
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* Privileged, execution priority negative (ditto)
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* If the CPU supports the v8M Security Extension then there are also:
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* Secure User
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* Secure Privileged
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* Secure User, execution priority negative
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* Secure Privileged, execution priority negative
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*
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* The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
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* are not quite the same -- different CPU types (most notably M profile
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* vs A/R profile) would like to use MMU indexes with different semantics,
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* but since we don't ever need to use all of those in a single CPU we
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* can avoid having to set NB_MMU_MODES to "total number of A profile MMU
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* modes + total number of M profile MMU modes". The lower bits of
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* ARMMMUIdx are the core TLB mmu index, and the higher bits are always
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* the same for any particular CPU.
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* Variables of type ARMMUIdx are always full values, and the core
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* index values are in variables of type 'int'.
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*
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* Our enumeration includes at the end some entries which are not "true"
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* mmu_idx values in that they don't have corresponding TLBs and are only
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* valid for doing slow path page table walks.
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*
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* The constant names here are patterned after the general style of the names
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* of the AT/ATS operations.
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* The values used are carefully arranged to make mmu_idx => EL lookup easy.
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* For M profile we arrange them to have a bit for priv, a bit for negpri
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* and a bit for secure.
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*/
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#define ARM_MMU_IDX_A 0x10 /* A profile */
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#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
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#define ARM_MMU_IDX_M 0x40 /* M profile */
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/* Meanings of the bits for M profile mmu idx values */
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#define ARM_MMU_IDX_M_PRIV 0x1
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#define ARM_MMU_IDX_M_NEGPRI 0x2
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#define ARM_MMU_IDX_M_S 0x4 /* Secure */
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#define ARM_MMU_IDX_TYPE_MASK \
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(ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
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#define ARM_MMU_IDX_COREIDX_MASK 0xf
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typedef enum ARMMMUIdx {
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/*
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* A-profile.
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*/
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ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
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ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
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ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
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ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A,
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ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
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ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
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ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
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ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
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ARMMMUIdx_E30_0 = 8 | ARM_MMU_IDX_A,
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ARMMMUIdx_E30_3_PAN = 9 | ARM_MMU_IDX_A,
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/*
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* Used for second stage of an S12 page table walk, or for descriptor
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* loads during first stage of an S1 page table walk. Note that both
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* are in use simultaneously for SecureEL2: the security state for
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* the S2 ptw is selected by the NS bit from the S1 ptw.
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*/
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ARMMMUIdx_Stage2_S = 10 | ARM_MMU_IDX_A,
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ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A,
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/* TLBs with 1-1 mapping to the physical address spaces. */
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ARMMMUIdx_Phys_S = 12 | ARM_MMU_IDX_A,
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ARMMMUIdx_Phys_NS = 13 | ARM_MMU_IDX_A,
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ARMMMUIdx_Phys_Root = 14 | ARM_MMU_IDX_A,
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ARMMMUIdx_Phys_Realm = 15 | ARM_MMU_IDX_A,
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/*
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* These are not allocated TLBs and are used only for AT system
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* instructions or for the first stage of an S12 page table walk.
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*/
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ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
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ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
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ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
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/*
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* M-profile.
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*/
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ARMMMUIdx_MUser = ARM_MMU_IDX_M,
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ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
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ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
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ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
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ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
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ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
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ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
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ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
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} ARMMMUIdx;
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/*
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* Bit macros for the core-mmu-index values for each index,
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* for use when calling tlb_flush_by_mmuidx() and friends.
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*/
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#define TO_CORE_BIT(NAME) \
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ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
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typedef enum ARMMMUIdxBit {
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TO_CORE_BIT(E10_0),
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TO_CORE_BIT(E20_0),
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TO_CORE_BIT(E10_1),
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TO_CORE_BIT(E10_1_PAN),
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TO_CORE_BIT(E2),
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TO_CORE_BIT(E20_2),
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TO_CORE_BIT(E20_2_PAN),
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TO_CORE_BIT(E3),
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TO_CORE_BIT(E30_0),
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TO_CORE_BIT(E30_3_PAN),
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TO_CORE_BIT(Stage2),
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TO_CORE_BIT(Stage2_S),
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TO_CORE_BIT(MUser),
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TO_CORE_BIT(MPriv),
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TO_CORE_BIT(MUserNegPri),
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TO_CORE_BIT(MPrivNegPri),
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TO_CORE_BIT(MSUser),
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TO_CORE_BIT(MSPriv),
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TO_CORE_BIT(MSUserNegPri),
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TO_CORE_BIT(MSPrivNegPri),
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} ARMMMUIdxBit;
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#undef TO_CORE_BIT
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#define MMU_USER_IDX 0
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/* Indexes used when registering address spaces with cpu_address_space_init */
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typedef enum ARMASIdx {
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ARMASIdx_NS = 0,
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@@ -0,0 +1,216 @@
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/*
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* QEMU Arm software mmu index definitions
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef TARGET_ARM_MMUIDX_H
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#define TARGET_ARM_MMUIDX_H
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/*
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* Arm has the following "translation regimes" (as the Arm ARM calls them):
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*
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* If EL3 is 64-bit:
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* + NonSecure EL1 & 0 stage 1
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* + NonSecure EL1 & 0 stage 2
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* + NonSecure EL2
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* + NonSecure EL2 & 0 (ARMv8.1-VHE)
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* + Secure EL1 & 0 stage 1
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* + Secure EL1 & 0 stage 2 (FEAT_SEL2)
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* + Secure EL2 (FEAT_SEL2)
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* + Secure EL2 & 0 (FEAT_SEL2)
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* + Realm EL1 & 0 stage 1 (FEAT_RME)
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* + Realm EL1 & 0 stage 2 (FEAT_RME)
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* + Realm EL2 (FEAT_RME)
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* + EL3
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* If EL3 is 32-bit:
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* + NonSecure PL1 & 0 stage 1
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* + NonSecure PL1 & 0 stage 2
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* + NonSecure PL2
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* + Secure PL1 & 0
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* (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
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*
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* For QEMU, an mmu_idx is not quite the same as a translation regime because:
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* 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
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* because they may differ in access permissions even if the VA->PA map is
|
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* the same
|
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* 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
|
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* translation, which means that we have one mmu_idx that deals with two
|
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* concatenated translation regimes [this sort of combined s1+2 TLB is
|
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* architecturally permitted]
|
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* 3. we don't need to allocate an mmu_idx to translations that we won't be
|
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* handling via the TLB. The only way to do a stage 1 translation without
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* the immediate stage 2 translation is via the ATS or AT system insns,
|
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* which can be slow-pathed and always do a page table walk.
|
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* The only use of stage 2 translations is either as part of an s1+2
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* lookup or when loading the descriptors during a stage 1 page table walk,
|
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* and in both those cases we don't use the TLB.
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* 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
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* translation regimes, because they map reasonably well to each other
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* and they can't both be active at the same time.
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* 5. we want to be able to use the TLB for accesses done as part of a
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* stage1 page table walk, rather than having to walk the stage2 page
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* table over and over.
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* 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
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* Never (PAN) bit within PSTATE.
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* 7. we fold together most secure and non-secure regimes for A-profile,
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* because there are no banked system registers for aarch64, so the
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* process of switching between secure and non-secure is
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* already heavyweight.
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* 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure,
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* because both are in use simultaneously for Secure EL2.
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*
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* This gives us the following list of cases:
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*
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* EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2)
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* EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2)
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* EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN)
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* EL0 EL2&0
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* EL2 EL2&0
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* EL2 EL2&0 +PAN
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* EL2 (aka NS PL2)
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* EL3 (aka AArch32 S PL1 PL1&0)
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* AArch32 S PL0 PL1&0 (we call this EL30_0)
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* AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN)
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* Stage2 Secure
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* Stage2 NonSecure
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* plus one TLB per Physical address space: S, NS, Realm, Root
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*
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* for a total of 16 different mmu_idx.
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*
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* R profile CPUs have an MPU, but can use the same set of MMU indexes
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* as A profile. They only need to distinguish EL0 and EL1 (and
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* EL2 for cores like the Cortex-R52).
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*
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* M profile CPUs are rather different as they do not have a true MMU.
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* They have the following different MMU indexes:
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* User
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* Privileged
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* User, execution priority negative (ie the MPU HFNMIENA bit may apply)
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* Privileged, execution priority negative (ditto)
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* If the CPU supports the v8M Security Extension then there are also:
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* Secure User
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* Secure Privileged
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* Secure User, execution priority negative
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* Secure Privileged, execution priority negative
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*
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* The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
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* are not quite the same -- different CPU types (most notably M profile
|
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* vs A/R profile) would like to use MMU indexes with different semantics,
|
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* but since we don't ever need to use all of those in a single CPU we
|
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* can avoid having to set NB_MMU_MODES to "total number of A profile MMU
|
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* modes + total number of M profile MMU modes". The lower bits of
|
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* ARMMMUIdx are the core TLB mmu index, and the higher bits are always
|
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* the same for any particular CPU.
|
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* Variables of type ARMMUIdx are always full values, and the core
|
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* index values are in variables of type 'int'.
|
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*
|
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* Our enumeration includes at the end some entries which are not "true"
|
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* mmu_idx values in that they don't have corresponding TLBs and are only
|
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* valid for doing slow path page table walks.
|
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*
|
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* The constant names here are patterned after the general style of the names
|
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* of the AT/ATS operations.
|
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* The values used are carefully arranged to make mmu_idx => EL lookup easy.
|
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* For M profile we arrange them to have a bit for priv, a bit for negpri
|
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* and a bit for secure.
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*/
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#define ARM_MMU_IDX_A 0x10 /* A profile */
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#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
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#define ARM_MMU_IDX_M 0x40 /* M profile */
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/* Meanings of the bits for M profile mmu idx values */
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#define ARM_MMU_IDX_M_PRIV 0x1
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#define ARM_MMU_IDX_M_NEGPRI 0x2
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#define ARM_MMU_IDX_M_S 0x4 /* Secure */
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#define ARM_MMU_IDX_TYPE_MASK \
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(ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
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#define ARM_MMU_IDX_COREIDX_MASK 0xf
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typedef enum ARMMMUIdx {
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/*
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* A-profile.
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*/
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ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
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ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
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ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
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ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A,
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ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
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ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
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ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
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ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
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ARMMMUIdx_E30_0 = 8 | ARM_MMU_IDX_A,
|
||||
ARMMMUIdx_E30_3_PAN = 9 | ARM_MMU_IDX_A,
|
||||
|
||||
/*
|
||||
* Used for second stage of an S12 page table walk, or for descriptor
|
||||
* loads during first stage of an S1 page table walk. Note that both
|
||||
* are in use simultaneously for SecureEL2: the security state for
|
||||
* the S2 ptw is selected by the NS bit from the S1 ptw.
|
||||
*/
|
||||
ARMMMUIdx_Stage2_S = 10 | ARM_MMU_IDX_A,
|
||||
ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A,
|
||||
|
||||
/* TLBs with 1-1 mapping to the physical address spaces. */
|
||||
ARMMMUIdx_Phys_S = 12 | ARM_MMU_IDX_A,
|
||||
ARMMMUIdx_Phys_NS = 13 | ARM_MMU_IDX_A,
|
||||
ARMMMUIdx_Phys_Root = 14 | ARM_MMU_IDX_A,
|
||||
ARMMMUIdx_Phys_Realm = 15 | ARM_MMU_IDX_A,
|
||||
|
||||
/*
|
||||
* These are not allocated TLBs and are used only for AT system
|
||||
* instructions or for the first stage of an S12 page table walk.
|
||||
*/
|
||||
ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
|
||||
ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
|
||||
ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
|
||||
|
||||
/*
|
||||
* M-profile.
|
||||
*/
|
||||
ARMMMUIdx_MUser = ARM_MMU_IDX_M,
|
||||
ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
|
||||
ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
|
||||
ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
|
||||
ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
|
||||
ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
|
||||
ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
|
||||
ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
|
||||
} ARMMMUIdx;
|
||||
|
||||
/*
|
||||
* Bit macros for the core-mmu-index values for each index,
|
||||
* for use when calling tlb_flush_by_mmuidx() and friends.
|
||||
*/
|
||||
#define TO_CORE_BIT(NAME) \
|
||||
ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
|
||||
|
||||
typedef enum ARMMMUIdxBit {
|
||||
TO_CORE_BIT(E10_0),
|
||||
TO_CORE_BIT(E20_0),
|
||||
TO_CORE_BIT(E10_1),
|
||||
TO_CORE_BIT(E10_1_PAN),
|
||||
TO_CORE_BIT(E2),
|
||||
TO_CORE_BIT(E20_2),
|
||||
TO_CORE_BIT(E20_2_PAN),
|
||||
TO_CORE_BIT(E3),
|
||||
TO_CORE_BIT(E30_0),
|
||||
TO_CORE_BIT(E30_3_PAN),
|
||||
TO_CORE_BIT(Stage2),
|
||||
TO_CORE_BIT(Stage2_S),
|
||||
|
||||
TO_CORE_BIT(MUser),
|
||||
TO_CORE_BIT(MPriv),
|
||||
TO_CORE_BIT(MUserNegPri),
|
||||
TO_CORE_BIT(MPrivNegPri),
|
||||
TO_CORE_BIT(MSUser),
|
||||
TO_CORE_BIT(MSPriv),
|
||||
TO_CORE_BIT(MSUserNegPri),
|
||||
TO_CORE_BIT(MSPrivNegPri),
|
||||
} ARMMMUIdxBit;
|
||||
|
||||
#undef TO_CORE_BIT
|
||||
|
||||
#define MMU_USER_IDX 0
|
||||
|
||||
#endif /* TARGET_ARM_MMUIDX_H */
|
||||
Reference in New Issue
Block a user