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Merge tag 's390x-tcg-2019-05-17-2' into s390-next-staging
Implement all Vector Integer Instructions introduced with the "Vector Facility" for s390x TCG. # gpg: Signature made Fri 17 May 2019 01:37:40 PM CEST # gpg: using RSA key 4DDE10F700FF835A # gpg: Good signature from "David Hildenbrand <david@redhat.com>" [full] # gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full] * tag 's390x-tcg-2019-05-17-2': (40 commits) s390x/tcg: Implement VECTOR TEST UNDER MASK s390x/tcg: Implement VECTOR SUM ACROSS WORD s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE) s390x/tcg: Implement VECTOR ELEMENT SHIFT s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL s390x/tcg: Implement VECTOR POPULATION COUNT s390x/tcg: Implement VECTOR OR WITH COMPLEMENT s390x/tcg: Implement VECTOR OR s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR s390x/tcg: Implement VECTOR NOR ... Signed-off-by: Cornelia Huck <cohuck@redhat.com>
This commit is contained in:
Cornelia Huck
@@ -1,7 +1,7 @@
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obj-y += cpu.o cpu_models.o cpu_features.o gdbstub.o interrupt.o helper.o
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obj-$(CONFIG_TCG) += translate.o cc_helper.o excp_helper.o fpu_helper.o
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obj-$(CONFIG_TCG) += int_helper.o mem_helper.o misc_helper.o crypto_helper.o
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obj-$(CONFIG_TCG) += vec_helper.o
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obj-$(CONFIG_TCG) += vec_helper.o vec_int_helper.o
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obj-$(CONFIG_SOFTMMU) += machine.o ioinst.o arch_dump.o mmu_helper.o diag.o
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obj-$(CONFIG_SOFTMMU) += sigp.o
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obj-$(CONFIG_KVM) += kvm.o
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@@ -402,6 +402,20 @@ static uint32_t cc_calc_lcbb(uint64_t dst)
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return dst == 16 ? 0 : 3;
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}
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static uint32_t cc_calc_vc(uint64_t low, uint64_t high)
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{
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if (high == -1ull && low == -1ull) {
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/* all elements match */
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return 0;
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} else if (high == 0 && low == 0) {
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/* no elements match */
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return 3;
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} else {
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/* some elements but not all match */
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return 1;
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}
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}
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static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
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uint64_t src, uint64_t dst, uint64_t vr)
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{
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@@ -514,6 +528,9 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
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case CC_OP_LCBB:
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r = cc_calc_lcbb(dst);
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break;
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case CC_OP_VC:
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r = cc_calc_vc(src, dst);
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break;
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case CC_OP_NZ_F32:
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r = set_cc_nz_f32(dst);
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@@ -418,6 +418,7 @@ const char *cc_name(enum cc_op cc_op)
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[CC_OP_SLA_64] = "CC_OP_SLA_64",
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[CC_OP_FLOGR] = "CC_OP_FLOGR",
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[CC_OP_LCBB] = "CC_OP_LCBB",
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[CC_OP_VC] = "CC_OP_VC",
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};
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return cc_names[cc_op];
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@@ -145,6 +145,72 @@ DEF_HELPER_5(gvec_vpkls_cc64, void, ptr, cptr, cptr, env, i32)
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DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(vstl, TCG_CALL_NO_WG, void, env, cptr, i64, i64)
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/* === Vector Integer Instructions === */
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DEF_HELPER_FLAGS_4(gvec_vavg8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vavg16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vavgl8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vavgl16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_3(gvec_vclz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
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DEF_HELPER_FLAGS_3(gvec_vclz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
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DEF_HELPER_FLAGS_3(gvec_vctz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
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DEF_HELPER_FLAGS_3(gvec_vctz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vgfm8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vgfm16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vgfm32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vgfm64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vgfma8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vgfma16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vgfma32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vgfma64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmal8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmal16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmah8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmah16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmalh8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmalh16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmae8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmae16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmae32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmale8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmale16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmale32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmao8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmao16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmao32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmalo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmalo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_5(gvec_vmalo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmh8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmh16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmlh8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmlh16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vme8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vme16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vme32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmle8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmle16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmle32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmlo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
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DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_vscbi8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vscbi16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_4(gvec_vtm, void, ptr, cptr, env, i32)
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#ifndef CONFIG_USER_ONLY
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DEF_HELPER_3(servc, i32, env, i64, i64)
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DEF_HELPER_4(diag, void, env, i32, i32, i32)
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@@ -1054,6 +1054,143 @@
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/* VECTOR UNPACK LOGICAL LOW */
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F(0xe7d4, VUPLL, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
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/* === Vector Integer Instructions === */
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/* VECTOR ADD */
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F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC)
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/* VECTOR ADD COMPUTE CARRY */
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F(0xe7f1, VACC, VRR_c, V, 0, 0, 0, 0, vacc, 0, IF_VEC)
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/* VECTOR ADD WITH CARRY */
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F(0xe7bb, VAC, VRR_d, V, 0, 0, 0, 0, vac, 0, IF_VEC)
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/* VECTOR ADD WITH CARRY COMPUTE CARRY */
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F(0xe7b9, VACCC, VRR_d, V, 0, 0, 0, 0, vaccc, 0, IF_VEC)
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/* VECTOR AND */
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F(0xe768, VN, VRR_c, V, 0, 0, 0, 0, vn, 0, IF_VEC)
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/* VECTOR AND WITH COMPLEMENT */
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F(0xe769, VNC, VRR_c, V, 0, 0, 0, 0, vnc, 0, IF_VEC)
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/* VECTOR AVERAGE */
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F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC)
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/* VECTOR AVERAGE LOGICAL */
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F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC)
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/* VECTOR CHECKSUM */
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F(0xe766, VCKSM, VRR_c, V, 0, 0, 0, 0, vcksm, 0, IF_VEC)
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/* VECTOR ELEMENT COMPARE */
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F(0xe7db, VEC, VRR_a, V, 0, 0, 0, 0, vec, cmps64, IF_VEC)
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/* VECTOR ELEMENT COMPARE LOGICAL */
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F(0xe7d9, VECL, VRR_a, V, 0, 0, 0, 0, vec, cmpu64, IF_VEC)
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/* VECTOR COMPARE EQUAL */
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E(0xe7f8, VCEQ, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_EQ, IF_VEC)
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/* VECTOR COMPARE HIGH */
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E(0xe7fb, VCH, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GT, IF_VEC)
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/* VECTOR COMPARE HIGH LOGICAL */
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E(0xe7f9, VCHL, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GTU, IF_VEC)
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/* VECTOR COUNT LEADING ZEROS */
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F(0xe753, VCLZ, VRR_a, V, 0, 0, 0, 0, vclz, 0, IF_VEC)
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/* VECTOR COUNT TRAILING ZEROS */
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F(0xe752, VCTZ, VRR_a, V, 0, 0, 0, 0, vctz, 0, IF_VEC)
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/* VECTOR EXCLUSIVE OR */
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F(0xe76d, VX, VRR_c, V, 0, 0, 0, 0, vx, 0, IF_VEC)
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/* VECTOR GALOIS FIELD MULTIPLY SUM */
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F(0xe7b4, VGFM, VRR_c, V, 0, 0, 0, 0, vgfm, 0, IF_VEC)
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/* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */
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F(0xe7bc, VGFMA, VRR_d, V, 0, 0, 0, 0, vgfma, 0, IF_VEC)
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/* VECTOR LOAD COMPLEMENT */
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F(0xe7de, VLC, VRR_a, V, 0, 0, 0, 0, vlc, 0, IF_VEC)
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/* VECTOR LOAD POSITIVE */
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F(0xe7df, VLP, VRR_a, V, 0, 0, 0, 0, vlp, 0, IF_VEC)
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/* VECTOR MAXIMUM */
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F(0xe7ff, VMX, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
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/* VECTOR MAXIMUM LOGICAL */
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F(0xe7fd, VMXL, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
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/* VECTOR MINIMUM */
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F(0xe7fe, VMN, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
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/* VECTOR MINIMUM LOGICAL */
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F(0xe7fc, VMNL, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
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/* VECTOR MULTIPLY AND ADD LOW */
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F(0xe7aa, VMAL, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
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/* VECTOR MULTIPLY AND ADD HIGH */
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F(0xe7ab, VMAH, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
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/* VECTOR MULTIPLY AND ADD LOGICAL HIGH */
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F(0xe7a9, VMALH, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
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/* VECTOR MULTIPLY AND ADD EVEN */
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F(0xe7ae, VMAE, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
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/* VECTOR MULTIPLY AND ADD LOGICAL EVEN */
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F(0xe7ac, VMALE, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
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/* VECTOR MULTIPLY AND ADD ODD */
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F(0xe7af, VMAO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
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/* VECTOR MULTIPLY AND ADD LOGICAL ODD */
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F(0xe7ad, VMALO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
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/* VECTOR MULTIPLY HIGH */
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F(0xe7a3, VMH, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
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/* VECTOR MULTIPLY LOGICAL HIGH */
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F(0xe7a1, VMLH, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
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/* VECTOR MULTIPLY LOW */
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F(0xe7a2, VML, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
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/* VECTOR MULTIPLY EVEN */
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F(0xe7a6, VME, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
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/* VECTOR MULTIPLY LOGICAL EVEN */
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F(0xe7a4, VMLE, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
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/* VECTOR MULTIPLY ODD */
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F(0xe7a7, VMO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
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/* VECTOR MULTIPLY LOGICAL ODD */
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F(0xe7a5, VMLO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
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/* VECTOR NAND */
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F(0xe76e, VNN, VRR_c, VE, 0, 0, 0, 0, vnn, 0, IF_VEC)
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/* VECTOR NOR */
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F(0xe76b, VNO, VRR_c, V, 0, 0, 0, 0, vno, 0, IF_VEC)
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/* VECTOR NOT EXCLUSIVE OR */
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F(0xe76c, VNX, VRR_c, VE, 0, 0, 0, 0, vnx, 0, IF_VEC)
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/* VECTOR OR */
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F(0xe76a, VO, VRR_c, V, 0, 0, 0, 0, vo, 0, IF_VEC)
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/* VECTOR OR WITH COMPLEMENT */
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F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC)
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/* VECTOR POPULATION COUNT */
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F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC)
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/* VECTOR ELEMENT ROTATE LEFT LOGICAL */
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F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC)
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F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
|
||||
/* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
|
||||
F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC)
|
||||
/* VECTOR ELEMENT SHIFT LEFT */
|
||||
F(0xe770, VESLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
|
||||
F(0xe730, VESL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
|
||||
/* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */
|
||||
F(0xe77a, VESRAV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
|
||||
F(0xe73a, VESRA, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
|
||||
/* VECTOR ELEMENT SHIFT RIGHT LOGICAL */
|
||||
F(0xe778, VESRLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
|
||||
F(0xe738, VESRL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
|
||||
/* VECTOR SHIFT LEFT */
|
||||
F(0xe774, VSL, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
|
||||
/* VECTOR SHIFT LEFT BY BYTE */
|
||||
F(0xe775, VSLB, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
|
||||
/* VECTOR SHIFT LEFT DOUBLE BY BYTE */
|
||||
F(0xe777, VSLDB, VRI_d, V, 0, 0, 0, 0, vsldb, 0, IF_VEC)
|
||||
/* VECTOR SHIFT RIGHT ARITHMETIC */
|
||||
F(0xe77e, VSRA, VRR_c, V, 0, 0, 0, 0, vsra, 0, IF_VEC)
|
||||
/* VECTOR SHIFT RIGHT ARITHMETIC BY BYTE */
|
||||
F(0xe77f, VSRAB, VRR_c, V, 0, 0, 0, 0, vsra, 0, IF_VEC)
|
||||
/* VECTOR SHIFT RIGHT LOGICAL */
|
||||
F(0xe77c, VSRL, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
|
||||
/* VECTOR SHIFT RIGHT LOGICAL BY BYTE */
|
||||
F(0xe77d, VSRLB, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
|
||||
/* VECTOR SUBTRACT */
|
||||
F(0xe7f7, VS, VRR_c, V, 0, 0, 0, 0, vs, 0, IF_VEC)
|
||||
/* VECTOR SUBTRACT COMPUTE BORROW INDICATION */
|
||||
F(0xe7f5, VSCBI, VRR_c, V, 0, 0, 0, 0, vscbi, 0, IF_VEC)
|
||||
/* VECTOR SUBTRACT WITH BORROW INDICATION */
|
||||
F(0xe7bf, VSBI, VRR_d, V, 0, 0, 0, 0, vsbi, 0, IF_VEC)
|
||||
/* VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION */
|
||||
F(0xe7bd, VSBCBI, VRR_d, V, 0, 0, 0, 0, vsbcbi, 0, IF_VEC)
|
||||
/* VECTOR SUM ACROSS DOUBLEWORD */
|
||||
F(0xe765, VSUMG, VRR_c, V, 0, 0, 0, 0, vsumg, 0, IF_VEC)
|
||||
/* VECTOR SUM ACROSS QUADWORD */
|
||||
F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
|
||||
/* VECTOR SUM ACROSS WORD */
|
||||
F(0xe764, VSUM, VRR_c, V, 0, 0, 0, 0, vsum, 0, IF_VEC)
|
||||
/* VECTOR TEST UNDER MASK */
|
||||
F(0xe7d8, VTM, VRR_a, V, 0, 0, 0, 0, vtm, 0, IF_VEC)
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
/* COMPARE AND SWAP AND PURGE */
|
||||
E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV)
|
||||
|
||||
@@ -200,6 +200,7 @@ enum cc_op {
|
||||
CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
|
||||
CC_OP_FLOGR, /* find leftmost one */
|
||||
CC_OP_LCBB, /* load count to block boundary */
|
||||
CC_OP_VC, /* vector compare result */
|
||||
CC_OP_MAX
|
||||
};
|
||||
|
||||
|
||||
@@ -572,6 +572,7 @@ static void gen_op_calc_cc(DisasContext *s)
|
||||
case CC_OP_SLA_32:
|
||||
case CC_OP_SLA_64:
|
||||
case CC_OP_NZ_F128:
|
||||
case CC_OP_VC:
|
||||
/* 2 arguments */
|
||||
gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
|
||||
break;
|
||||
@@ -6092,6 +6093,7 @@ enum DisasInsnEnum {
|
||||
#define FAC_PCI S390_FEAT_ZPCI /* z/PCI facility */
|
||||
#define FAC_AIS S390_FEAT_ADAPTER_INT_SUPPRESSION
|
||||
#define FAC_V S390_FEAT_VECTOR /* vector facility */
|
||||
#define FAC_VE S390_FEAT_VECTOR_ENH /* vector enhancements facility 1 */
|
||||
|
||||
static const DisasInsn insn_info[] = {
|
||||
#include "insn-data.def"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user