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Merge remote-tracking branch 'kraxel/pixman.v8' into staging

Browse Source 
# By Gerd Hoffmann (18) and others
# Via Blue Swirl (1) and Gerd Hoffmann (1)
* kraxel/pixman.v8: (37 commits)
  console: remove ds_get_* helper functions
  console: zap color_table
  console: stop using DisplayState in gfx hardware emulation
  console: zap displaystate from dcl callbacks
  cocoa: stop using DisplayState
  spice: stop using DisplayState
  sdl: stop using DisplayState
  vnc: stop using DisplayState
  gtk: stop using DisplayState
  console: add surface_*() getters
  console: rework DisplaySurface handling [dcl/ui side]
  console: rework DisplaySurface handling [vga emu side]
  sdl: drop dead code
  qxl: better vga init in enter_vga_mode
  qxl: zap qxl0 global
  spice: zap sdpy global
  console: kill DisplayState->opaque
  console: fix displaychangelisteners interface
  s390: Fix cpu refactoring fallout.
  target-mips: fix rndrashift_short_acc and code for EXTR_ instructions
  ...
This commit is contained in:
Anthony Liguori
2013-03-18 07:34:24 -05:00
parent b1999e87b4 1562e53112
commit e531761d63
62 changed files with 3546 additions and 1238 deletions
Download Patch File Download Diff File Expand all files Collapse all files
default-configs/arm-softmmu.mak
+1
View File
@@ -42,6 +42,7 @@ CONFIG_PL110=y
CONFIG_PL181=y
CONFIG_PL190=y
CONFIG_PL310=y
CONFIG_PL330=y
CONFIG_CADENCE=y
CONFIG_XGMAC=y
hw/Makefile.objs
+1
View File
@@ -98,6 +98,7 @@ common-obj-$(CONFIG_PL110) += pl110.o
common-obj-$(CONFIG_PL181) += pl181.o
common-obj-$(CONFIG_PL190) += pl190.o
common-obj-$(CONFIG_PL310) += arm_l2x0.o
common-obj-$(CONFIG_PL330) += pl330.o
common-obj-$(CONFIG_VERSATILE_PCI) += versatile_pci.o
common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
common-obj-$(CONFIG_CADENCE) += cadence_uart.o
hw/arm/musicpal.c
+11 -9
View File
@@ -462,7 +462,7 @@ typedef struct musicpal_lcd_state {
uint32_t irqctrl;
uint32_t page;
uint32_t page_off;
DisplayState *ds;
QemuConsole *con;
uint8_t video_ram[128*64/8];
} musicpal_lcd_state;
@@ -483,7 +483,8 @@ static inline void glue(set_lcd_pixel, depth) \
(musicpal_lcd_state *s, int x, int y, type col) \
{ \
int dx, dy; \
type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
DisplaySurface *surface = qemu_console_surface(s->con); \
type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \
\
for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
for (dx = 0; dx < 3; dx++, pixel++) \
@@ -496,9 +497,10 @@ SET_LCD_PIXEL(32, uint32_t)
static void lcd_refresh(void *opaque)
{
musicpal_lcd_state *s = opaque;
DisplaySurface *surface = qemu_console_surface(s->con);
int x, y, col;
switch (ds_get_bits_per_pixel(s->ds)) {
switch (surface_bits_per_pixel(surface)) {
case 0:
return;
#define LCD_REFRESH(depth, func) \
@@ -518,14 +520,14 @@ static void lcd_refresh(void *opaque)
break;
LCD_REFRESH(8, rgb_to_pixel8)
LCD_REFRESH(16, rgb_to_pixel16)
LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
LCD_REFRESH(32, (is_surface_bgr(surface) ?
rgb_to_pixel32bgr : rgb_to_pixel32))
default:
hw_error("unsupported colour depth %i\n",
ds_get_bits_per_pixel(s->ds));
surface_bits_per_pixel(surface));
}
dpy_gfx_update(s->ds, 0, 0, 128*3, 64*3);
dpy_gfx_update(s->con, 0, 0, 128*3, 64*3);
}
static void lcd_invalidate(void *opaque)
@@ -609,9 +611,9 @@ static int musicpal_lcd_init(SysBusDevice *dev)
"musicpal-lcd", MP_LCD_SIZE);
sysbus_init_mmio(dev, &s->iomem);
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
NULL, NULL, s);
qemu_console_resize(s->ds, 128*3, 64*3);
s->con = graphic_console_init(lcd_refresh, lcd_invalidate,
NULL, NULL, s);
qemu_console_resize(s->con, 128*3, 64*3);
qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
hw/arm/nseries.c
-7
View File
@@ -1290,7 +1290,6 @@ static void n8x0_init(QEMUMachineInitArgs *args,
MemoryRegion *sysmem = get_system_memory();
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
int sdram_size = binfo->ram_size;
DisplayState *ds;
s->mpu = omap2420_mpu_init(sysmem, sdram_size, args->cpu_model);
@@ -1370,12 +1369,6 @@ static void n8x0_init(QEMUMachineInitArgs *args,
n800_setup_nolo_tags(nolo_tags);
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
}
/* FIXME: We shouldn't really be doing this here. The LCD controller
will set the size once configured, so this just sets an initial
size until the guest activates the display. */
ds = get_displaystate();
ds->surface = qemu_resize_displaysurface(ds, 800, 480);
dpy_gfx_resize(ds);
}
static struct arm_boot_info n800_binfo = {
hw/arm/palm.c
-7
View File
@@ -205,7 +205,6 @@ static void palmte_init(QEMUMachineInitArgs *args)
static uint32_t cs2val = 0x0000e1a0;
static uint32_t cs3val = 0xe1a0e1a0;
int rom_size, rom_loaded = 0;
DisplayState *ds = get_displaystate();
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
@@ -268,12 +267,6 @@ static void palmte_init(QEMUMachineInitArgs *args)
palmte_binfo.initrd_filename = initrd_filename;
arm_load_kernel(mpu->cpu, &palmte_binfo);
}
/* FIXME: We shouldn't really be doing this here. The LCD controller
will set the size once configured, so this just sets an initial
size until the guest activates the display. */
ds->surface = qemu_resize_displaysurface(ds, 320, 320);
dpy_gfx_resize(ds);
}
static QEMUMachine palmte_machine = {
hw/arm/vexpress.c
+70 -11
View File
@@ -147,19 +147,24 @@ typedef struct VEDBoardInfo VEDBoardInfo;
typedef void DBoardInitFn(const VEDBoardInfo *daughterboard,
ram_addr_t ram_size,
const char *cpu_model,
qemu_irq *pic, uint32_t *proc_id);
qemu_irq *pic);
struct VEDBoardInfo {
const hwaddr *motherboard_map;
hwaddr loader_start;
const hwaddr gic_cpu_if_addr;
uint32_t proc_id;
uint32_t num_voltage_sensors;
const uint32_t *voltages;
uint32_t num_clocks;
const uint32_t *clocks;
DBoardInitFn *init;
};
static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
ram_addr_t ram_size,
const char *cpu_model,
qemu_irq *pic, uint32_t *proc_id)
qemu_irq *pic)
{
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
@@ -175,8 +180,6 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
cpu_model = "cortex-a9";
}
*proc_id = 0x0c000191;
for (n = 0; n < smp_cpus; n++) {
ARMCPU *cpu = cpu_arm_init(cpu_model);
if (!cpu) {
@@ -247,17 +250,41 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
}
/* Voltage values for SYS_CFG_VOLT daughterboard registers;
* values are in microvolts.
*/
static const uint32_t a9_voltages[] = {
1000000, /* VD10 : 1.0V : SoC internal logic voltage */
1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
};
/* Reset values for daughterboard oscillators (in Hz) */
static const uint32_t a9_clocks[] = {
45000000, /* AMBA AXI ACLK: 45MHz */
23750000, /* daughterboard CLCD clock: 23.75MHz */
66670000, /* Test chip reference clock: 66.67MHz */
};
static const VEDBoardInfo a9_daughterboard = {
.motherboard_map = motherboard_legacy_map,
.loader_start = 0x60000000,
.gic_cpu_if_addr = 0x1e000100,
.proc_id = 0x0c000191,
.num_voltage_sensors = ARRAY_SIZE(a9_voltages),
.voltages = a9_voltages,
.num_clocks = ARRAY_SIZE(a9_clocks),
.clocks = a9_clocks,
.init = a9_daughterboard_init,
};
static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
ram_addr_t ram_size,
const char *cpu_model,
qemu_irq *pic, uint32_t *proc_id)
qemu_irq *pic)
{
int n;
MemoryRegion *sysmem = get_system_memory();
@@ -271,8 +298,6 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
cpu_model = "cortex-a15";
}
*proc_id = 0x14000237;
for (n = 0; n < smp_cpus; n++) {
ARMCPU *cpu;
qemu_irq *irqp;
@@ -340,10 +365,31 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
/* 0x7ffd0000: PL354 static memory controller: not modelled */
}
static const uint32_t a15_voltages[] = {
900000, /* Vcore: 0.9V : CPU core voltage */
};
static const uint32_t a15_clocks[] = {
60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
0, /* OSCCLK1: reserved */
0, /* OSCCLK2: reserved */
0, /* OSCCLK3: reserved */
40000000, /* OSCCLK4: 40MHz : external AXI master clock */
23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
50000000, /* OSCCLK6: 50MHz : static memory controller clock */
60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
};
static const VEDBoardInfo a15_daughterboard = {
.motherboard_map = motherboard_aseries_map,
.loader_start = 0x80000000,
.gic_cpu_if_addr = 0x2c002000,
.proc_id = 0x14000237,
.num_voltage_sensors = ARRAY_SIZE(a15_voltages),
.voltages = a15_voltages,
.num_clocks = ARRAY_SIZE(a15_clocks),
.clocks = a15_clocks,
.init = a15_daughterboard_init,
};
@@ -352,7 +398,6 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
{
DeviceState *dev, *sysctl, *pl041;
qemu_irq pic[64];
uint32_t proc_id;
uint32_t sys_id;
DriveInfo *dinfo;
ram_addr_t vram_size, sram_size;
@@ -360,9 +405,9 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
MemoryRegion *vram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
const hwaddr *map = daughterboard->motherboard_map;
int i;
daughterboard->init(daughterboard, args->ram_size, args->cpu_model,
pic, &proc_id);
daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic);
/* Motherboard peripherals: the wiring is the same but the
* addresses vary between the legacy and A-Series memory maps.
@@ -372,7 +417,21 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
sysctl = qdev_create(NULL, "realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
qdev_prop_set_uint32(sysctl, "len-db-voltage",
daughterboard->num_voltage_sensors);
for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
char *propname = g_strdup_printf("db-voltage[%d]", i);
qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
g_free(propname);
}
qdev_prop_set_uint32(sysctl, "len-db-clock",
daughterboard->num_clocks);
for (i = 0; i < daughterboard->num_clocks; i++) {
char *propname = g_strdup_printf("db-clock[%d]", i);
qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
g_free(propname);
}
qdev_init_nofail(sysctl);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
hw/arm/xilinx_zynq.c
+24
View File
@@ -35,6 +35,10 @@
#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
static const int dma_irqs[8] = {
46, 47, 48, 49, 72, 73, 74, 75
};
static struct arm_boot_info zynq_binfo = {};
static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
@@ -196,6 +200,26 @@ static void zynq_init(QEMUMachineInitArgs *args)
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
dev = qdev_create(NULL, "pl330");
qdev_prop_set_uint8(dev, "num_chnls", 8);
qdev_prop_set_uint8(dev, "num_periph_req", 4);
qdev_prop_set_uint8(dev, "num_events", 16);
qdev_prop_set_uint8(dev, "data_width", 64);
qdev_prop_set_uint8(dev, "wr_cap", 8);
qdev_prop_set_uint8(dev, "wr_q_dep", 16);
qdev_prop_set_uint8(dev, "rd_cap", 8);
qdev_prop_set_uint8(dev, "rd_q_dep", 16);
qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0xF8003000);
sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
for (n = 0; n < 8; ++n) { /* event irqs */
sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
}
zynq_binfo.ram_size = ram_size;
zynq_binfo.kernel_filename = kernel_filename;
zynq_binfo.kernel_cmdline = kernel_cmdline;
hw/arm_sysctl.c
+241 -20
View File
@@ -9,6 +9,7 @@
#include "hw/hw.h"
#include "qemu/timer.h"
#include "qemu/bitops.h"
#include "hw/sysbus.h"
#include "hw/primecell.h"
#include "sysemu/sysemu.h"
@@ -34,11 +35,17 @@ typedef struct {
uint32_t sys_cfgctrl;
uint32_t sys_cfgstat;
uint32_t sys_clcd;
uint32_t mb_clock[6];
uint32_t *db_clock;
uint32_t db_num_vsensors;
uint32_t *db_voltage;
uint32_t db_num_clocks;
uint32_t *db_clock_reset;
} arm_sysctl_state;
static const VMStateDescription vmstate_arm_sysctl = {
.name = "realview_sysctl",
.version_id = 3,
.version_id = 4,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(leds, arm_sysctl_state),
@@ -53,6 +60,9 @@ static const VMStateDescription vmstate_arm_sysctl = {
VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4),
VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks,
4, vmstate_info_uint32, uint32_t),
VMSTATE_END_OF_LIST()
}
};
@@ -76,6 +86,7 @@ static int board_id(arm_sysctl_state *s)
static void arm_sysctl_reset(DeviceState *d)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
int i;
s->leds = 0;
s->lockval = 0;
@@ -83,6 +94,17 @@ static void arm_sysctl_reset(DeviceState *d)
s->cfgdata2 = 0;
s->flags = 0;
s->resetlevel = 0;
/* Motherboard oscillators (in Hz) */
s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */
s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */
s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */
s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */
s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */
s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */
/* Daughterboard oscillators: reset from property values */
for (i = 0; i < s->db_num_clocks; i++) {
s->db_clock[i] = s->db_clock_reset[i];
}
if (board_id(s) == BOARD_ID_VEXPRESS) {
/* On VExpress this register will RAZ/WI */
s->sys_clcd = 0;
@@ -191,6 +213,166 @@ static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
}
}
/* SYS_CFGCTRL functions */
#define SYS_CFG_OSC 1
#define SYS_CFG_VOLT 2
#define SYS_CFG_AMP 3
#define SYS_CFG_TEMP 4
#define SYS_CFG_RESET 5
#define SYS_CFG_SCC 6
#define SYS_CFG_MUXFPGA 7
#define SYS_CFG_SHUTDOWN 8
#define SYS_CFG_REBOOT 9
#define SYS_CFG_DVIMODE 11
#define SYS_CFG_POWER 12
#define SYS_CFG_ENERGY 13
/* SYS_CFGCTRL site field values */
#define SYS_CFG_SITE_MB 0
#define SYS_CFG_SITE_DB1 1
#define SYS_CFG_SITE_DB2 2
/**
* vexpress_cfgctrl_read:
* @s: arm_sysctl_state pointer
* @dcc, @function, @site, @position, @device: split out values from
* SYS_CFGCTRL register
* @val: pointer to where to put the read data on success
*
* Handle a VExpress SYS_CFGCTRL register read. On success, return true and
* write the read value to *val. On failure, return false (and val may
* or may not be written to).
*/
static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc,
unsigned int function, unsigned int site,
unsigned int position, unsigned int device,
uint32_t *val)
{
/* We don't support anything other than DCC 0, board stack position 0
* or sites other than motherboard/daughterboard:
*/
if (dcc != 0 || position != 0 ||
(site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
goto cfgctrl_unimp;
}
switch (function) {
case SYS_CFG_VOLT:
if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) {
*val = s->db_voltage[device];
return true;
}
if (site == SYS_CFG_SITE_MB && device == 0) {
/* There is only one motherboard voltage sensor:
* VIO : 3.3V : bus voltage between mother and daughterboard
*/
*val = 3300000;
return true;
}
break;
case SYS_CFG_OSC:
if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) {
/* motherboard clock */
*val = s->mb_clock[device];
return true;
}
if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
/* daughterboard clock */
*val = s->db_clock[device];
return true;
}
break;
default:
break;
}
cfgctrl_unimp:
qemu_log_mask(LOG_UNIMP,
"arm_sysctl: Unimplemented SYS_CFGCTRL read of function "
"0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
function, dcc, site, position, device);
return false;
}
/**
* vexpress_cfgctrl_write:
* @s: arm_sysctl_state pointer
* @dcc, @function, @site, @position, @device: split out values from
* SYS_CFGCTRL register
* @val: data to write
*
* Handle a VExpress SYS_CFGCTRL register write. On success, return true.
* On failure, return false.
*/
static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
unsigned int function, unsigned int site,
unsigned int position, unsigned int device,
uint32_t val)
{
/* We don't support anything other than DCC 0, board stack position 0
* or sites other than motherboard/daughterboard:
*/
if (dcc != 0 || position != 0 ||
(site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
goto cfgctrl_unimp;
}
switch (function) {
case SYS_CFG_OSC:
if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) {
/* motherboard clock */
s->mb_clock[device] = val;
return true;
}
if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
/* daughterboard clock */
s->db_clock[device] = val;
return true;
}
break;
case SYS_CFG_MUXFPGA:
if (site == SYS_CFG_SITE_MB && device == 0) {
/* Select whether video output comes from motherboard
* or daughterboard: log and ignore as QEMU doesn't
* support this.
*/
qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output "
"not supported, ignoring\n");
return true;
}
break;
case SYS_CFG_SHUTDOWN:
if (site == SYS_CFG_SITE_MB && device == 0) {
qemu_system_shutdown_request();
return true;
}
break;
case SYS_CFG_REBOOT:
if (site == SYS_CFG_SITE_MB && device == 0) {
qemu_system_reset_request();
return true;
}
break;
case SYS_CFG_DVIMODE:
if (site == SYS_CFG_SITE_MB && device == 0) {
/* Selecting DVI mode is meaningless for QEMU: we will
* always display the output correctly according to the
* pixel height/width programmed into the CLCD controller.
*/
return true;
}
default:
break;
}
cfgctrl_unimp:
qemu_log_mask(LOG_UNIMP,
"arm_sysctl: Unimplemented SYS_CFGCTRL write of function "
"0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
function, dcc, site, position, device);
return false;
}
static void arm_sysctl_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
@@ -322,17 +504,33 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
if (board_id(s) != BOARD_ID_VEXPRESS) {
goto bad_reg;
}
s->sys_cfgctrl = val & ~(3 << 18);
s->sys_cfgstat = 1; /* complete */
switch (s->sys_cfgctrl) {
case 0xc0800000: /* SYS_CFG_SHUTDOWN to motherboard */
qemu_system_shutdown_request();
break;
case 0xc0900000: /* SYS_CFG_REBOOT to motherboard */
qemu_system_reset_request();
break;
default:
s->sys_cfgstat |= 2; /* error */
/* Undefined bits [19:18] are RAZ/WI, and writing to
* the start bit just triggers the action; it always reads
* as zero.
*/
s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
if (val & (1 << 31)) {
/* Start bit set -- actually do something */
unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
unsigned int site = extract32(s->sys_cfgctrl, 16, 2);
unsigned int position = extract32(s->sys_cfgctrl, 12, 4);
unsigned int device = extract32(s->sys_cfgctrl, 0, 12);
s->sys_cfgstat = 1; /* complete */
if (s->sys_cfgctrl & (1 << 30)) {
if (!vexpress_cfgctrl_write(s, dcc, function, site, position,
device, s->sys_cfgdata)) {
s->sys_cfgstat |= 2; /* error */
}
} else {
uint32_t val;
if (!vexpress_cfgctrl_read(s, dcc, function, site, position,
device, &val)) {
s->sys_cfgstat |= 2; /* error */
} else {
s->sys_cfgdata = val;
}
}
}
s->sys_cfgctrl &= ~(1 << 31);
return;
@@ -385,29 +583,50 @@ static void arm_sysctl_gpio_set(void *opaque, int line, int level)
}
}
static int arm_sysctl_init(SysBusDevice *dev)
static void arm_sysctl_init(Object *obj)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
DeviceState *dev = DEVICE(obj);
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sd);
memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
return 0;
sysbus_init_mmio(sd, &s->iomem);
qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2);
qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1);
}
static void arm_sysctl_realize(DeviceState *d, Error **errp)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
s->db_clock = g_new0(uint32_t, s->db_num_clocks);
}
static void arm_sysctl_finalize(Object *obj)
{
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
g_free(s->db_voltage);
g_free(s->db_clock);
g_free(s->db_clock_reset);
}
static Property arm_sysctl_properties[] = {
DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
/* Daughterboard power supply voltages (as reported via SYS_CFG) */
DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors,
db_voltage, qdev_prop_uint32, uint32_t),
/* Daughterboard clock reset values (as reported via SYS_CFG) */
DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks,
db_clock_reset, qdev_prop_uint32, uint32_t),
DEFINE_PROP_END_OF_LIST(),
};
static void arm_sysctl_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = arm_sysctl_init;
dc->realize = arm_sysctl_realize;
dc->reset = arm_sysctl_reset;
dc->vmsd = &vmstate_arm_sysctl;
dc->props = arm_sysctl_properties;
@@ -417,6 +636,8 @@ static const TypeInfo arm_sysctl_info = {
.name = "realview_sysctl",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(arm_sysctl_state),
.instance_init = arm_sysctl_init,
.instance_finalize = arm_sysctl_finalize,
.class_init = arm_sysctl_class_init,
};
hw/blizzard.c
+22 -15
View File
@@ -69,7 +69,7 @@ typedef struct {
uint8_t effect;
uint8_t iformat;
uint8_t source;
DisplayState *state;
QemuConsole *con;
blizzard_fn_t *line_fn_tab[2];
void *fb;
@@ -144,6 +144,7 @@ static inline void blizzard_rgb2yuv(int r, int g, int b,
static void blizzard_window(BlizzardState *s)
{
DisplaySurface *surface = qemu_console_surface(s->con);
uint8_t *src, *dst;
int bypp[2];
int bypl[3];
@@ -162,7 +163,7 @@ static void blizzard_window(BlizzardState *s)
s->my[1] = s->data.y + s->data.dy;
bypp[0] = s->bpp;
bypp[1] = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
bypp[1] = surface_bytes_per_pixel(surface);
bypl[0] = bypp[0] * s->data.pitch;
bypl[1] = bypp[1] * s->x;
bypl[2] = bypp[0] * s->data.dx;
@@ -883,23 +884,25 @@ void s1d13745_write_block(void *opaque, int dc,
static void blizzard_update_display(void *opaque)
{
BlizzardState *s = (BlizzardState *) opaque;
DisplaySurface *surface = qemu_console_surface(s->con);
int y, bypp, bypl, bwidth;
uint8_t *src, *dst;
if (!s->enable)
return;
if (s->x != ds_get_width(s->state) || s->y != ds_get_height(s->state)) {
if (s->x != surface_width(surface) || s->y != surface_height(surface)) {
s->invalidate = 1;
qemu_console_resize(s->state, s->x, s->y);
qemu_console_resize(s->con, s->x, s->y);
surface = qemu_console_surface(s->con);
}
if (s->invalidate) {
s->invalidate = 0;
if (s->blank) {
bypp = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
memset(ds_get_data(s->state), 0, bypp * s->x * s->y);
bypp = surface_bytes_per_pixel(surface);
memset(surface_data(surface), 0, bypp * s->x * s->y);
return;
}
@@ -912,16 +915,16 @@ static void blizzard_update_display(void *opaque)
if (s->mx[1] <= s->mx[0])
return;
bypp = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
bypp = surface_bytes_per_pixel(surface);
bypl = bypp * s->x;
bwidth = bypp * (s->mx[1] - s->mx[0]);
y = s->my[0];
src = s->fb + bypl * y + bypp * s->mx[0];
dst = ds_get_data(s->state) + bypl * y + bypp * s->mx[0];
dst = surface_data(surface) + bypl * y + bypp * s->mx[0];
for (; y < s->my[1]; y ++, src += bypl, dst += bypl)
memcpy(dst, src, bwidth);
dpy_gfx_update(s->state, s->mx[0], s->my[0],
dpy_gfx_update(s->con, s->mx[0], s->my[0],
s->mx[1] - s->mx[0], y - s->my[0]);
s->mx[0] = s->x;
@@ -934,10 +937,12 @@ static void blizzard_screen_dump(void *opaque, const char *filename,
bool cswitch, Error **errp)
{
BlizzardState *s = (BlizzardState *) opaque;
DisplaySurface *surface = qemu_console_surface(s->con);
blizzard_update_display(opaque);
if (s && ds_get_data(s->state))
ppm_save(filename, s->state->surface, errp);
if (s && surface_data(surface)) {
ppm_save(filename, surface, errp);
}
}
#define DEPTH 8
@@ -954,14 +959,16 @@ static void blizzard_screen_dump(void *opaque, const char *filename,
void *s1d13745_init(qemu_irq gpio_int)
{
BlizzardState *s = (BlizzardState *) g_malloc0(sizeof(*s));
DisplaySurface *surface;
s->fb = g_malloc(0x180000);
s->state = graphic_console_init(blizzard_update_display,
blizzard_invalidate_display,
blizzard_screen_dump, NULL, s);
s->con = graphic_console_init(blizzard_update_display,
blizzard_invalidate_display,
blizzard_screen_dump, NULL, s);
surface = qemu_console_surface(s->con);
switch (ds_get_bits_per_pixel(s->state)) {
switch (surface_bits_per_pixel(surface)) {
case 0:
s->line_fn_tab[0] = s->line_fn_tab[1] =
g_malloc0(sizeof(blizzard_fn_t) * 0x10);
hw/cirrus_vga.c
+12 -10
View File
@@ -729,11 +729,12 @@ static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
s->cirrus_blt_width, s->cirrus_blt_height);
if (notify)
qemu_console_copy(s->vga.ds,
if (notify) {
qemu_console_copy(s->vga.con,
sx, sy, dx, dy,
s->cirrus_blt_width / depth,
s->cirrus_blt_height);
}
/* we don't have to notify the display that this portion has
changed since qemu_console_copy implies this */
@@ -2176,6 +2177,7 @@ static void cirrus_cursor_invalidate(VGACommonState *s1)
static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
{
CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
DisplaySurface *surface = qemu_console_surface(s->vga.con);
int w, h, bpp, x1, x2, poffset;
unsigned int color0, color1;
const uint8_t *palette, *src;
@@ -2228,9 +2230,9 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
c6_to_8(palette[0xf * 3 + 1]),
c6_to_8(palette[0xf * 3 + 2]));
bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
bpp = surface_bytes_per_pixel(surface);
d1 += x1 * bpp;
switch(ds_get_bits_per_pixel(s->vga.ds)) {
switch (surface_bits_per_pixel(surface)) {
default:
break;
case 8:
@@ -2908,9 +2910,9 @@ static int vga_initfn(ISADevice *dev)
vga_common_init(s);
cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
isa_address_space(dev), isa_address_space_io(dev));
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update,
s);
s->con = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update,
s);
rom_add_vga(VGABIOS_CIRRUS_FILENAME);
/* XXX ISA-LFB support */
/* FIXME not qdev yet */
@@ -2957,9 +2959,9 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
vga_common_init(&s->vga);
cirrus_init_common(s, device_id, 1, pci_address_space(dev),
pci_address_space_io(dev));
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update,
&s->vga);
s->vga.con = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update,
&s->vga);
/* setup PCI */
hw/exynos4210_fimd.c
+10 -7
View File
@@ -296,7 +296,7 @@ struct Exynos4210fimdWindow {
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
DisplayState *console;
QemuConsole *console;
qemu_irq irq[3];
uint32_t vidcon[4]; /* Video main control registers 0-3 */
@@ -1221,16 +1221,18 @@ static void exynos4210_fimd_invalidate(void *opaque)
static void exynos4210_update_resolution(Exynos4210fimdState *s)
{
DisplaySurface *surface = qemu_console_surface(s->console);
/* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */
uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT) &
FIMD_VIDTCON2_SIZE_MASK) + 1;
uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
FIMD_VIDTCON2_SIZE_MASK) + 1;
if (s->ifb == NULL || ds_get_width(s->console) != width ||
ds_get_height(s->console) != height) {
if (s->ifb == NULL || surface_width(surface) != width ||
surface_height(surface) != height) {
DPRINT_L1("Resolution changed from %ux%u to %ux%u\n",
ds_get_width(s->console), ds_get_height(s->console), width, height);
surface_width(surface), surface_height(surface), width, height);
qemu_console_resize(s->console, width, height);
s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE + 1);
memset(s->ifb, 0, width * height * RGBA_SIZE + 1);
@@ -1241,6 +1243,7 @@ static void exynos4210_update_resolution(Exynos4210fimdState *s)
static void exynos4210_fimd_update(void *opaque)
{
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
DisplaySurface *surface = qemu_console_surface(s->console);
Exynos4210fimdWindow *w;
int i, line;
hwaddr fb_line_addr, inc_size;
@@ -1253,7 +1256,7 @@ static void exynos4210_fimd_update(void *opaque)
const int global_height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
FIMD_VIDTCON2_SIZE_MASK) + 1;
if (!s || !s->console || !ds_get_bits_per_pixel(s->console) ||
if (!s || !s->console || !surface_bits_per_pixel(surface) ||
!s->enabled) {
return;
}
@@ -1299,10 +1302,10 @@ static void exynos4210_fimd_update(void *opaque)
uint8_t *d;
int bpp;
bpp = ds_get_bits_per_pixel(s->console);
bpp = surface_bits_per_pixel(surface);
fimd_update_putpix_qemu(bpp);
bpp = (bpp + 1) >> 3;
d = ds_get_data(s->console);
d = surface_data(surface);
for (line = first_line; line <= last_line; line++) {
fimd_copy_line_toqemu(global_width, s->ifb + global_width * line *
RGBA_SIZE, d + global_width * line * bpp);
hw/framebuffer.c
+2 -2
View File
@@ -24,7 +24,7 @@
/* Render an image from a shared memory framebuffer. */
void framebuffer_update_display(
DisplayState *ds,
DisplaySurface *ds,
MemoryRegion *address_space,
hwaddr base,
int cols, /* Width in pixels. */
@@ -73,7 +73,7 @@ void framebuffer_update_display(
return;
}
src = src_base;
dest = ds_get_data(ds);
dest = surface_data(ds);
if (dest_col_pitch < 0)
dest -= dest_col_pitch * (cols - 1);
if (dest_row_pitch < 0) {
hw/framebuffer.h
+1 -1
View File
@@ -8,7 +8,7 @@
typedef void (*drawfn)(void *, uint8_t *, const uint8_t *, int, int);
void framebuffer_update_display(
DisplayState *ds,
DisplaySurface *ds,
MemoryRegion *address_space,
hwaddr base,
int cols,
hw/g364fb.c
+24 -19
View File
@@ -39,7 +39,7 @@ typedef struct G364State {
uint32_t top_of_screen;
uint32_t width, height; /* in pixels */
/* display refresh support */
DisplayState *ds;
QemuConsole *con;
int depth;
int blanked;
} G364State;
@@ -77,6 +77,7 @@ static inline void reset_dirty(G364State *s,
static void g364fb_draw_graphic8(G364State *s)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int i, w;
uint8_t *vram;
uint8_t *data_display, *dd;
@@ -87,7 +88,7 @@ static void g364fb_draw_graphic8(G364State *s)
int xcursor, ycursor;
unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
switch (ds_get_bits_per_pixel(s->ds)) {
switch (surface_bits_per_pixel(surface)) {
case 8:
rgb_to_pixel = rgb_to_pixel8;
w = 1;
@@ -106,7 +107,7 @@ static void g364fb_draw_graphic8(G364State *s)
break;
default:
hw_error("g364: unknown host depth %d",
ds_get_bits_per_pixel(s->ds));
surface_bits_per_pixel(surface));
return;
}
@@ -129,7 +130,7 @@ static void g364fb_draw_graphic8(G364State *s)
vram = s->vram + s->top_of_screen;
/* XXX: out of range in vram? */
data_display = dd = ds_get_data(s->ds);
data_display = dd = surface_data(surface);
while (y < s->height) {
if (check_dirty(s, page)) {
if (y < ymin)
@@ -182,7 +183,7 @@ static void g364fb_draw_graphic8(G364State *s)
ymax = s->height - 1;
goto done;
}
data_display = dd = data_display + ds_get_linesize(s->ds);
data_display = dd = data_display + surface_stride(surface);
xmin = 0;
x = 0;
}
@@ -197,7 +198,7 @@ static void g364fb_draw_graphic8(G364State *s)
reset_dirty(s, page_min, page_max);
page_min = (ram_addr_t)-1;
page_max = 0;
dpy_gfx_update(s->ds, xmin, ymin,
dpy_gfx_update(s->con, xmin, ymin,
xmax - xmin + 1, ymax - ymin + 1);
xmin = s->width;
xmax = 0;
@@ -209,7 +210,7 @@ static void g364fb_draw_graphic8(G364State *s)
x = x % s->width;
y += dy;
vram += G364_PAGE_SIZE;
data_display += dy * ds_get_linesize(s->ds);
data_display += dy * surface_stride(surface);
dd = data_display + x * w;
}
page += G364_PAGE_SIZE;
@@ -217,13 +218,14 @@ static void g364fb_draw_graphic8(G364State *s)
done:
if (page_min != (ram_addr_t)-1) {
dpy_gfx_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
reset_dirty(s, page_min, page_max);
}
}
static void g364fb_draw_blank(G364State *s)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int i, w;
uint8_t *d;
@@ -232,28 +234,30 @@ static void g364fb_draw_blank(G364State *s)
return;
}
w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
d = ds_get_data(s->ds);
w = s->width * surface_bytes_per_pixel(surface);
d = surface_data(surface);
for (i = 0; i < s->height; i++) {
memset(d, 0, w);
d += ds_get_linesize(s->ds);
d += surface_stride(surface);
}
dpy_gfx_update(s->ds, 0, 0, s->width, s->height);
dpy_gfx_update(s->con, 0, 0, s->width, s->height);
s->blanked = 1;
}
static void g364fb_update_display(void *opaque)
{
G364State *s = opaque;
DisplaySurface *surface = qemu_console_surface(s->con);
qemu_flush_coalesced_mmio_buffer();
if (s->width == 0 || s->height == 0)
return;
if (s->width != ds_get_width(s->ds) || s->height != ds_get_height(s->ds)) {
qemu_console_resize(s->ds, s->width, s->height);
if (s->width != surface_width(surface) ||
s->height != surface_height(surface)) {
qemu_console_resize(s->con, s->width, s->height);
}
if (s->ctla & CTLA_FORCE_BLANK) {
@@ -413,13 +417,14 @@ static void g364fb_update_depth(G364State *s)
static void g364_invalidate_cursor_position(G364State *s)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int ymin, ymax, start, end;
/* invalidate only near the cursor */
ymin = s->cursor_position & 0xfff;
ymax = MIN(s->height, ymin + 64);
start = ymin * ds_get_linesize(s->ds);
end = (ymax + 1) * ds_get_linesize(s->ds);
start = ymin * surface_stride(surface);
end = (ymax + 1) * surface_stride(surface);
memory_region_set_dirty(&s->mem_vram, start, end - start);
}
@@ -545,9 +550,9 @@ static void g364fb_init(DeviceState *dev, G364State *s)
{
s->vram = g_malloc0(s->vram_size);
s->ds = graphic_console_init(g364fb_update_display,
g364fb_invalidate_display,
g364fb_screen_dump, NULL, s);
s->con = graphic_console_init(g364fb_update_display,
g364fb_invalidate_display,
g364fb_screen_dump, NULL, s);
memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
memory_region_init_ram_ptr(&s->mem_vram, "vram",
hw/jazz_led.c
+50 -38
View File
@@ -36,7 +36,7 @@ typedef struct LedState {
SysBusDevice busdev;
MemoryRegion iomem;
uint8_t segments;
DisplayState *ds;
QemuConsole *con;
screen_state_t state;
} LedState;
@@ -75,13 +75,15 @@ static const MemoryRegionOps led_ops = {
/***********************************************************/
/* jazz_led display */
static void draw_horizontal_line(DisplayState *ds, int posy, int posx1, int posx2, uint32_t color)
static void draw_horizontal_line(DisplaySurface *ds,
int posy, int posx1, int posx2,
uint32_t color)
{
uint8_t *d;
int x, bpp;
bpp = (ds_get_bits_per_pixel(ds) + 7) >> 3;
d = ds_get_data(ds) + ds_get_linesize(ds) * posy + bpp * posx1;
bpp = (surface_bits_per_pixel(ds) + 7) >> 3;
d = surface_data(ds) + surface_stride(ds) * posy + bpp * posx1;
switch(bpp) {
case 1:
for (x = posx1; x <= posx2; x++) {
@@ -104,30 +106,32 @@ static void draw_horizontal_line(DisplayState *ds, int posy, int posx1, int posx
}
}
static void draw_vertical_line(DisplayState *ds, int posx, int posy1, int posy2, uint32_t color)
static void draw_vertical_line(DisplaySurface *ds,
int posx, int posy1, int posy2,
uint32_t color)
{
uint8_t *d;
int y, bpp;
bpp = (ds_get_bits_per_pixel(ds) + 7) >> 3;
d = ds_get_data(ds) + ds_get_linesize(ds) * posy1 + bpp * posx;
bpp = (surface_bits_per_pixel(ds) + 7) >> 3;
d = surface_data(ds) + surface_stride(ds) * posy1 + bpp * posx;
switch(bpp) {
case 1:
for (y = posy1; y <= posy2; y++) {
*((uint8_t *)d) = color;
d += ds_get_linesize(ds);
d += surface_stride(ds);
}
break;
case 2:
for (y = posy1; y <= posy2; y++) {
*((uint16_t *)d) = color;
d += ds_get_linesize(ds);
d += surface_stride(ds);
}
break;
case 4:
for (y = posy1; y <= posy2; y++) {
*((uint32_t *)d) = color;
d += ds_get_linesize(ds);
d += surface_stride(ds);
}
break;
}
@@ -136,24 +140,24 @@ static void draw_vertical_line(DisplayState *ds, int posx, int posy1, int posy2,
static void jazz_led_update_display(void *opaque)
{
LedState *s = opaque;
DisplayState *ds = s->ds;
DisplaySurface *surface = qemu_console_surface(s->con);
uint8_t *d1;
uint32_t color_segment, color_led;
int y, bpp;
if (s->state & REDRAW_BACKGROUND) {
/* clear screen */
bpp = (ds_get_bits_per_pixel(ds) + 7) >> 3;
d1 = ds_get_data(ds);
for (y = 0; y < ds_get_height(ds); y++) {
memset(d1, 0x00, ds_get_width(ds) * bpp);
d1 += ds_get_linesize(ds);
bpp = (surface_bits_per_pixel(surface) + 7) >> 3;
d1 = surface_data(surface);
for (y = 0; y < surface_height(surface); y++) {
memset(d1, 0x00, surface_width(surface) * bpp);
d1 += surface_stride(surface);
}
}
if (s->state & REDRAW_SEGMENTS) {
/* set colors according to bpp */
switch (ds_get_bits_per_pixel(ds)) {
switch (surface_bits_per_pixel(surface)) {
case 8:
color_segment = rgb_to_pixel8(0xaa, 0xaa, 0xaa);
color_led = rgb_to_pixel8(0x00, 0xff, 0x00);
@@ -178,26 +182,34 @@ static void jazz_led_update_display(void *opaque)
}
/* display segments */
draw_horizontal_line(ds, 40, 10, 40, (s->segments & 0x02) ? color_segment : 0);
draw_vertical_line(ds, 10, 10, 40, (s->segments & 0x04) ? color_segment : 0);
draw_vertical_line(ds, 10, 40, 70, (s->segments & 0x08) ? color_segment : 0);
draw_horizontal_line(ds, 70, 10, 40, (s->segments & 0x10) ? color_segment : 0);
draw_vertical_line(ds, 40, 40, 70, (s->segments & 0x20) ? color_segment : 0);
draw_vertical_line(ds, 40, 10, 40, (s->segments & 0x40) ? color_segment : 0);
draw_horizontal_line(ds, 10, 10, 40, (s->segments & 0x80) ? color_segment : 0);
draw_horizontal_line(surface, 40, 10, 40,
(s->segments & 0x02) ? color_segment : 0);
draw_vertical_line(surface, 10, 10, 40,
(s->segments & 0x04) ? color_segment : 0);
draw_vertical_line(surface, 10, 40, 70,
(s->segments & 0x08) ? color_segment : 0);
draw_horizontal_line(surface, 70, 10, 40,
(s->segments & 0x10) ? color_segment : 0);
draw_vertical_line(surface, 40, 40, 70,
(s->segments & 0x20) ? color_segment : 0);
draw_vertical_line(surface, 40, 10, 40,
(s->segments & 0x40) ? color_segment : 0);
draw_horizontal_line(surface, 10, 10, 40,
(s->segments & 0x80) ? color_segment : 0);
/* display led */
if (!(s->segments & 0x01))
color_led = 0; /* black */
draw_horizontal_line(ds, 68, 50, 50, color_led);
draw_horizontal_line(ds, 69, 49, 51, color_led);
draw_horizontal_line(ds, 70, 48, 52, color_led);
draw_horizontal_line(ds, 71, 49, 51, color_led);
draw_horizontal_line(ds, 72, 50, 50, color_led);
draw_horizontal_line(surface, 68, 50, 50, color_led);
draw_horizontal_line(surface, 69, 49, 51, color_led);
draw_horizontal_line(surface, 70, 48, 52, color_led);
draw_horizontal_line(surface, 71, 49, 51, color_led);
draw_horizontal_line(surface, 72, 50, 50, color_led);
}
s->state = REDRAW_NONE;
dpy_gfx_update(ds, 0, 0, ds_get_width(ds), ds_get_height(ds));
dpy_gfx_update(s->con, 0, 0,
surface_width(surface), surface_height(surface));
}
static void jazz_led_invalidate_display(void *opaque)
@@ -211,15 +223,15 @@ static void jazz_led_text_update(void *opaque, console_ch_t *chardata)
LedState *s = opaque;
char buf[2];
dpy_text_cursor(s->ds, -1, -1);
qemu_console_resize(s->ds, 2, 1);
dpy_text_cursor(s->con, -1, -1);
qemu_console_resize(s->con, 2, 1);
/* TODO: draw the segments */
snprintf(buf, 2, "%02hhx\n", s->segments);
console_write_ch(chardata++, 0x00200100 | buf[0]);
console_write_ch(chardata++, 0x00200100 | buf[1]);
dpy_text_update(s->ds, 0, 0, 2, 1);
dpy_text_update(s->con, 0, 0, 2, 1);
}
static int jazz_led_post_load(void *opaque, int version_id)
@@ -249,10 +261,10 @@ static int jazz_led_init(SysBusDevice *dev)
memory_region_init_io(&s->iomem, &led_ops, s, "led", 1);
sysbus_init_mmio(dev, &s->iomem);
s->ds = graphic_console_init(jazz_led_update_display,
jazz_led_invalidate_display,
NULL,
jazz_led_text_update, s);
s->con = graphic_console_init(jazz_led_update_display,
jazz_led_invalidate_display,
NULL,
jazz_led_text_update, s);
return 0;
}
@@ -263,7 +275,7 @@ static void jazz_led_reset(DeviceState *d)
s->segments = 0;
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
qemu_console_resize(s->ds, 60, 80);
qemu_console_resize(s->con, 60, 80);
}
static void jazz_led_class_init(ObjectClass *klass, void *data)
hw/milkymist-vgafb.c
+9 -8
View File
@@ -66,7 +66,7 @@ enum {
struct MilkymistVgafbState {
SysBusDevice busdev;
MemoryRegion regs_region;
DisplayState *ds;
QemuConsole *con;
int invalidate;
uint32_t fb_offset;
@@ -84,6 +84,7 @@ static int vgafb_enabled(MilkymistVgafbState *s)
static void vgafb_update_display(void *opaque)
{
MilkymistVgafbState *s = opaque;
DisplaySurface *surface = qemu_console_surface(s->con);
int first = 0;
int last = 0;
drawfn fn;
@@ -94,7 +95,7 @@ static void vgafb_update_display(void *opaque)
int dest_width = s->regs[R_HRES];
switch (ds_get_bits_per_pixel(s->ds)) {
switch (surface_bits_per_pixel(surface)) {
case 0:
return;
case 8:
@@ -121,7 +122,7 @@ static void vgafb_update_display(void *opaque)
break;
}
framebuffer_update_display(s->ds, sysbus_address_space(&s->busdev),
framebuffer_update_display(surface, sysbus_address_space(&s->busdev),
s->regs[R_BASEADDRESS] + s->fb_offset,
s->regs[R_HRES],
s->regs[R_VRES],
@@ -134,7 +135,7 @@ static void vgafb_update_display(void *opaque)
&first, &last);
if (first >= 0) {
dpy_gfx_update(s->ds, 0, first, s->regs[R_HRES], last - first + 1);
dpy_gfx_update(s->con, 0, first, s->regs[R_HRES], last - first + 1);
}
s->invalidate = 0;
}
@@ -151,7 +152,7 @@ static void vgafb_resize(MilkymistVgafbState *s)
return;
}
qemu_console_resize(s->ds, s->regs[R_HRES], s->regs[R_VRES]);
qemu_console_resize(s->con, s->regs[R_HRES], s->regs[R_VRES]);
s->invalidate = 1;
}
@@ -277,9 +278,9 @@ static int milkymist_vgafb_init(SysBusDevice *dev)
"milkymist-vgafb", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
s->ds = graphic_console_init(vgafb_update_display,
vgafb_invalidate_display,
NULL, NULL, s);
s->con = graphic_console_init(vgafb_update_display,
vgafb_invalidate_display,
NULL, NULL, s);
return 0;
}
hw/omap_lcdc.c
+26 -21
View File
@@ -26,7 +26,7 @@ struct omap_lcd_panel_s {
MemoryRegion *sysmem;
MemoryRegion iomem;
qemu_irq irq;
DisplayState *state;
QemuConsole *con;
int plm;
int tft;
@@ -113,14 +113,16 @@ static draw_line_func draw_line_table2[33] = {
static void omap_update_display(void *opaque)
{
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
DisplaySurface *surface = qemu_console_surface(omap_lcd->con);
draw_line_func draw_line;
int size, height, first, last;
int width, linesize, step, bpp, frame_offset;
hwaddr frame_base;
if (!omap_lcd || omap_lcd->plm == 1 ||
!omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable ||
!surface_bits_per_pixel(surface)) {
return;
}
frame_offset = 0;
if (omap_lcd->plm != 2) {
@@ -139,25 +141,25 @@ static void omap_update_display(void *opaque)
/* Colour depth */
switch ((omap_lcd->palette[0] >> 12) & 7) {
case 1:
draw_line = draw_line_table2[ds_get_bits_per_pixel(omap_lcd->state)];
draw_line = draw_line_table2[surface_bits_per_pixel(surface)];
bpp = 2;
break;
case 2:
draw_line = draw_line_table4[ds_get_bits_per_pixel(omap_lcd->state)];
draw_line = draw_line_table4[surface_bits_per_pixel(surface)];
bpp = 4;
break;
case 3:
draw_line = draw_line_table8[ds_get_bits_per_pixel(omap_lcd->state)];
draw_line = draw_line_table8[surface_bits_per_pixel(surface)];
bpp = 8;
break;
case 4 ... 7:
if (!omap_lcd->tft)
draw_line = draw_line_table12[ds_get_bits_per_pixel(omap_lcd->state)];
draw_line = draw_line_table12[surface_bits_per_pixel(surface)];
else
draw_line = draw_line_table16[ds_get_bits_per_pixel(omap_lcd->state)];
draw_line = draw_line_table16[surface_bits_per_pixel(surface)];
bpp = 16;
break;
@@ -168,10 +170,11 @@ static void omap_update_display(void *opaque)
/* Resolution */
width = omap_lcd->width;
if (width != ds_get_width(omap_lcd->state) ||
omap_lcd->height != ds_get_height(omap_lcd->state)) {
qemu_console_resize(omap_lcd->state,
if (width != surface_width(surface) ||
omap_lcd->height != surface_height(surface)) {
qemu_console_resize(omap_lcd->con,
omap_lcd->width, omap_lcd->height);
surface = qemu_console_surface(omap_lcd->con);
omap_lcd->invalidate = 1;
}
@@ -196,8 +199,9 @@ static void omap_update_display(void *opaque)
if (omap_lcd->dma->dual)
omap_lcd->dma->current_frame ^= 1;
if (!ds_get_bits_per_pixel(omap_lcd->state))
if (!surface_bits_per_pixel(surface)) {
return;
}
first = 0;
height = omap_lcd->height;
@@ -210,15 +214,15 @@ static void omap_update_display(void *opaque)
}
step = width * bpp >> 3;
linesize = ds_get_linesize(omap_lcd->state);
framebuffer_update_display(omap_lcd->state, omap_lcd->sysmem,
linesize = surface_stride(surface);
framebuffer_update_display(surface, omap_lcd->sysmem,
frame_base, width, height,
step, linesize, 0,
omap_lcd->invalidate,
draw_line, omap_lcd->palette,
&first, &last);
if (first >= 0) {
dpy_gfx_update(omap_lcd->state, 0, first, width, last - first + 1);
dpy_gfx_update(omap_lcd->con, 0, first, width, last - first + 1);
}
omap_lcd->invalidate = 0;
}
@@ -298,12 +302,13 @@ static void omap_screen_dump(void *opaque, const char *filename, bool cswitch,
Error **errp)
{
struct omap_lcd_panel_s *omap_lcd = opaque;
DisplaySurface *surface = qemu_console_surface(omap_lcd->con);
omap_update_display(opaque);
if (omap_lcd && ds_get_data(omap_lcd->state))
omap_ppm_save(filename, ds_get_data(omap_lcd->state),
if (omap_lcd && surface_data(surface))
omap_ppm_save(filename, surface_data(surface),
omap_lcd->width, omap_lcd->height,
ds_get_linesize(omap_lcd->state), errp);
surface_stride(surface), errp);
}
static void omap_invalidate_display(void *opaque) {
@@ -480,9 +485,9 @@ struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
memory_region_init_io(&s->iomem, &omap_lcdc_ops, s, "omap.lcdc", 0x100);
memory_region_add_subregion(sysmem, base, &s->iomem);
s->state = graphic_console_init(omap_update_display,
omap_invalidate_display,
omap_screen_dump, NULL, s);
s->con = graphic_console_init(omap_update_display,
omap_invalidate_display,
omap_screen_dump, NULL, s);
return s;
}
hw/pl110.c
+13 -11
View File
@@ -42,7 +42,7 @@ enum pl110_version
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
DisplayState *ds;
QemuConsole *con;
int version;
uint32_t timing[4];
@@ -129,6 +129,7 @@ static int pl110_enabled(pl110_state *s)
static void pl110_update_display(void *opaque)
{
pl110_state *s = (pl110_state *)opaque;
DisplaySurface *surface = qemu_console_surface(s->con);
drawfn* fntable;
drawfn fn;
int dest_width;
@@ -140,7 +141,7 @@ static void pl110_update_display(void *opaque)
if (!pl110_enabled(s))
return;
switch (ds_get_bits_per_pixel(s->ds)) {
switch (surface_bits_per_pixel(surface)) {
case 0:
return;
case 8:
@@ -231,14 +232,14 @@ static void pl110_update_display(void *opaque)
}
dest_width *= s->cols;
first = 0;
framebuffer_update_display(s->ds, sysbus_address_space(&s->busdev),
framebuffer_update_display(surface, sysbus_address_space(&s->busdev),
s->upbase, s->cols, s->rows,
src_width, dest_width, 0,
s->invalidate,
fn, s->palette,
&first, &last);
if (first >= 0) {
dpy_gfx_update(s->ds, 0, first, s->cols, last - first + 1);
dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
}
s->invalidate = 0;
}
@@ -248,12 +249,13 @@ static void pl110_invalidate_display(void * opaque)
pl110_state *s = (pl110_state *)opaque;
s->invalidate = 1;
if (pl110_enabled(s)) {
qemu_console_resize(s->ds, s->cols, s->rows);
qemu_console_resize(s->con, s->cols, s->rows);
}
}
static void pl110_update_palette(pl110_state *s, int n)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int i;
uint32_t raw;
unsigned int r, g, b;
@@ -268,7 +270,7 @@ static void pl110_update_palette(pl110_state *s, int n)
b = (raw & 0x1f) << 3;
/* The I bit is ignored. */
raw >>= 6;
switch (ds_get_bits_per_pixel(s->ds)) {
switch (surface_bits_per_pixel(surface)) {
case 8:
s->palette[n] = rgb_to_pixel8(r, g, b);
break;
@@ -291,7 +293,7 @@ static void pl110_resize(pl110_state *s, int width, int height)
{
if (width != s->cols || height != s->rows) {
if (pl110_enabled(s)) {
qemu_console_resize(s->ds, width, height);
qemu_console_resize(s->con, width, height);
}
}
s->cols = width;
@@ -409,7 +411,7 @@ static void pl110_write(void *opaque, hwaddr offset,
s->cr = val;
s->bpp = (val >> 1) & 7;
if (pl110_enabled(s)) {
qemu_console_resize(s->ds, s->cols, s->rows);
qemu_console_resize(s->con, s->cols, s->rows);
}
break;
case 10: /* LCDICR */
@@ -450,9 +452,9 @@ static int pl110_init(SysBusDevice *dev)
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);
s->ds = graphic_console_init(pl110_update_display,
pl110_invalidate_display,
NULL, NULL, s);
s->con = graphic_console_init(pl110_update_display,
pl110_invalidate_display,
NULL, NULL, s);
return 0;
}
hw/pl330.c
+1654
View File
File diff suppressed because it is too large Load Diff
hw/pxa2xx_lcd.c
+23 -16
View File
@@ -39,7 +39,7 @@ struct PXA2xxLCDState {
int irqlevel;
int invalidated;
DisplayState *ds;
QemuConsole *con;
drawfn *line_fn[2];
int dest_width;
int xres, yres;
@@ -579,6 +579,7 @@ static const MemoryRegionOps pxa2xx_lcdc_ops = {
/* Load new palette for a given DMA channel, convert to internal format */
static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int i, n, format, r, g, b, alpha;
uint32_t *dest;
uint8_t *src;
@@ -652,7 +653,7 @@ static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
src += 4;
break;
}
switch (ds_get_bits_per_pixel(s->ds)) {
switch (surface_bits_per_pixel(surface)) {
case 8:
*dest = rgb_to_pixel8(r, g, b) | alpha;
break;
@@ -676,6 +677,7 @@ static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
hwaddr addr, int *miny, int *maxy)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int src_width, dest_width;
drawfn fn = NULL;
if (s->dest_width)
@@ -693,7 +695,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
dest_width = s->xres * s->dest_width;
*miny = 0;
framebuffer_update_display(s->ds, s->sysmem,
framebuffer_update_display(surface, s->sysmem,
addr, s->xres, s->yres,
src_width, dest_width, s->dest_width,
s->invalidated,
@@ -703,6 +705,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
hwaddr addr, int *miny, int *maxy)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int src_width, dest_width;
drawfn fn = NULL;
if (s->dest_width)
@@ -720,7 +723,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
dest_width = s->yres * s->dest_width;
*miny = 0;
framebuffer_update_display(s->ds, s->sysmem,
framebuffer_update_display(surface, s->sysmem,
addr, s->xres, s->yres,
src_width, s->dest_width, -dest_width,
s->invalidated,
@@ -731,6 +734,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
hwaddr addr, int *miny, int *maxy)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int src_width, dest_width;
drawfn fn = NULL;
if (s->dest_width) {
@@ -751,7 +755,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
dest_width = s->xres * s->dest_width;
*miny = 0;
framebuffer_update_display(s->ds, s->sysmem,
framebuffer_update_display(surface, s->sysmem,
addr, s->xres, s->yres,
src_width, -dest_width, -s->dest_width,
s->invalidated,
@@ -761,6 +765,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
hwaddr addr, int *miny, int *maxy)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int src_width, dest_width;
drawfn fn = NULL;
if (s->dest_width) {
@@ -781,7 +786,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
dest_width = s->yres * s->dest_width;
*miny = 0;
framebuffer_update_display(s->ds, s->sysmem,
framebuffer_update_display(surface, s->sysmem,
addr, s->xres, s->yres,
src_width, -s->dest_width, dest_width,
s->invalidated,
@@ -800,9 +805,9 @@ static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
if (width != s->xres || height != s->yres) {
if (s->orientation == 90 || s->orientation == 270) {
qemu_console_resize(s->ds, height, width);
qemu_console_resize(s->con, height, width);
} else {
qemu_console_resize(s->ds, width, height);
qemu_console_resize(s->con, width, height);
}
s->invalidated = 1;
s->xres = width;
@@ -871,20 +876,20 @@ static void pxa2xx_update_display(void *opaque)
if (miny >= 0) {
switch (s->orientation) {
case 0:
dpy_gfx_update(s->ds, 0, miny, s->xres, maxy - miny + 1);
dpy_gfx_update(s->con, 0, miny, s->xres, maxy - miny + 1);
break;
case 90:
dpy_gfx_update(s->ds, miny, 0, maxy - miny + 1, s->xres);
dpy_gfx_update(s->con, miny, 0, maxy - miny + 1, s->xres);
break;
case 180:
maxy = s->yres - maxy - 1;
miny = s->yres - miny - 1;
dpy_gfx_update(s->ds, 0, maxy, s->xres, miny - maxy + 1);
dpy_gfx_update(s->con, 0, maxy, s->xres, miny - maxy + 1);
break;
case 270:
maxy = s->yres - maxy - 1;
miny = s->yres - miny - 1;
dpy_gfx_update(s->ds, maxy, 0, miny - maxy + 1, s->xres);
dpy_gfx_update(s->con, maxy, 0, miny - maxy + 1, s->xres);
break;
}
}
@@ -990,6 +995,7 @@ PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
hwaddr base, qemu_irq irq)
{
PXA2xxLCDState *s;
DisplaySurface *surface;
s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
s->invalidated = 1;
@@ -1002,11 +1008,12 @@ PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
"pxa2xx-lcd-controller", 0x00100000);
memory_region_add_subregion(sysmem, base, &s->iomem);
s->ds = graphic_console_init(pxa2xx_update_display,
pxa2xx_invalidate_display,
NULL, NULL, s);
s->con = graphic_console_init(pxa2xx_update_display,
pxa2xx_invalidate_display,
NULL, NULL, s);
surface = qemu_console_surface(s->con);
switch (ds_get_bits_per_pixel(s->ds)) {
switch (surface_bits_per_pixel(surface)) {
case 0:
s->dest_width = 0;
break;

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