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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160512' into staging

Browse Source 
target-arm queue:
 * blizzard, omap_lcdc: code cleanup to remove DEPTH != 32 dead code
 * QOMify various ARM devices
 * bcm2835_property: use cached values when querying framebuffer
 * hw/arm/nseries: don't allocate large sized array on the stack
 * fix LPAE descriptor address masking (only visible for EL2)
 * fix stage 2 exec permission handling for AArch32
 * first part of supporting syndrome info for data aborts to EL2
 * virt: NUMA support
 * work towards i.MX6 support
 * avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writes

# gpg: Signature made Thu 12 May 2016 14:29:14 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20160512: (43 commits)
  hw/arm: QOM'ify versatilepb.c
  hw/arm: QOM'ify strongarm.c
  hw/arm: QOM'ify stellaris.c
  hw/arm: QOM'ify spitz.c
  hw/arm: QOM'ify pxa2xx_pic.c
  hw/arm: QOM'ify pxa2xx.c
  hw/arm: QOM'ify integratorcp.c
  hw/arm: QOM'ify highbank.c
  hw/arm: QOM'ify armv7m.c
  target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writes
  hw/display/blizzard: Remove blizzard_template.h
  hw/display/blizzard: Expand out macros
  i.MX: Add sabrelite i.MX6 emulation.
  i.MX: Add i.MX6 SOC implementation.
  i.MX: Add the Freescale SPI Controller
  FIFO: Add a FIFO32 implementation
  i.MX: Add i.MX6 System Reset Controller device.
  ARM: Factor out ARM on/off PSCI control functions
  ACPI: Virt: Generate SRAT table
  ACPI: move acpi_build_srat_memory to common place
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2016-05-12 15:55:45 +01:00
parent 6ddeeffffe 0bc91ab3bb
commit e4f70d6358
53 changed files with 2976 additions and 643 deletions
Download Patch File Download Diff File Expand all files Collapse all files
default-configs/arm-softmmu.mak
+1
View File
@@ -100,6 +100,7 @@ CONFIG_ALLWINNER_A10_PIT=y
CONFIG_ALLWINNER_A10_PIC=y
CONFIG_ALLWINNER_A10=y
CONFIG_FSL_IMX6=y
CONFIG_FSL_IMX31=y
CONFIG_FSL_IMX25=y
hw/acpi/aml-build.c
+11
View File
@@ -1563,3 +1563,14 @@ build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets,
build_header(linker, table_data,
(void *)rsdt, "RSDT", rsdt_len, 1, oem_id, oem_table_id);
}
void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
uint64_t len, int node, MemoryAffinityFlags flags)
{
numamem->type = ACPI_SRAT_MEMORY;
numamem->length = sizeof(*numamem);
numamem->proximity = cpu_to_le32(node);
numamem->flags = cpu_to_le32(flags);
numamem->base_addr = cpu_to_le64(base);
numamem->range_length = cpu_to_le64(len);
}
hw/arm/Makefile.objs
+1
View File
@@ -16,4 +16,5 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
obj-$(CONFIG_ASPEED_SOC) += ast2400.o palmetto-bmc.o
hw/arm/armv7m.c
+5 -6
View File
@@ -132,14 +132,14 @@ typedef struct {
uint32_t base;
} BitBandState;
static int bitband_init(SysBusDevice *dev)
static void bitband_init(Object *obj)
{
BitBandState *s = BITBAND(dev);
BitBandState *s = BITBAND(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &bitband_ops, &s->base,
memory_region_init_io(&s->iomem, obj, &bitband_ops, &s->base,
"bitband", 0x02000000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static void armv7m_bitband_init(void)
@@ -244,9 +244,7 @@ static Property bitband_properties[] = {
static void bitband_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = bitband_init;
dc->props = bitband_properties;
}
@@ -254,6 +252,7 @@ static const TypeInfo bitband_info = {
.name = TYPE_BITBAND,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BitBandState),
.instance_init = bitband_init,
.class_init = bitband_class_init,
};
hw/arm/boot.c
+37 -6
View File
@@ -14,6 +14,7 @@
#include "hw/arm/linux-boot-if.h"
#include "sysemu/kvm.h"
#include "sysemu/sysemu.h"
#include "sysemu/numa.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "elf.h"
@@ -405,6 +406,9 @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
void *fdt = NULL;
int size, rc;
uint32_t acells, scells;
char *nodename;
unsigned int i;
hwaddr mem_base, mem_len;
if (binfo->dtb_filename) {
char *filename;
@@ -456,12 +460,39 @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
goto fail;
}
rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg",
acells, binfo->loader_start,
scells, binfo->ram_size);
if (rc < 0) {
fprintf(stderr, "couldn't set /memory/reg\n");
goto fail;
if (nb_numa_nodes > 0) {
/*
* Turn the /memory node created before into a NOP node, then create
* /memory@addr nodes for all numa nodes respectively.
*/
qemu_fdt_nop_node(fdt, "/memory");
mem_base = binfo->loader_start;
for (i = 0; i < nb_numa_nodes; i++) {
mem_len = numa_info[i].node_mem;
nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
acells, mem_base,
scells, mem_len);
if (rc < 0) {
fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename,
i);
goto fail;
}
qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i);
mem_base += mem_len;
g_free(nodename);
}
} else {
rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg",
acells, binfo->loader_start,
scells, binfo->ram_size);
if (rc < 0) {
fprintf(stderr, "couldn't set /memory/reg\n");
goto fail;
}
}
if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
hw/arm/fsl-imx6.c
+449
View File
@@ -0,0 +1,449 @@
/*
* Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
*
* i.MX6 SOC emulation.
*
* Based on hw/arm/fsl-imx31.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "hw/arm/fsl-imx6.h"
#include "sysemu/sysemu.h"
#include "sysemu/char.h"
#include "qemu/error-report.h"
#define NAME_SIZE 20
static void fsl_imx6_init(Object *obj)
{
FslIMX6State *s = FSL_IMX6(obj);
char name[NAME_SIZE];
int i;
if (smp_cpus > FSL_IMX6_NUM_CPUS) {
error_report("%s: Only %d CPUs are supported (%d requested)",
TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
exit(1);
}
for (i = 0; i < smp_cpus; i++) {
object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
"cortex-a9-" TYPE_ARM_CPU);
snprintf(name, NAME_SIZE, "cpu%d", i);
object_property_add_child(obj, name, OBJECT(&s->cpu[i]), NULL);
}
object_initialize(&s->a9mpcore, sizeof(s->a9mpcore), TYPE_A9MPCORE_PRIV);
qdev_set_parent_bus(DEVICE(&s->a9mpcore), sysbus_get_default());
object_property_add_child(obj, "a9mpcore", OBJECT(&s->a9mpcore), NULL);
object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM);
qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
object_property_add_child(obj, "ccm", OBJECT(&s->ccm), NULL);
object_initialize(&s->src, sizeof(s->src), TYPE_IMX6_SRC);
qdev_set_parent_bus(DEVICE(&s->src), sysbus_get_default());
object_property_add_child(obj, "src", OBJECT(&s->src), NULL);
for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "uart%d", i + 1);
object_property_add_child(obj, name, OBJECT(&s->uart[i]), NULL);
}
object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);
qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
object_property_add_child(obj, "gpt", OBJECT(&s->gpt), NULL);
for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "epit%d", i + 1);
object_property_add_child(obj, name, OBJECT(&s->epit[i]), NULL);
}
for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
object_property_add_child(obj, name, OBJECT(&s->i2c[i]), NULL);
}
for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "gpio%d", i + 1);
object_property_add_child(obj, name, OBJECT(&s->gpio[i]), NULL);
}
for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
object_initialize(&s->esdhc[i], sizeof(s->esdhc[i]), TYPE_SYSBUS_SDHCI);
qdev_set_parent_bus(DEVICE(&s->esdhc[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
object_property_add_child(obj, name, OBJECT(&s->esdhc[i]), NULL);
}
for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
object_initialize(&s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI);
qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "spi%d", i + 1);
object_property_add_child(obj, name, OBJECT(&s->spi[i]), NULL);
}
}
static void fsl_imx6_realize(DeviceState *dev, Error **errp)
{
FslIMX6State *s = FSL_IMX6(dev);
uint16_t i;
Error *err = NULL;
for (i = 0; i < smp_cpus; i++) {
/* On uniprocessor, the CBAR is set to 0 */
if (smp_cpus > 1) {
object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR,
"reset-cbar", &error_abort);
}
/* All CPU but CPU 0 start in power off mode */
if (i) {
object_property_set_bool(OBJECT(&s->cpu[i]), true,
"start-powered-off", &error_abort);
}
object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
}
object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu",
&error_abort);
object_property_set_int(OBJECT(&s->a9mpcore),
FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
&error_abort);
object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
for (i = 0; i < smp_cpus; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
}
object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
object_property_set_bool(OBJECT(&s->src), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
/* Initialize all UARTs */
for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
static const struct {
hwaddr addr;
unsigned int irq;
} serial_table[FSL_IMX6_NUM_UARTS] = {
{ FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
{ FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
{ FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
{ FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
{ FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
};
if (i < MAX_SERIAL_PORTS) {
CharDriverState *chr;
chr = serial_hds[i];
if (!chr) {
char *label = g_strdup_printf("imx6.uart%d", i + 1);
chr = qemu_chr_new(label, "null", NULL);
g_free(label);
serial_hds[i] = chr;
}
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
}
object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
serial_table[i].irq));
}
s->gpt.ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
FSL_IMX6_GPT_IRQ));
/* Initialize all EPIT timers */
for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
static const struct {
hwaddr addr;
unsigned int irq;
} epit_table[FSL_IMX6_NUM_EPITS] = {
{ FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
{ FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
};
s->epit[i].ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
epit_table[i].irq));
}
/* Initialize all I2C */
for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
static const struct {
hwaddr addr;
unsigned int irq;
} i2c_table[FSL_IMX6_NUM_I2CS] = {
{ FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
{ FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
{ FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
};
object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
i2c_table[i].irq));
}
/* Initialize all GPIOs */
for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
static const struct {
hwaddr addr;
unsigned int irq_low;
unsigned int irq_high;
} gpio_table[FSL_IMX6_NUM_GPIOS] = {
{
FSL_IMX6_GPIO1_ADDR,
FSL_IMX6_GPIO1_LOW_IRQ,
FSL_IMX6_GPIO1_HIGH_IRQ
},
{
FSL_IMX6_GPIO2_ADDR,
FSL_IMX6_GPIO2_LOW_IRQ,
FSL_IMX6_GPIO2_HIGH_IRQ
},
{
FSL_IMX6_GPIO3_ADDR,
FSL_IMX6_GPIO3_LOW_IRQ,
FSL_IMX6_GPIO3_HIGH_IRQ
},
{
FSL_IMX6_GPIO4_ADDR,
FSL_IMX6_GPIO4_LOW_IRQ,
FSL_IMX6_GPIO4_HIGH_IRQ
},
{
FSL_IMX6_GPIO5_ADDR,
FSL_IMX6_GPIO5_LOW_IRQ,
FSL_IMX6_GPIO5_HIGH_IRQ
},
{
FSL_IMX6_GPIO6_ADDR,
FSL_IMX6_GPIO6_LOW_IRQ,
FSL_IMX6_GPIO6_HIGH_IRQ
},
{
FSL_IMX6_GPIO7_ADDR,
FSL_IMX6_GPIO7_LOW_IRQ,
FSL_IMX6_GPIO7_HIGH_IRQ
},
};
object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel",
&error_abort);
object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
&error_abort);
object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
gpio_table[i].irq_low));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
gpio_table[i].irq_high));
}
/* Initialize all SDHC */
for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
static const struct {
hwaddr addr;
unsigned int irq;
} esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
{ FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
{ FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
{ FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
{ FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
};
object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
esdhc_table[i].irq));
}
/* Initialize all ECSPI */
for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
static const struct {
hwaddr addr;
unsigned int irq;
} spi_table[FSL_IMX6_NUM_ECSPIS] = {
{ FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
{ FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
{ FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
{ FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
{ FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
};
/* Initialize the SPI */
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
spi_table[i].irq));
}
/* ROM memory */
memory_region_init_rom_device(&s->rom, NULL, NULL, NULL, "imx6.rom",
FSL_IMX6_ROM_SIZE, &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
&s->rom);
/* CAAM memory */
memory_region_init_rom_device(&s->caam, NULL, NULL, NULL, "imx6.caam",
FSL_IMX6_CAAM_MEM_SIZE, &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
&s->caam);
/* OCRAM memory */
memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
&err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
&s->ocram);
vmstate_register_ram_global(&s->ocram);
/* internal OCRAM (256 KB) is aliased over 1 MB */
memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias",
&s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
&s->ocram_alias);
}
static void fsl_imx6_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = fsl_imx6_realize;
/*
* Reason: creates an ARM CPU, thus use after free(), see
* arm_cpu_class_init()
*/
dc->cannot_destroy_with_object_finalize_yet = true;
dc->desc = "i.MX6 SOC";
}
static const TypeInfo fsl_imx6_type_info = {
.name = TYPE_FSL_IMX6,
.parent = TYPE_DEVICE,
.instance_size = sizeof(FslIMX6State),
.instance_init = fsl_imx6_init,
.class_init = fsl_imx6_class_init,
};
static void fsl_imx6_register_types(void)
{
type_register_static(&fsl_imx6_type_info);
}
type_init(fsl_imx6_register_types)
hw/arm/highbank.c
+5 -7
View File
@@ -168,23 +168,20 @@ static void highbank_regs_reset(DeviceState *dev)
s->regs[0x43] = 0x05F40121;
}
static int highbank_regs_init(SysBusDevice *dev)
static void highbank_regs_init(Object *obj)
{
HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
"highbank_regs", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static void highbank_regs_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
sbc->init = highbank_regs_init;
dc->desc = "Calxeda Highbank registers";
dc->vmsd = &vmstate_highbank_regs;
dc->reset = highbank_regs_reset;
@@ -194,6 +191,7 @@ static const TypeInfo highbank_regs_info = {
.name = TYPE_HIGHBANK_REGISTERS,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(HighbankRegsState),
.instance_init = highbank_regs_init,
.class_init = highbank_regs_class_init,
};
hw/arm/integratorcp.c
+12 -20
View File
@@ -242,9 +242,10 @@ static const MemoryRegionOps integratorcm_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int integratorcm_init(SysBusDevice *dev)
static void integratorcm_init(Object *obj)
{
IntegratorCMState *s = INTEGRATOR_CM(dev);
IntegratorCMState *s = INTEGRATOR_CM(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
s->cm_osc = 0x01000048;
/* ??? What should the high bits of this value be? */
@@ -269,17 +270,16 @@ static int integratorcm_init(SysBusDevice *dev)
s->cm_init = 0x00000112;
s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
1000);
memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000,
memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000,
&error_fatal);
vmstate_register_ram_global(&s->flash);
memory_region_init_io(&s->iomem, OBJECT(s), &integratorcm_ops, s,
memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s,
"integratorcm", 0x00800000);
sysbus_init_mmio(dev, &s->iomem);
integratorcm_do_remap(s);
/* ??? Save/restore. */
return 0;
}
/* Integrator/CP hardware emulation. */
@@ -394,18 +394,18 @@ static const MemoryRegionOps icp_pic_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int icp_pic_init(SysBusDevice *sbd)
static void icp_pic_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
icp_pic_state *s = INTEGRATOR_PIC(dev);
DeviceState *dev = DEVICE(obj);
icp_pic_state *s = INTEGRATOR_PIC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
sysbus_init_irq(sbd, &s->parent_irq);
sysbus_init_irq(sbd, &s->parent_fiq);
memory_region_init_io(&s->iomem, OBJECT(s), &icp_pic_ops, s,
memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s,
"icp-pic", 0x00800000);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
/* CP control registers. */
@@ -630,9 +630,7 @@ static Property core_properties[] = {
static void core_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = integratorcm_init;
dc->props = core_properties;
}
@@ -640,21 +638,15 @@ static const TypeInfo core_info = {
.name = TYPE_INTEGRATOR_CM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IntegratorCMState),
.instance_init = integratorcm_init,
.class_init = core_class_init,
};
static void icp_pic_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
sdc->init = icp_pic_init;
}
static const TypeInfo icp_pic_info = {
.name = TYPE_INTEGRATOR_PIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(icp_pic_state),
.class_init = icp_pic_class_init,
.instance_init = icp_pic_init,
};
static const TypeInfo icp_ctrl_regs_info = {
hw/arm/nseries.c
+2 -1
View File
@@ -1364,7 +1364,7 @@ static void n8x0_init(MachineState *machine,
if (option_rom[0].name &&
(machine->boot_order[0] == 'n' || !machine->kernel_filename)) {
uint8_t nolo_tags[0x10000];
uint8_t *nolo_tags = g_new(uint8_t, 0x10000);
/* No, wait, better start at the ROM. */
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
@@ -1383,6 +1383,7 @@ static void n8x0_init(MachineState *machine,
n800_setup_nolo_tags(nolo_tags);
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
g_free(nolo_tags);
}
}
hw/arm/pxa2xx.c
+11 -15
View File
@@ -1107,9 +1107,10 @@ static const MemoryRegionOps pxa2xx_rtc_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pxa2xx_rtc_init(SysBusDevice *dev)
static void pxa2xx_rtc_init(Object *obj)
{
PXA2xxRTCState *s = PXA2XX_RTC(dev);
PXA2xxRTCState *s = PXA2XX_RTC(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
struct tm tm;
int wom;
@@ -1138,11 +1139,9 @@ static int pxa2xx_rtc_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->rtc_irq);
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s,
memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s,
"pxa2xx-rtc", 0x10000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static void pxa2xx_rtc_pre_save(void *opaque)
@@ -1195,9 +1194,7 @@ static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pxa2xx_rtc_init;
dc->desc = "PXA2xx RTC Controller";
dc->vmsd = &vmstate_pxa2xx_rtc_regs;
}
@@ -1206,6 +1203,7 @@ static const TypeInfo pxa2xx_rtc_sysbus_info = {
.name = TYPE_PXA2XX_RTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxRTCState),
.instance_init = pxa2xx_rtc_init,
.class_init = pxa2xx_rtc_sysbus_class_init,
};
@@ -1501,19 +1499,18 @@ PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
return s;
}
static int pxa2xx_i2c_initfn(SysBusDevice *sbd)
static void pxa2xx_i2c_initfn(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
PXA2xxI2CState *s = PXA2XX_I2C(dev);
DeviceState *dev = DEVICE(obj);
PXA2xxI2CState *s = PXA2XX_I2C(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
s->bus = i2c_init_bus(dev, "i2c");
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s,
memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s,
"pxa2xx-i2c", s->region_size);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
return 0;
}
I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
@@ -1530,9 +1527,7 @@ static Property pxa2xx_i2c_properties[] = {
static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pxa2xx_i2c_initfn;
dc->desc = "PXA2xx I2C Bus Controller";
dc->vmsd = &vmstate_pxa2xx_i2c;
dc->props = pxa2xx_i2c_properties;
@@ -1542,6 +1537,7 @@ static const TypeInfo pxa2xx_i2c_info = {
.name = TYPE_PXA2XX_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxI2CState),
.instance_init = pxa2xx_i2c_initfn,
.class_init = pxa2xx_i2c_class_init,
};
hw/arm/pxa2xx_pic.c
-7
View File
@@ -310,17 +310,10 @@ static VMStateDescription vmstate_pxa2xx_pic_regs = {
},
};
static int pxa2xx_pic_initfn(SysBusDevice *dev)
{
return 0;
}
static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pxa2xx_pic_initfn;
dc->desc = "PXA2xx PIC";
dc->vmsd = &vmstate_pxa2xx_pic_regs;
}
hw/arm/sabrelite.c
+121
View File
@@ -0,0 +1,121 @@
/*
* SABRELITE Board System emulation.
*
* Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
*
* This code is licensed under the GPL, version 2 or later.
* See the file `COPYING' in the top level directory.
*
* It (partially) emulates a sabrelite board, with a Freescale
* i.MX6 SoC
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "hw/arm/fsl-imx6.h"
#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
#include "sysemu/qtest.h"
typedef struct IMX6Sabrelite {
FslIMX6State soc;
MemoryRegion ram;
} IMX6Sabrelite;
static struct arm_boot_info sabrelite_binfo = {
/* DDR memory start */
.loader_start = FSL_IMX6_MMDC_ADDR,
/* No board ID, we boot from DT tree */
.board_id = -1,
};
/* No need to do any particular setup for secondary boot */
static void sabrelite_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info)
{
}
/* Secondary cores are reset through SRC device */
static void sabrelite_reset_secondary(ARMCPU *cpu,
const struct arm_boot_info *info)
{
}
static void sabrelite_init(MachineState *machine)
{
IMX6Sabrelite *s = g_new0(IMX6Sabrelite, 1);
Error *err = NULL;
/* Check the amount of memory is compatible with the SOC */
if (machine->ram_size > FSL_IMX6_MMDC_SIZE) {
error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
machine->ram_size, FSL_IMX6_MMDC_SIZE);
exit(1);
}
object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX6);
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
&error_abort);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
if (err != NULL) {
error_report("%s", error_get_pretty(err));
exit(1);
}
memory_region_allocate_system_memory(&s->ram, NULL, "sabrelite.ram",
machine->ram_size);
memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
&s->ram);
{
/*
* TODO: Ideally we would expose the chip select and spi bus on the
* SoC object using alias properties; then we would not need to
* directly access the underlying spi device object.
*/
/* Add the sst25vf016b NOR FLASH memory to first SPI */
Object *spi_dev;
spi_dev = object_resolve_path_component(OBJECT(&s->soc), "spi1");
if (spi_dev) {
SSIBus *spi_bus;
spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi");
if (spi_bus) {
DeviceState *flash_dev;
flash_dev = ssi_create_slave(spi_bus, "sst25vf016b");
if (flash_dev) {
qemu_irq cs_line = qdev_get_gpio_in_named(flash_dev,
SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
}
}
}
}
sabrelite_binfo.ram_size = machine->ram_size;
sabrelite_binfo.kernel_filename = machine->kernel_filename;
sabrelite_binfo.kernel_cmdline = machine->kernel_cmdline;
sabrelite_binfo.initrd_filename = machine->initrd_filename;
sabrelite_binfo.nb_cpus = smp_cpus;
sabrelite_binfo.secure_boot = true;
sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
if (!qtest_enabled()) {
arm_load_kernel(&s->soc.cpu[0], &sabrelite_binfo);
}
}
static void sabrelite_machine_init(MachineClass *mc)
{
mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)";
mc->init = sabrelite_init;
mc->max_cpus = FSL_IMX6_NUM_CPUS;
}
DEFINE_MACHINE("sabrelite", sabrelite_machine_init)
hw/arm/spitz.c
+9 -14
View File
@@ -164,9 +164,10 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE);
}
static int sl_nand_init(SysBusDevice *dev)
static void sl_nand_init(Object *obj)
{
SLNANDState *s = SL_NAND(dev);
SLNANDState *s = SL_NAND(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
DriveInfo *nand;
s->ctl = 0;
@@ -175,10 +176,8 @@ static int sl_nand_init(SysBusDevice *dev)
s->nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
s->manf_id, s->chip_id);
memory_region_init_io(&s->iomem, OBJECT(s), &sl_ops, s, "sl", 0x40);
memory_region_init_io(&s->iomem, obj, &sl_ops, s, "sl", 0x40);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
/* Spitz Keyboard */
@@ -501,10 +500,10 @@ static void spitz_keyboard_register(PXA2xxState *cpu)
qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
}
static int spitz_keyboard_init(SysBusDevice *sbd)
static void spitz_keyboard_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
SpitzKeyboardState *s = SPITZ_KEYBOARD(dev);
DeviceState *dev = DEVICE(obj);
SpitzKeyboardState *s = SPITZ_KEYBOARD(obj);
int i, j;
for (i = 0; i < 0x80; i ++)
@@ -519,8 +518,6 @@ static int spitz_keyboard_init(SysBusDevice *sbd)
s->kbdtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, spitz_keyboard_tick, s);
qdev_init_gpio_in(dev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
qdev_init_gpio_out(dev, s->sense, SPITZ_KEY_SENSE_NUM);
return 0;
}
/* LCD backlight controller */
@@ -1065,9 +1062,7 @@ static Property sl_nand_properties[] = {
static void sl_nand_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = sl_nand_init;
dc->vmsd = &vmstate_sl_nand_info;
dc->props = sl_nand_properties;
/* Reason: init() method uses drive_get() */
@@ -1078,6 +1073,7 @@ static const TypeInfo sl_nand_info = {
.name = TYPE_SL_NAND,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SLNANDState),
.instance_init = sl_nand_init,
.class_init = sl_nand_class_init,
};
@@ -1097,9 +1093,7 @@ static VMStateDescription vmstate_spitz_kbd = {
static void spitz_keyboard_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = spitz_keyboard_init;
dc->vmsd = &vmstate_spitz_kbd;
}
@@ -1107,6 +1101,7 @@ static const TypeInfo spitz_keyboard_info = {
.name = TYPE_SPITZ_KEYBOARD,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SpitzKeyboardState),
.instance_init = spitz_keyboard_init,
.class_init = spitz_keyboard_class_init,
};
hw/arm/stellaris.c
+24 -24
View File
@@ -316,23 +316,22 @@ static const VMStateDescription vmstate_stellaris_gptm = {
}
};
static int stellaris_gptm_init(SysBusDevice *sbd)
static void stellaris_gptm_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
gptm_state *s = STELLARIS_GPTM(dev);
DeviceState *dev = DEVICE(obj);
gptm_state *s = STELLARIS_GPTM(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_out(dev, &s->trigger, 1);
memory_region_init_io(&s->iomem, OBJECT(s), &gptm_ops, s,
memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
"gptm", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
s->opaque[0] = s->opaque[1] = s;
s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
vmstate_register(dev, -1, &vmstate_stellaris_gptm, s);
return 0;
}
@@ -873,23 +872,22 @@ static const VMStateDescription vmstate_stellaris_i2c = {
}
};
static int stellaris_i2c_init(SysBusDevice *sbd)
static void stellaris_i2c_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
stellaris_i2c_state *s = STELLARIS_I2C(dev);
DeviceState *dev = DEVICE(obj);
stellaris_i2c_state *s = STELLARIS_I2C(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
I2CBus *bus;
sysbus_init_irq(sbd, &s->irq);
bus = i2c_init_bus(dev, "i2c");
s->bus = bus;
memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_i2c_ops, s,
memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
"i2c", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
/* ??? For now we only implement the master interface. */
stellaris_i2c_reset(s);
vmstate_register(dev, -1, &vmstate_stellaris_i2c, s);
return 0;
}
/* Analogue to Digital Converter. This is only partially implemented,
@@ -1160,23 +1158,22 @@ static const VMStateDescription vmstate_stellaris_adc = {
}
};
static int stellaris_adc_init(SysBusDevice *sbd)
static void stellaris_adc_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
stellaris_adc_state *s = STELLARIS_ADC(dev);
DeviceState *dev = DEVICE(obj);
stellaris_adc_state *s = STELLARIS_ADC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
int n;
for (n = 0; n < 4; n++) {
sysbus_init_irq(sbd, &s->irq[n]);
}
memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_adc_ops, s,
memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
"adc", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
stellaris_adc_reset(s);
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
vmstate_register(dev, -1, &vmstate_stellaris_adc, s);
return 0;
}
static
@@ -1425,43 +1422,46 @@ type_init(stellaris_machine_init)
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
sdc->init = stellaris_i2c_init;
dc->vmsd = &vmstate_stellaris_i2c;
}
static const TypeInfo stellaris_i2c_info = {
.name = TYPE_STELLARIS_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(stellaris_i2c_state),
.instance_init = stellaris_i2c_init,
.class_init = stellaris_i2c_class_init,
};
static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
sdc->init = stellaris_gptm_init;
dc->vmsd = &vmstate_stellaris_gptm;
}
static const TypeInfo stellaris_gptm_info = {
.name = TYPE_STELLARIS_GPTM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(gptm_state),
.instance_init = stellaris_gptm_init,
.class_init = stellaris_gptm_class_init,
};
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
sdc->init = stellaris_adc_init;
dc->vmsd = &vmstate_stellaris_adc;
}
static const TypeInfo stellaris_adc_info = {
.name = TYPE_STELLARIS_ADC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(stellaris_adc_state),
.instance_init = stellaris_adc_init,
.class_init = stellaris_adc_class_init,
};
hw/arm/strongarm.c
+28 -38
View File
@@ -179,19 +179,18 @@ static const MemoryRegionOps strongarm_pic_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int strongarm_pic_initfn(SysBusDevice *sbd)
static void strongarm_pic_initfn(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
StrongARMPICState *s = STRONGARM_PIC(dev);
DeviceState *dev = DEVICE(obj);
StrongARMPICState *s = STRONGARM_PIC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s,
memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s,
"pic", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
sysbus_init_irq(sbd, &s->fiq);
return 0;
}
static int strongarm_pic_post_load(void *opaque, int version_id)
@@ -217,9 +216,7 @@ static VMStateDescription vmstate_strongarm_pic_regs = {
static void strongarm_pic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = strongarm_pic_initfn;
dc->desc = "StrongARM PIC";
dc->vmsd = &vmstate_strongarm_pic_regs;
}
@@ -228,6 +225,7 @@ static const TypeInfo strongarm_pic_info = {
.name = TYPE_STRONGARM_PIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMPICState),
.instance_init = strongarm_pic_initfn,
.class_init = strongarm_pic_class_init,
};
@@ -381,9 +379,10 @@ static const MemoryRegionOps strongarm_rtc_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int strongarm_rtc_init(SysBusDevice *dev)
static void strongarm_rtc_init(Object *obj)
{
StrongARMRTCState *s = STRONGARM_RTC(dev);
StrongARMRTCState *s = STRONGARM_RTC(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
struct tm tm;
s->rttr = 0x0;
@@ -400,11 +399,9 @@ static int strongarm_rtc_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->rtc_irq);
sysbus_init_irq(dev, &s->rtc_hz_irq);
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s,
memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s,
"rtc", 0x10000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static void strongarm_rtc_pre_save(void *opaque)
@@ -443,9 +440,7 @@ static const VMStateDescription vmstate_strongarm_rtc_regs = {
static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = strongarm_rtc_init;
dc->desc = "StrongARM RTC Controller";
dc->vmsd = &vmstate_strongarm_rtc_regs;
}
@@ -454,6 +449,7 @@ static const TypeInfo strongarm_rtc_sysbus_info = {
.name = TYPE_STRONGARM_RTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMRTCState),
.instance_init = strongarm_rtc_init,
.class_init = strongarm_rtc_sysbus_class_init,
};
@@ -646,16 +642,17 @@ static DeviceState *strongarm_gpio_init(hwaddr base,
return dev;
}
static int strongarm_gpio_initfn(SysBusDevice *sbd)
static void strongarm_gpio_initfn(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
StrongARMGPIOInfo *s = STRONGARM_GPIO(dev);
DeviceState *dev = DEVICE(obj);
StrongARMGPIOInfo *s = STRONGARM_GPIO(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
int i;
qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
qdev_init_gpio_out(dev, s->handler, 28);
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s,
memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s,
"gpio", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
@@ -663,8 +660,6 @@ static int strongarm_gpio_initfn(SysBusDevice *sbd)
sysbus_init_irq(sbd, &s->irqs[i]);
}
sysbus_init_irq(sbd, &s->irqX);
return 0;
}
static const VMStateDescription vmstate_strongarm_gpio_regs = {
@@ -687,9 +682,7 @@ static const VMStateDescription vmstate_strongarm_gpio_regs = {
static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = strongarm_gpio_initfn;
dc->desc = "StrongARM GPIO controller";
dc->vmsd = &vmstate_strongarm_gpio_regs;
}
@@ -698,6 +691,7 @@ static const TypeInfo strongarm_gpio_info = {
.name = TYPE_STRONGARM_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMGPIOInfo),
.instance_init = strongarm_gpio_initfn,
.class_init = strongarm_gpio_class_init,
};
@@ -824,20 +818,19 @@ static const MemoryRegionOps strongarm_ppc_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int strongarm_ppc_init(SysBusDevice *sbd)
static void strongarm_ppc_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
StrongARMPPCInfo *s = STRONGARM_PPC(dev);
DeviceState *dev = DEVICE(obj);
StrongARMPPCInfo *s = STRONGARM_PPC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
qdev_init_gpio_out(dev, s->handler, 22);
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s,
memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s,
"ppc", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
static const VMStateDescription vmstate_strongarm_ppc_regs = {
@@ -859,9 +852,7 @@ static const VMStateDescription vmstate_strongarm_ppc_regs = {
static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = strongarm_ppc_init;
dc->desc = "StrongARM PPC controller";
dc->vmsd = &vmstate_strongarm_ppc_regs;
}
@@ -870,6 +861,7 @@ static const TypeInfo strongarm_ppc_info = {
.name = TYPE_STRONGARM_PPC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMPPCInfo),
.instance_init = strongarm_ppc_init,
.class_init = strongarm_ppc_class_init,
};
@@ -1231,11 +1223,12 @@ static const MemoryRegionOps strongarm_uart_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int strongarm_uart_init(SysBusDevice *dev)
static void strongarm_uart_init(Object *obj)
{
StrongARMUARTState *s = STRONGARM_UART(dev);
StrongARMUARTState *s = STRONGARM_UART(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s,
memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s,
"uart", 0x10000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
@@ -1250,8 +1243,6 @@ static int strongarm_uart_init(SysBusDevice *dev)
strongarm_uart_event,
s);
}
return 0;
}
static void strongarm_uart_reset(DeviceState *dev)
@@ -1321,9 +1312,7 @@ static Property strongarm_uart_properties[] = {
static void strongarm_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = strongarm_uart_init;
dc->desc = "StrongARM UART controller";
dc->reset = strongarm_uart_reset;
dc->vmsd = &vmstate_strongarm_uart_regs;
@@ -1334,6 +1323,7 @@ static const TypeInfo strongarm_uart_info = {
.name = TYPE_STRONGARM_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMUARTState),
.instance_init = strongarm_uart_init,
.class_init = strongarm_uart_class_init,
};
hw/arm/versatilepb.c
+6 -7
View File
@@ -153,10 +153,11 @@ static const MemoryRegionOps vpb_sic_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int vpb_sic_init(SysBusDevice *sbd)
static void vpb_sic_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
vpb_sic_state *s = VERSATILE_PB_SIC(dev);
DeviceState *dev = DEVICE(obj);
vpb_sic_state *s = VERSATILE_PB_SIC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
int i;
qdev_init_gpio_in(dev, vpb_sic_set_irq, 32);
@@ -164,10 +165,9 @@ static int vpb_sic_init(SysBusDevice *sbd)
sysbus_init_irq(sbd, &s->parent[i]);
}
s->irq = 31;
memory_region_init_io(&s->iomem, OBJECT(s), &vpb_sic_ops, s,
memory_region_init_io(&s->iomem, obj, &vpb_sic_ops, s,
"vpb-sic", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
/* Board init. */
@@ -427,9 +427,7 @@ type_init(versatile_machine_init)
static void vpb_sic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = vpb_sic_init;
dc->vmsd = &vmstate_vpb_sic;
}
@@ -437,6 +435,7 @@ static const TypeInfo vpb_sic_info = {
.name = TYPE_VERSATILE_PB_SIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(vpb_sic_state),
.instance_init = vpb_sic_init,
.class_init = vpb_sic_class_init,
};
hw/arm/virt-acpi-build.c
+52
View File
@@ -43,6 +43,7 @@
#include "hw/acpi/aml-build.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci.h"
#include "sysemu/numa.h"
#define ARM_SPI_BASE 32
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
@@ -413,6 +414,52 @@ build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
NULL, NULL);
}
static void
build_srat(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
{
AcpiSystemResourceAffinityTable *srat;
AcpiSratProcessorGiccAffinity *core;
AcpiSratMemoryAffinity *numamem;
int i, j, srat_start;
uint64_t mem_base;
uint32_t *cpu_node = g_malloc0(guest_info->smp_cpus * sizeof(uint32_t));
for (i = 0; i < guest_info->smp_cpus; i++) {
for (j = 0; j < nb_numa_nodes; j++) {
if (test_bit(i, numa_info[j].node_cpu)) {
cpu_node[i] = j;
break;
}
}
}
srat_start = table_data->len;
srat = acpi_data_push(table_data, sizeof(*srat));
srat->reserved1 = cpu_to_le32(1);
for (i = 0; i < guest_info->smp_cpus; ++i) {
core = acpi_data_push(table_data, sizeof(*core));
core->type = ACPI_SRAT_PROCESSOR_GICC;
core->length = sizeof(*core);
core->proximity = cpu_to_le32(cpu_node[i]);
core->acpi_processor_uid = cpu_to_le32(i);
core->flags = cpu_to_le32(1);
}
g_free(cpu_node);
mem_base = guest_info->memmap[VIRT_MEM].base;
for (i = 0; i < nb_numa_nodes; ++i) {
numamem = acpi_data_push(table_data, sizeof(*numamem));
build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
MEM_AFFINITY_ENABLED);
mem_base += numa_info[i].node_mem;
}
build_header(linker, table_data,
(void *)(table_data->data + srat_start), "SRAT",
table_data->len - srat_start, 3, NULL, NULL);
}
static void
build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
{
@@ -638,6 +685,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_spcr(tables_blob, tables->linker, guest_info);
if (nb_numa_nodes > 0) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker, guest_info);
}
/* RSDT is pointed to by RSDP */
rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
hw/arm/virt.c
+8
View File
@@ -38,6 +38,7 @@
#include "net/net.h"
#include "sysemu/block-backend.h"
#include "sysemu/device_tree.h"
#include "sysemu/numa.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "hw/boards.h"
@@ -329,6 +330,7 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
{
int cpu;
int addr_cells = 1;
unsigned int i;
/*
* From Documentation/devicetree/bindings/arm/cpus.txt
@@ -378,6 +380,12 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
armcpu->mp_affinity);
}
for (i = 0; i < nb_numa_nodes; i++) {
if (test_bit(cpu, numa_info[i].node_cpu)) {
qemu_fdt_setprop_cell(vbi->fdt, nodename, "numa-node-id", i);
}
}
g_free(nodename);
}
}
hw/display/blizzard.c
+81 -39
View File
@@ -925,16 +925,83 @@ static void blizzard_update_display(void *opaque)
s->my[1] = 0;
}
#define DEPTH 8
#include "blizzard_template.h"
#define DEPTH 15
#include "blizzard_template.h"
#define DEPTH 16
#include "blizzard_template.h"
#define DEPTH 24
#include "blizzard_template.h"
#define DEPTH 32
#include "blizzard_template.h"
static void blizzard_draw_line16_32(uint32_t *dest,
const uint16_t *src, unsigned int width)
{
uint16_t data;
unsigned int r, g, b;
const uint16_t *end = (const void *) src + width;
while (src < end) {
data = *src ++;
b = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x3f) << 2;
data >>= 6;
r = (data & 0x1f) << 3;
data >>= 5;
*dest++ = rgb_to_pixel32(r, g, b);
}
}
static void blizzard_draw_line24mode1_32(uint32_t *dest,
const uint8_t *src, unsigned int width)
{
/* TODO: check if SDL 24-bit planes are not in the same format and
* if so, use memcpy */
unsigned int r[2], g[2], b[2];
const uint8_t *end = src + width;
while (src < end) {
g[0] = *src ++;
r[0] = *src ++;
r[1] = *src ++;
b[0] = *src ++;
*dest++ = rgb_to_pixel32(r[0], g[0], b[0]);
b[1] = *src ++;
g[1] = *src ++;
*dest++ = rgb_to_pixel32(r[1], g[1], b[1]);
}
}
static void blizzard_draw_line24mode2_32(uint32_t *dest,
const uint8_t *src, unsigned int width)
{
unsigned int r, g, b;
const uint8_t *end = src + width;
while (src < end) {
r = *src ++;
src ++;
b = *src ++;
g = *src ++;
*dest++ = rgb_to_pixel32(r, g, b);
}
}
/* No rotation */
static blizzard_fn_t blizzard_draw_fn_32[0x10] = {
NULL,
/* RGB 5:6:5*/
(blizzard_fn_t) blizzard_draw_line16_32,
/* RGB 6:6:6 mode 1 */
(blizzard_fn_t) blizzard_draw_line24mode1_32,
/* RGB 8:8:8 mode 1 */
(blizzard_fn_t) blizzard_draw_line24mode1_32,
NULL, NULL,
/* RGB 6:6:6 mode 2 */
(blizzard_fn_t) blizzard_draw_line24mode2_32,
/* RGB 8:8:8 mode 2 */
(blizzard_fn_t) blizzard_draw_line24mode2_32,
/* YUV 4:2:2 */
NULL,
/* YUV 4:2:0 */
NULL,
NULL, NULL, NULL, NULL, NULL, NULL,
};
/* 90deg, 180deg and 270deg rotation */
static blizzard_fn_t blizzard_draw_fn_r_32[0x10] = {
/* TODO */
[0 ... 0xf] = NULL,
};
static const GraphicHwOps blizzard_ops = {
.invalidate = blizzard_invalidate_display,
@@ -951,35 +1018,10 @@ void *s1d13745_init(qemu_irq gpio_int)
s->con = graphic_console_init(NULL, 0, &blizzard_ops, s);
surface = qemu_console_surface(s->con);
switch (surface_bits_per_pixel(surface)) {
case 0:
s->line_fn_tab[0] = s->line_fn_tab[1] =
g_malloc0(sizeof(blizzard_fn_t) * 0x10);
break;
case 8:
s->line_fn_tab[0] = blizzard_draw_fn_8;
s->line_fn_tab[1] = blizzard_draw_fn_r_8;
break;
case 15:
s->line_fn_tab[0] = blizzard_draw_fn_15;
s->line_fn_tab[1] = blizzard_draw_fn_r_15;
break;
case 16:
s->line_fn_tab[0] = blizzard_draw_fn_16;
s->line_fn_tab[1] = blizzard_draw_fn_r_16;
break;
case 24:
s->line_fn_tab[0] = blizzard_draw_fn_24;
s->line_fn_tab[1] = blizzard_draw_fn_r_24;
break;
case 32:
s->line_fn_tab[0] = blizzard_draw_fn_32;
s->line_fn_tab[1] = blizzard_draw_fn_r_32;
break;
default:
fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
exit(1);
}
assert(surface_bits_per_pixel(surface) == 32);
s->line_fn_tab[0] = blizzard_draw_fn_32;
s->line_fn_tab[1] = blizzard_draw_fn_r_32;
blizzard_reset(s);
hw/display/blizzard_template.h
-146
View File
@@ -1,146 +0,0 @@
/*
* QEMU Epson S1D13744/S1D13745 templates
*
* Copyright (C) 2008 Nokia Corporation
* Written by Andrzej Zaborowski <andrew@openedhand.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#define SKIP_PIXEL(to) (to += deststep)
#if DEPTH == 8
# define PIXEL_TYPE uint8_t
# define COPY_PIXEL(to, from) do { *to = from; SKIP_PIXEL(to); } while (0)
# define COPY_PIXEL1(to, from) (*to++ = from)
#elif DEPTH == 15 || DEPTH == 16
# define PIXEL_TYPE uint16_t
# define COPY_PIXEL(to, from) do { *to = from; SKIP_PIXEL(to); } while (0)
# define COPY_PIXEL1(to, from) (*to++ = from)
#elif DEPTH == 24
# define PIXEL_TYPE uint8_t
# define COPY_PIXEL(to, from) \
do { \
to[0] = from; \
to[1] = (from) >> 8; \
to[2] = (from) >> 16; \
SKIP_PIXEL(to); \
} while (0)
# define COPY_PIXEL1(to, from) \
do { \
*to++ = from; \
*to++ = (from) >> 8; \
*to++ = (from) >> 16; \
} while (0)
#elif DEPTH == 32
# define PIXEL_TYPE uint32_t
# define COPY_PIXEL(to, from) do { *to = from; SKIP_PIXEL(to); } while (0)
# define COPY_PIXEL1(to, from) (*to++ = from)
#else
# error unknown bit depth
#endif
#ifdef HOST_WORDS_BIGENDIAN
# define SWAP_WORDS 1
#endif
static void glue(blizzard_draw_line16_, DEPTH)(PIXEL_TYPE *dest,
const uint16_t *src, unsigned int width)
{
#if !defined(SWAP_WORDS) && DEPTH == 16
memcpy(dest, src, width);
#else
uint16_t data;
unsigned int r, g, b;
const uint16_t *end = (const void *) src + width;
while (src < end) {
data = *src ++;
b = (data & 0x1f) << 3;
data >>= 5;
g = (data & 0x3f) << 2;
data >>= 6;
r = (data & 0x1f) << 3;
data >>= 5;
COPY_PIXEL1(dest, glue(rgb_to_pixel, DEPTH)(r, g, b));
}
#endif
}
static void glue(blizzard_draw_line24mode1_, DEPTH)(PIXEL_TYPE *dest,
const uint8_t *src, unsigned int width)
{
/* TODO: check if SDL 24-bit planes are not in the same format and
* if so, use memcpy */
unsigned int r[2], g[2], b[2];
const uint8_t *end = src + width;
while (src < end) {
g[0] = *src ++;
r[0] = *src ++;
r[1] = *src ++;
b[0] = *src ++;
COPY_PIXEL1(dest, glue(rgb_to_pixel, DEPTH)(r[0], g[0], b[0]));
b[1] = *src ++;
g[1] = *src ++;
COPY_PIXEL1(dest, glue(rgb_to_pixel, DEPTH)(r[1], g[1], b[1]));
}
}
static void glue(blizzard_draw_line24mode2_, DEPTH)(PIXEL_TYPE *dest,
const uint8_t *src, unsigned int width)
{
unsigned int r, g, b;
const uint8_t *end = src + width;
while (src < end) {
r = *src ++;
src ++;
b = *src ++;
g = *src ++;
COPY_PIXEL1(dest, glue(rgb_to_pixel, DEPTH)(r, g, b));
}
}
/* No rotation */
static blizzard_fn_t glue(blizzard_draw_fn_, DEPTH)[0x10] = {
NULL,
/* RGB 5:6:5*/
(blizzard_fn_t) glue(blizzard_draw_line16_, DEPTH),
/* RGB 6:6:6 mode 1 */
(blizzard_fn_t) glue(blizzard_draw_line24mode1_, DEPTH),
/* RGB 8:8:8 mode 1 */
(blizzard_fn_t) glue(blizzard_draw_line24mode1_, DEPTH),
NULL, NULL,
/* RGB 6:6:6 mode 2 */
(blizzard_fn_t) glue(blizzard_draw_line24mode2_, DEPTH),
/* RGB 8:8:8 mode 2 */
(blizzard_fn_t) glue(blizzard_draw_line24mode2_, DEPTH),
/* YUV 4:2:2 */
NULL,
/* YUV 4:2:0 */
NULL,
NULL, NULL, NULL, NULL, NULL, NULL,
};
/* 90deg, 180deg and 270deg rotation */
static blizzard_fn_t glue(blizzard_draw_fn_r_, DEPTH)[0x10] = {
/* TODO */
[0 ... 0xf] = NULL,
};
#undef DEPTH
#undef SKIP_PIXEL
#undef COPY_PIXEL
#undef COPY_PIXEL1
#undef PIXEL_TYPE
#undef SWAP_WORDS

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