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hw: Add support for LSI SAS1068 (mptsas) device
This adds the SAS1068 device, a SAS disk controller used in VMware that is oldish but widely supported and has decent performance. Unlike megasas, it presents itself as a SAS controller and not as a RAID controller. The device corresponds to the mptsas kernel driver in Linux. A few small things in the device setup are based on Don Slutz's old patch, but the device emulation was written from scratch based on Don's SeaBIOS patch and on the FreeBSD and Linux drivers. It is 2400 lines shorter than Don's patch (and roughly the same size as MegaSAS---also because it doesn't support the similar SPI controller), implements SCSI task management functions (with asynchronous cancellation), supports big-endian hosts, has complete support for migration and follows the QEMU coding standards much more closely. To write the driver, I first split Don's patch in two parts, with the configuration bits in one file and the rest in a separate file. I first left mptconfig.c in place and rewrote the rest, then deleted mptconfig.c as well. The configuration pages are still based mostly on VirtualBox's, though not exactly the same. However, the implementation is completely different. The contents of the pages themselves should not be copyrightable. Signed-off-by: Don Slutz <Don@CloudSwitch.com> Message-Id: <1347382813-5662-1-git-send-email-Don@CloudSwitch.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
@@ -15,6 +15,7 @@ CONFIG_ES1370=y
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CONFIG_LSI_SCSI_PCI=y
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CONFIG_VMW_PVSCSI_SCSI_PCI=y
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CONFIG_MEGASAS_SCSI_PCI=y
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CONFIG_MPTSAS_SCSI_PCI=y
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CONFIG_RTL8139_PCI=y
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CONFIG_E1000_PCI=y
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CONFIG_VMXNET3_PCI=y
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@@ -1,6 +1,7 @@
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common-obj-y += scsi-disk.o
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common-obj-y += scsi-generic.o scsi-bus.o
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common-obj-$(CONFIG_LSI_SCSI_PCI) += lsi53c895a.o
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common-obj-$(CONFIG_MPTSAS_SCSI_PCI) += mptsas.o mptconfig.o mptendian.o
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common-obj-$(CONFIG_MEGASAS_SCSI_PCI) += megasas.o
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common-obj-$(CONFIG_VMW_PVSCSI_SCSI_PCI) += vmw_pvscsi.o
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common-obj-$(CONFIG_ESP) += esp.o
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+1153
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,204 @@
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/*
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* QEMU LSI SAS1068 Host Bus Adapter emulation
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* Endianness conversion for MPI data structures
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*
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* Copyright (c) 2016 Red Hat, Inc.
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*
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* Authors: Paolo Bonzini <pbonzini@redhat.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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#include "sysemu/dma.h"
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#include "sysemu/block-backend.h"
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#include "hw/pci/msi.h"
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#include "qemu/iov.h"
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#include "hw/scsi/scsi.h"
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#include "block/scsi.h"
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#include "trace.h"
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#include "mptsas.h"
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#include "mpi.h"
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static void mptsas_fix_sgentry_endianness(MPISGEntry *sge)
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{
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le32_to_cpus(&sge->FlagsLength);
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if (sge->FlagsLength & MPI_SGE_FLAGS_64_BIT_ADDRESSING) {
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le64_to_cpus(&sge->u.Address64);
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} else {
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le32_to_cpus(&sge->u.Address32);
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}
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}
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static void mptsas_fix_sgentry_endianness_reply(MPISGEntry *sge)
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{
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if (sge->FlagsLength & MPI_SGE_FLAGS_64_BIT_ADDRESSING) {
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cpu_to_le64s(&sge->u.Address64);
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} else {
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cpu_to_le32s(&sge->u.Address32);
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}
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cpu_to_le32s(&sge->FlagsLength);
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}
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void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req)
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{
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le32_to_cpus(&req->MsgContext);
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le32_to_cpus(&req->Control);
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le32_to_cpus(&req->DataLength);
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le32_to_cpus(&req->SenseBufferLowAddr);
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}
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void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply)
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{
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cpu_to_le32s(&reply->MsgContext);
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cpu_to_le16s(&reply->IOCStatus);
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cpu_to_le32s(&reply->IOCLogInfo);
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cpu_to_le32s(&reply->TransferCount);
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cpu_to_le32s(&reply->SenseCount);
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cpu_to_le32s(&reply->ResponseInfo);
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cpu_to_le16s(&reply->TaskTag);
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}
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void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req)
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{
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le32_to_cpus(&req->MsgContext);
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le32_to_cpus(&req->TaskMsgContext);
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}
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void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply)
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{
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cpu_to_le32s(&reply->MsgContext);
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cpu_to_le16s(&reply->IOCStatus);
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cpu_to_le32s(&reply->IOCLogInfo);
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cpu_to_le32s(&reply->TerminationCount);
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}
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void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req)
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{
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le32_to_cpus(&req->MsgContext);
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le16_to_cpus(&req->ReplyFrameSize);
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le32_to_cpus(&req->HostMfaHighAddr);
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le32_to_cpus(&req->SenseBufferHighAddr);
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le32_to_cpus(&req->ReplyFifoHostSignalingAddr);
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mptsas_fix_sgentry_endianness(&req->HostPageBufferSGE);
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le16_to_cpus(&req->MsgVersion);
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le16_to_cpus(&req->HeaderVersion);
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}
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void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply)
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{
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cpu_to_le32s(&reply->MsgContext);
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cpu_to_le16s(&reply->IOCStatus);
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cpu_to_le32s(&reply->IOCLogInfo);
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}
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void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req)
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{
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le32_to_cpus(&req->MsgContext);
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}
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void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply)
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{
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cpu_to_le16s(&reply->MsgVersion);
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cpu_to_le16s(&reply->HeaderVersion);
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cpu_to_le32s(&reply->MsgContext);
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cpu_to_le16s(&reply->IOCExceptions);
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cpu_to_le16s(&reply->IOCStatus);
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cpu_to_le32s(&reply->IOCLogInfo);
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cpu_to_le16s(&reply->ReplyQueueDepth);
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cpu_to_le16s(&reply->RequestFrameSize);
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cpu_to_le16s(&reply->ProductID);
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cpu_to_le32s(&reply->CurrentHostMfaHighAddr);
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cpu_to_le16s(&reply->GlobalCredits);
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cpu_to_le32s(&reply->CurrentSenseBufferHighAddr);
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cpu_to_le16s(&reply->CurReplyFrameSize);
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cpu_to_le32s(&reply->FWImageSize);
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cpu_to_le32s(&reply->IOCCapabilities);
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cpu_to_le16s(&reply->HighPriorityQueueDepth);
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mptsas_fix_sgentry_endianness_reply(&reply->HostPageBufferSGE);
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cpu_to_le32s(&reply->ReplyFifoHostSignalingAddr);
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}
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void mptsas_fix_config_endianness(MPIMsgConfig *req)
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{
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le16_to_cpus(&req->ExtPageLength);
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le32_to_cpus(&req->MsgContext);
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le32_to_cpus(&req->PageAddress);
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mptsas_fix_sgentry_endianness(&req->PageBufferSGE);
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}
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void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply)
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{
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cpu_to_le16s(&reply->ExtPageLength);
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cpu_to_le32s(&reply->MsgContext);
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cpu_to_le16s(&reply->IOCStatus);
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cpu_to_le32s(&reply->IOCLogInfo);
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}
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void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req)
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{
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le32_to_cpus(&req->MsgContext);
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}
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void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply)
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{
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cpu_to_le32s(&reply->MsgContext);
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cpu_to_le16s(&reply->IOCStatus);
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cpu_to_le32s(&reply->IOCLogInfo);
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cpu_to_le16s(&reply->MaxDevices);
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cpu_to_le16s(&reply->PortSCSIID);
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cpu_to_le16s(&reply->ProtocolFlags);
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cpu_to_le16s(&reply->MaxPostedCmdBuffers);
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cpu_to_le16s(&reply->MaxPersistentIDs);
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cpu_to_le16s(&reply->MaxLanBuckets);
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}
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void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req)
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{
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le32_to_cpus(&req->MsgContext);
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}
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void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply)
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{
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cpu_to_le32s(&reply->MsgContext);
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cpu_to_le16s(&reply->IOCStatus);
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cpu_to_le32s(&reply->IOCLogInfo);
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}
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void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req)
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{
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le32_to_cpus(&req->MsgContext);
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}
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void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply)
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{
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int length = reply->EventDataLength;
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int i;
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cpu_to_le16s(&reply->EventDataLength);
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cpu_to_le32s(&reply->MsgContext);
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cpu_to_le16s(&reply->IOCStatus);
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cpu_to_le32s(&reply->IOCLogInfo);
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cpu_to_le32s(&reply->Event);
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cpu_to_le32s(&reply->EventContext);
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/* Really depends on the event kind. This will do for now. */
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for (i = 0; i < length; i++) {
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cpu_to_le32s(&reply->Data[i]);
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}
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}
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+1441
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,100 @@
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#ifndef MPTSAS_H
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#define MPTSAS_H
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#include "mpi.h"
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#define MPTSAS_NUM_PORTS 8
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#define MPTSAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
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#define MPTSAS_REQUEST_QUEUE_DEPTH 128
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#define MPTSAS_REPLY_QUEUE_DEPTH 128
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#define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22
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typedef struct MPTSASState MPTSASState;
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typedef struct MPTSASRequest MPTSASRequest;
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enum {
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DOORBELL_NONE,
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DOORBELL_WRITE,
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DOORBELL_READ
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};
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struct MPTSASState {
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PCIDevice dev;
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MemoryRegion mmio_io;
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MemoryRegion port_io;
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MemoryRegion diag_io;
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QEMUBH *request_bh;
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uint32_t msi_available;
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uint64_t sas_addr;
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bool msi_in_use;
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/* Doorbell register */
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uint32_t state;
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uint8_t who_init;
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uint8_t doorbell_state;
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/* Buffer for requests that are sent through the doorbell register. */
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uint32_t doorbell_msg[256];
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int doorbell_idx;
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int doorbell_cnt;
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uint16_t doorbell_reply[256];
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int doorbell_reply_idx;
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int doorbell_reply_size;
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/* Other registers */
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uint8_t diagnostic_idx;
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uint32_t diagnostic;
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uint32_t intr_mask;
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uint32_t intr_status;
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/* Request queues */
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uint32_t request_post[MPTSAS_REQUEST_QUEUE_DEPTH + 1];
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uint16_t request_post_head;
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uint16_t request_post_tail;
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uint32_t reply_post[MPTSAS_REPLY_QUEUE_DEPTH + 1];
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uint16_t reply_post_head;
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uint16_t reply_post_tail;
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uint32_t reply_free[MPTSAS_REPLY_QUEUE_DEPTH + 1];
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uint16_t reply_free_head;
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uint16_t reply_free_tail;
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/* IOC Facts */
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hwaddr host_mfa_high_addr;
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hwaddr sense_buffer_high_addr;
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uint16_t max_devices;
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uint16_t max_buses;
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uint16_t reply_frame_size;
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SCSIBus bus;
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QTAILQ_HEAD(, MPTSASRequest) pending;
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};
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void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req);
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void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply);
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void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req);
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void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply);
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void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req);
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void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply);
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void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req);
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void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply);
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void mptsas_fix_config_endianness(MPIMsgConfig *req);
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void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply);
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void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req);
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void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply);
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void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req);
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void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply);
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void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req);
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void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply);
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void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply);
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void mptsas_process_config(MPTSASState *s, MPIMsgConfig *req);
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#endif /* MPTSAS_H */
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@@ -64,6 +64,7 @@
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#define PCI_VENDOR_ID_LSI_LOGIC 0x1000
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#define PCI_DEVICE_ID_LSI_53C810 0x0001
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#define PCI_DEVICE_ID_LSI_53C895A 0x0012
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#define PCI_DEVICE_ID_LSI_SAS1068 0x0054
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#define PCI_DEVICE_ID_LSI_SAS1078 0x0060
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#define PCI_DEVICE_ID_LSI_SAS0079 0x0079
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@@ -726,6 +726,28 @@ lm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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lm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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lm32_uart_irq_state(int level) "irq state %d"
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# hw/scsi/mptsas.c
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mptsas_command_complete(void *dev, uint32_t ctx, uint32_t status, uint32_t resid) "dev %p context 0x%08x status %x resid %d"
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mptsas_diag_read(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%08x"
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mptsas_diag_write(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%08x"
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mptsas_irq_intx(void *dev, int level) "dev %p level %d"
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mptsas_irq_msi(void *dev) "dev %p "
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mptsas_mmio_read(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%x"
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mptsas_mmio_unhandled_read(void *dev, uint32_t addr) "dev %p addr 0x%08x"
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mptsas_mmio_unhandled_write(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%x"
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mptsas_mmio_write(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%x"
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mptsas_process_message(void *dev, int msg, uint32_t ctx) "dev %p cmd %d context 0x%08x\n"
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mptsas_process_scsi_io_request(void *dev, int bus, int target, int lun, uint64_t len) "dev %p dev %d:%d:%d length %"PRIu64""
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mptsas_reset(void *dev) "dev %p "
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mptsas_scsi_overflow(void *dev, uint32_t ctx, uint64_t req, uint64_t found) "dev %p context 0x%08x: %"PRIu64"/%"PRIu64""
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mptsas_sgl_overflow(void *dev, uint32_t ctx, uint64_t req, uint64_t found) "dev %p context 0x%08x: %"PRIu64"/%"PRIu64""
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mptsas_unhandled_cmd(void *dev, uint32_t ctx, uint8_t msg_cmd) "dev %p context 0x%08x: Unhandled cmd %x"
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mptsas_unhandled_doorbell_cmd(void *dev, int cmd) "dev %p value 0x%08x"
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# hw/scsi/mptconfig.c
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mptsas_config_sas_device(void *dev, int address, int port, int phy_handle, int dev_handle, int page) "dev %p address %d (port %d, handles: phy %d dev %d) page %d"
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mptsas_config_sas_phy(void *dev, int address, int port, int phy_handle, int dev_handle, int page) "dev %p address %d (port %d, handles: phy %d dev %d) page %d"
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# hw/scsi/megasas.c
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megasas_init_firmware(uint64_t pa) "pa %" PRIx64 " "
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megasas_init_queue(uint64_t queue_pa, int queue_len, uint64_t head, uint64_t tail, uint32_t flags) "queue at %" PRIx64 " len %d head %" PRIx64 " tail %" PRIx64 " flags %x"
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