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hw/arm/xlnx-versal-virt: tidy up
Remove now unused clock nodes. They have been replaced by the ones created in the SoC. Remove the unused cfg.secure VersalVirt field. Remove unecessary include directives. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-44-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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committed by
Peter Maydell
parent
ea7028b87b
commit
e2e9b9e129
@@ -19,10 +19,8 @@
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#include "hw/boards.h"
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#include "hw/sysbus.h"
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#include "hw/arm/fdt.h"
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#include "hw/qdev-properties.h"
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#include "hw/arm/xlnx-versal.h"
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#include "hw/arm/boot.h"
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#include "target/arm/multiprocessing.h"
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#include "qom/object.h"
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#include "target/arm/cpu.h"
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@@ -41,16 +39,11 @@ struct VersalVirt {
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void *fdt;
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int fdt_size;
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struct {
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uint32_t clk_125Mhz;
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uint32_t clk_25Mhz;
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} phandle;
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struct arm_boot_info binfo;
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CanBusState **canbus;
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struct {
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bool secure;
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char *ospi_model;
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} cfg;
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};
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@@ -72,10 +65,6 @@ static void fdt_create(VersalVirt *s)
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exit(1);
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}
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/* Allocate all phandles. */
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s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
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s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
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/* Create /chosen node for load_dtb. */
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qemu_fdt_add_subnode(s->fdt, "/chosen");
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qemu_fdt_add_subnode(s->fdt, "/aliases");
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@@ -86,17 +75,6 @@ static void fdt_create(VersalVirt *s)
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sizeof(versal_compat));
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}
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static void fdt_add_clk_node(VersalVirt *s, const char *name,
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unsigned int freq_hz, uint32_t phandle)
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{
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
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qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
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qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
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qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
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qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
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}
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static void fdt_nop_memory_nodes(void *fdt, Error **errp)
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{
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Error *err = NULL;
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@@ -268,9 +246,6 @@ static void versal_virt_init(MachineState *machine)
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sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
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create_virtio_regions(s);
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fdt_add_clk_node(s, "/old-clk125", 125000000, s->phandle.clk_125Mhz);
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fdt_add_clk_node(s, "/old-clk25", 25000000, s->phandle.clk_25Mhz);
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/*
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* Map the SoC address space onto system memory. This will allow virtio and
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* other modules unaware of multiple address-spaces to work.
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