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Merge remote-tracking branch 'afaerber-or/qom-cpu-3' into staging

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* afaerber-or/qom-cpu-3: (74 commits)
  Kill off cpu_state_reset()
  linux-user: Use cpu_reset() after cpu_init() / cpu_copy()
  bsd-user: Use cpu_reset() in after cpu_init()
  leon3: Store SPARCCPU in ResetData
  leon3: Use cpu_sparc_init() to obtain SPARCCPU
  sun4u: Store SPARCCPU in ResetData
  sun4u: Let cpu_devinit() return SPARCCPU
  sun4u: Use cpu_sparc_init() to obtain SPARCCPU
  sun4m: Pass SPARCCPU to {main,secondary}_cpu_reset()
  sun4m: Use cpu_sparc_init() to obtain SPARCCPU
  target-sparc: Let cpu_sparc_init() return SPARCCPU
  cpu-exec: Use cpu_reset() in cpu_exec() for TARGET_PPC
  virtex_ml507: Pass PowerPCCPU to main_cpu_reset()
  virtex_ml507: Let ppc440_init_xilinx() return PowerPCCPU
  virtex_ml507: Use cpu_ppc_init() to obtain PowerPCCPU
  ppc_prep: Pass PowerPCCPU to ppc_prep_reset()
  ppc_prep: Use cpu_ppc_init() to obtain PowerPCCPU
  ppc_oldworld: Pass PowerPCCPU to ppc_heathrow_reset()
  ppc_oldworld: Use cpu_ppc_init() to obtain PowerPCCPU
  ppc_newworld: Pass PowerPCCPU to ppc_core99_reset()
  ...
This commit is contained in:
Anthony Liguori
2012-06-06 17:55:07 +08:00
parent 6e72ae4690 b7e516ce04
commit e1ae9a7a78
73 changed files with 516 additions and 389 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsd-user/main.c
+1 -1
View File
@@ -918,7 +918,7 @@ int main(int argc, char **argv)
exit(1);
}
#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
cpu_state_reset(env);
cpu_reset(ENV_GET_CPU(env));
#endif
thread_env = env;
cpu-all.h
-1
View File
@@ -443,7 +443,6 @@ void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
void cpu_single_step(CPUArchState *env, int enabled);
void cpu_state_reset(CPUArchState *s);
int cpu_is_stopped(CPUArchState *env);
void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data);
cpu-exec.c
+6 -3
View File
@@ -184,6 +184,9 @@ volatile sig_atomic_t exit_request;
int cpu_exec(CPUArchState *env)
{
#ifdef TARGET_PPC
CPUState *cpu = ENV_GET_CPU(env);
#endif
int ret, interrupt_request;
TranslationBlock *tb;
uint8_t *tc_ptr;
@@ -287,11 +290,11 @@ int cpu_exec(CPUArchState *env)
#if defined(TARGET_I386)
if (interrupt_request & CPU_INTERRUPT_INIT) {
svm_check_intercept(env, SVM_EXIT_INIT);
do_cpu_init(env);
do_cpu_init(x86_env_get_cpu(env));
env->exception_index = EXCP_HALTED;
cpu_loop_exit(env);
} else if (interrupt_request & CPU_INTERRUPT_SIPI) {
do_cpu_sipi(env);
do_cpu_sipi(x86_env_get_cpu(env));
} else if (env->hflags2 & HF2_GIF_MASK) {
if ((interrupt_request & CPU_INTERRUPT_SMI) &&
!(env->hflags & HF_SMM_MASK)) {
@@ -341,7 +344,7 @@ int cpu_exec(CPUArchState *env)
}
#elif defined(TARGET_PPC)
if ((interrupt_request & CPU_INTERRUPT_RESET)) {
cpu_state_reset(env);
cpu_reset(cpu);
}
if (interrupt_request & CPU_INTERRUPT_HARD) {
ppc_hw_interrupt(env);
hw/arm_boot.c
+6 -3
View File
@@ -274,10 +274,11 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
static void do_cpu_reset(void *opaque)
{
CPUARMState *env = opaque;
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
const struct arm_boot_info *info = env->boot_info;
cpu_state_reset(env);
cpu_reset(CPU(cpu));
if (info) {
if (!info->is_linux) {
/* Jump to the entry point. */
@@ -302,6 +303,7 @@ static void do_cpu_reset(void *opaque)
void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
{
ARMCPU *cpu;
int kernel_size;
int initrd_size;
int n;
@@ -406,7 +408,8 @@ void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
info->is_linux = is_linux;
for (; env; env = env->next_cpu) {
cpu = arm_env_get_cpu(env);
env->boot_info = info;
qemu_register_reset(do_cpu_reset, env);
qemu_register_reset(do_cpu_reset, cpu);
}
}
hw/armv7m.c
+10 -5
View File
@@ -149,7 +149,9 @@ static void armv7m_bitband_init(void)
static void armv7m_reset(void *opaque)
{
cpu_state_reset((CPUARMState *)opaque);
ARMCPU *cpu = opaque;
cpu_reset(CPU(cpu));
}
/* Init CPU and memory for a v7-M based board.
@@ -160,6 +162,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model)
{
ARMCPU *cpu;
CPUARMState *env;
DeviceState *nvic;
/* FIXME: make this local state. */
@@ -177,13 +180,15 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
flash_size *= 1024;
sram_size *= 1024;
if (!cpu_model)
if (cpu_model == NULL) {
cpu_model = "cortex-m3";
env = cpu_init(cpu_model);
if (!env) {
}
cpu = cpu_arm_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
#if 0
/* > 32Mb SRAM gets complicated because it overlaps the bitband area.
@@ -241,7 +246,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
vmstate_register_ram_global(hack);
memory_region_add_subregion(address_space_mem, 0xfffff000, hack);
qemu_register_reset(armv7m_reset, env);
qemu_register_reset(armv7m_reset, cpu);
return pic;
}
hw/axis_dev88.c
+4 -2
View File
@@ -247,6 +247,7 @@ void axisdev88_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CRISCPU *cpu;
CPUCRISState *env;
DeviceState *dev;
SysBusDevice *s;
@@ -263,7 +264,8 @@ void axisdev88_init (ram_addr_t ram_size,
if (cpu_model == NULL) {
cpu_model = "crisv32";
}
env = cpu_init(cpu_model);
cpu = cpu_cris_init(cpu_model);
env = &cpu->env;
/* allocate RAM */
memory_region_init_ram(phys_ram, "axisdev88.ram", ram_size);
@@ -344,7 +346,7 @@ void axisdev88_init (ram_addr_t ram_size,
li.image_filename = kernel_filename;
li.cmdline = kernel_cmdline;
cris_load_image(env, &li);
cris_load_image(cpu, &li);
}
static QEMUMachine axisdev88_machine = {
hw/cris-boot.c
+6 -4
View File
@@ -29,12 +29,13 @@
static void main_cpu_reset(void *opaque)
{
CPUCRISState *env = opaque;
CRISCPU *cpu = opaque;
CPUCRISState *env = &cpu->env;
struct cris_load_info *li;
li = env->load_info;
cpu_state_reset(env);
cpu_reset(CPU(cpu));
if (!li) {
/* nothing more to do. */
@@ -60,8 +61,9 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return addr - 0x80000000LL;
}
void cris_load_image(CPUCRISState *env, struct cris_load_info *li)
void cris_load_image(CRISCPU *cpu, struct cris_load_info *li)
{
CPUCRISState *env = &cpu->env;
uint64_t entry, high;
int kcmdline_len;
int image_size;
@@ -92,5 +94,5 @@ void cris_load_image(CPUCRISState *env, struct cris_load_info *li)
}
pstrcpy_targphys("cmdline", 0x40000000, 256, li->cmdline);
}
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, cpu);
}
hw/cris-boot.h
+1 -1
View File
@@ -8,4 +8,4 @@ struct cris_load_info
target_phys_addr_t entry;
};
void cris_load_image(CPUCRISState *env, struct cris_load_info *li);
void cris_load_image(CRISCPU *cpu, struct cris_load_info *li);
hw/leon3.c
+8 -6
View File
@@ -42,16 +42,16 @@
#define MAX_PILS 16
typedef struct ResetData {
CPUSPARCState *env;
SPARCCPU *cpu;
uint32_t entry; /* save kernel entry in case of reset */
} ResetData;
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
CPUSPARCState *env = s->env;
CPUSPARCState *env = &s->cpu->env;
cpu_state_reset(env);
cpu_reset(CPU(s->cpu));
env->halted = 0;
env->pc = s->entry;
@@ -101,6 +101,7 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
SPARCCPU *cpu;
CPUSPARCState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
@@ -117,17 +118,18 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
cpu_model = "LEON3";
}
env = cpu_init(cpu_model);
if (!env) {
cpu = cpu_sparc_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
exit(1);
}
env = &cpu->env;
cpu_sparc_set_id(env, 0);
/* Reset data */
reset_info = g_malloc0(sizeof(ResetData));
reset_info->env = env;
reset_info->cpu = cpu;
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate IRQ manager */
hw/lm32_boards.c
+11 -7
View File
@@ -31,7 +31,7 @@
#include "exec-memory.h"
typedef struct {
CPULM32State *env;
LM32CPU *cpu;
target_phys_addr_t bootstrap_pc;
target_phys_addr_t flash_base;
target_phys_addr_t hwsetup_base;
@@ -54,9 +54,9 @@ static void cpu_irq_handler(void *opaque, int irq, int level)
static void main_cpu_reset(void *opaque)
{
ResetInfo *reset_info = opaque;
CPULM32State *env = reset_info->env;
CPULM32State *env = &reset_info->cpu->env;
cpu_state_reset(env);
cpu_reset(CPU(reset_info->cpu));
/* init defaults */
env->pc = (uint32_t)reset_info->bootstrap_pc;
@@ -75,6 +75,7 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
LM32CPU *cpu;
CPULM32State *env;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
@@ -101,8 +102,9 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
if (cpu_model == NULL) {
cpu_model = "lm32-full";
}
env = cpu_init(cpu_model);
reset_info->env = env;
cpu = cpu_lm32_init(cpu_model);
env = &cpu->env;
reset_info->cpu = cpu;
reset_info->flash_base = flash_base;
@@ -163,6 +165,7 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
LM32CPU *cpu;
CPULM32State *env;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
@@ -196,8 +199,9 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
if (cpu_model == NULL) {
cpu_model = "lm32-full";
}
env = cpu_init(cpu_model);
reset_info->env = env;
cpu = cpu_lm32_init(cpu_model);
env = &cpu->env;
reset_info->cpu = cpu;
reset_info->flash_base = flash_base;
hw/mainstone.c
+1 -1
View File
@@ -168,7 +168,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
mainstone_binfo.kernel_cmdline = kernel_cmdline;
mainstone_binfo.initrd_filename = initrd_filename;
mainstone_binfo.board_id = arm_id;
arm_load_kernel(cpu->env, &mainstone_binfo);
arm_load_kernel(&cpu->cpu->env, &mainstone_binfo);
}
static void mainstone_init(ram_addr_t ram_size,
hw/microblaze_boot.c
+8 -8
View File
@@ -35,7 +35,7 @@
static struct
{
void (*machine_cpu_reset)(CPUMBState *);
void (*machine_cpu_reset)(MicroBlazeCPU *);
uint32_t bootstrap_pc;
uint32_t cmdline;
uint32_t fdt;
@@ -43,14 +43,15 @@ static struct
static void main_cpu_reset(void *opaque)
{
CPUMBState *env = opaque;
MicroBlazeCPU *cpu = opaque;
CPUMBState *env = &cpu->env;
cpu_state_reset(env);
cpu_reset(CPU(cpu));
env->regs[5] = boot_info.cmdline;
env->regs[7] = boot_info.fdt;
env->sregs[SR_PC] = boot_info.bootstrap_pc;
if (boot_info.machine_cpu_reset) {
boot_info.machine_cpu_reset(env);
boot_info.machine_cpu_reset(cpu);
}
}
@@ -99,11 +100,10 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return addr - 0x30000000LL;
}
void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(CPUMBState *))
void (*machine_cpu_reset)(MicroBlazeCPU *))
{
QemuOpts *machine_opts;
const char *kernel_filename = NULL;
const char *kernel_cmdline = NULL;
@@ -122,7 +122,7 @@ void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
}
boot_info.machine_cpu_reset = machine_cpu_reset;
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, cpu);
if (kernel_filename) {
int kernel_size;
hw/microblaze_boot.h
+2 -2
View File
@@ -3,8 +3,8 @@
#include "hw.h"
void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(CPUMBState *));
void (*machine_cpu_reset)(MicroBlazeCPU *));
#endif /* __MICROBLAZE_BOOT __ */
hw/milkymist.c
+7 -5
View File
@@ -37,7 +37,7 @@
#define KERNEL_LOAD_ADDR 0x40000000
typedef struct {
CPULM32State *env;
LM32CPU *cpu;
target_phys_addr_t bootstrap_pc;
target_phys_addr_t flash_base;
target_phys_addr_t initrd_base;
@@ -59,9 +59,9 @@ static void cpu_irq_handler(void *opaque, int irq, int level)
static void main_cpu_reset(void *opaque)
{
ResetInfo *reset_info = opaque;
CPULM32State *env = reset_info->env;
CPULM32State *env = &reset_info->cpu->env;
cpu_state_reset(env);
cpu_reset(CPU(reset_info->cpu));
/* init defaults */
env->pc = reset_info->bootstrap_pc;
@@ -79,6 +79,7 @@ milkymist_init(ram_addr_t ram_size_not_used,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
LM32CPU *cpu;
CPULM32State *env;
int kernel_size;
DriveInfo *dinfo;
@@ -105,8 +106,9 @@ milkymist_init(ram_addr_t ram_size_not_used,
if (cpu_model == NULL) {
cpu_model = "lm32-full";
}
env = cpu_init(cpu_model);
reset_info->env = env;
cpu = cpu_lm32_init(cpu_model);
env = &cpu->env;
reset_info->cpu = cpu;
cpu_lm32_set_phys_msb_ignore(env, 1);
hw/mips_fulong2e.c
+8 -5
View File
@@ -198,9 +198,10 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_a
static void main_cpu_reset(void *opaque)
{
CPUMIPSState *env = opaque;
MIPSCPU *cpu = opaque;
CPUMIPSState *env = &cpu->env;
cpu_state_reset(env);
cpu_reset(CPU(cpu));
/* TODO: 2E reset stuff */
if (loaderparams.kernel_filename) {
env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
@@ -272,19 +273,21 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
i2c_bus *smbus;
int i;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
MIPSCPU *cpu;
CPUMIPSState *env;
/* init CPUs */
if (cpu_model == NULL) {
cpu_model = "Loongson-2E";
}
env = cpu_init(cpu_model);
if (!env) {
cpu = cpu_mips_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, cpu);
/* fulong 2e has 256M ram. */
ram_size = 256 * 1024 * 1024;
hw/mips_jazz.c
+8 -5
View File
@@ -50,8 +50,9 @@ enum jazz_model_e
static void main_cpu_reset(void *opaque)
{
CPUMIPSState *env = opaque;
cpu_state_reset(env);
MIPSCPU *cpu = opaque;
cpu_reset(CPU(cpu));
}
static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
@@ -112,6 +113,7 @@ static void mips_jazz_init(MemoryRegion *address_space,
{
char *filename;
int bios_size, n;
MIPSCPU *cpu;
CPUMIPSState *env;
qemu_irq *rc4030, *i8259;
rc4030_dma *dmas;
@@ -140,12 +142,13 @@ static void mips_jazz_init(MemoryRegion *address_space,
cpu_model = "24Kf";
#endif
}
env = cpu_init(cpu_model);
if (!env) {
cpu = cpu_mips_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, env);
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
/* allocate RAM */
memory_region_init_ram(ram, "mips_jazz.ram", ram_size);
hw/mips_malta.c
+10 -5
View File
@@ -751,8 +751,10 @@ static void malta_mips_config(CPUMIPSState *env)
static void main_cpu_reset(void *opaque)
{
CPUMIPSState *env = opaque;
cpu_state_reset(env);
MIPSCPU *cpu = opaque;
CPUMIPSState *env = &cpu->env;
cpu_reset(CPU(cpu));
/* The bootloader does not need to be rewritten as it is located in a
read only location. The kernel location and the arguments table
@@ -788,6 +790,7 @@ void mips_malta_init (ram_addr_t ram_size,
int64_t kernel_entry;
PCIBus *pci_bus;
ISABus *isa_bus;
MIPSCPU *cpu;
CPUMIPSState *env;
qemu_irq *isa_irq;
qemu_irq *cpu_exit_irq;
@@ -825,15 +828,17 @@ void mips_malta_init (ram_addr_t ram_size,
}
for (i = 0; i < smp_cpus; i++) {
env = cpu_init(cpu_model);
if (!env) {
cpu = cpu_mips_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
/* Init internal devices */
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, cpu);
}
env = first_cpu;
hw/mips_mipssim.c
+9 -6
View File
@@ -46,7 +46,7 @@ static struct _loaderparams {
} loaderparams;
typedef struct ResetData {
CPUMIPSState *env;
MIPSCPU *cpu;
uint64_t vector;
} ResetData;
@@ -105,9 +105,9 @@ static int64_t load_kernel(void)
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
CPUMIPSState *env = s->env;
CPUMIPSState *env = &s->cpu->env;
cpu_state_reset(env);
cpu_reset(CPU(s->cpu));
env->active_tc.PC = s->vector & ~(target_ulong)1;
if (s->vector & 1) {
env->hflags |= MIPS_HFLAG_M16;
@@ -140,6 +140,7 @@ mips_mipssim_init (ram_addr_t ram_size,
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MIPSCPU *cpu;
CPUMIPSState *env;
ResetData *reset_info;
int bios_size;
@@ -152,13 +153,15 @@ mips_mipssim_init (ram_addr_t ram_size,
cpu_model = "24Kf";
#endif
}
env = cpu_init(cpu_model);
if (!env) {
cpu = cpu_mips_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
reset_info = g_malloc0(sizeof(ResetData));
reset_info->env = env;
reset_info->cpu = cpu;
reset_info->vector = env->active_tc.PC;
qemu_register_reset(main_cpu_reset, reset_info);
hw/mips_r4k.c
+9 -6
View File
@@ -65,7 +65,7 @@ static const MemoryRegionOps mips_qemu_ops = {
};
typedef struct ResetData {
CPUMIPSState *env;
MIPSCPU *cpu;
uint64_t vector;
} ResetData;
@@ -143,9 +143,9 @@ static int64_t load_kernel(void)
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
CPUMIPSState *env = s->env;
CPUMIPSState *env = &s->cpu->env;
cpu_state_reset(env);
cpu_reset(CPU(s->cpu));
env->active_tc.PC = s->vector;
}
@@ -162,6 +162,7 @@ void mips_r4k_init (ram_addr_t ram_size,
MemoryRegion *bios;
MemoryRegion *iomem = g_new(MemoryRegion, 1);
int bios_size;
MIPSCPU *cpu;
CPUMIPSState *env;
ResetData *reset_info;
int i;
@@ -179,13 +180,15 @@ void mips_r4k_init (ram_addr_t ram_size,
cpu_model = "24Kf";
#endif
}
env = cpu_init(cpu_model);
if (!env) {
cpu = cpu_mips_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
reset_info = g_malloc0(sizeof(ResetData));
reset_info->env = env;
reset_info->cpu = cpu;
reset_info->vector = env->active_tc.PC;
qemu_register_reset(main_cpu_reset, reset_info);
hw/nseries.c
+3 -3
View File
@@ -1023,7 +1023,7 @@ static void n8x0_boot_init(void *opaque)
n800_dss_init(&s->blizzard);
/* CPU setup */
s->cpu->env->GE = 0x5;
s->cpu->cpu->env.GE = 0x5;
/* If the machine has a slided keyboard, open it */
if (s->kbd)
@@ -1329,7 +1329,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
binfo->kernel_filename = kernel_filename;
binfo->kernel_cmdline = kernel_cmdline;
binfo->initrd_filename = initrd_filename;
arm_load_kernel(s->cpu->env, binfo);
arm_load_kernel(&s->cpu->cpu->env, binfo);
qemu_register_reset(n8x0_boot_init, s);
}
@@ -1338,7 +1338,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
int rom_size;
uint8_t nolo_tags[0x10000];
/* No, wait, better start at the ROM. */
s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
s->cpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
/* This is intended for loading the `secondary.bin' program from
* Nokia images (the NOLO bootloader). The entry point seems

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