mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200511' into staging
target-arm queue: aspeed: Add boot stub for smp booting target/arm: Drop access_el3_aa32ns_aa64any() aspeed: Support AST2600A1 silicon revision aspeed: sdmc: Implement AST2600 locking behaviour nrf51: Tracing cleanups target/arm: Improve handling of SVE loads and stores target/arm: Don't show TCG-only CPUs in KVM-only QEMU builds hw/arm/musicpal: Map the UART devices unconditionally target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA # gpg: Signature made Mon 11 May 2020 14:33:14 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200511: (34 commits) target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA hw/arm/musicpal: Map the UART devices unconditionally target/arm: Restrict TCG cpus to TCG accel target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[] target/arm: Make set_feature() available for other files target/arm/kvm: Inline set_feature() calls target/arm: Remove sve_memopidx target/arm: Reuse sve_probe_page for gather loads target/arm: Reuse sve_probe_page for scatter stores target/arm: Reuse sve_probe_page for gather first-fault loads target/arm: Use SVEContLdSt for contiguous stores target/arm: Update contiguous first-fault and no-fault loads target/arm: Use SVEContLdSt for multi-register contiguous loads target/arm: Handle watchpoints in sve_ld1_r target/arm: Use SVEContLdSt in sve_ld1_r target/arm: Adjust interface of sve_ld1_host_fn target/arm: Add sve infrastructure for page lookup target/arm: Drop manual handling of set/clear_helper_retaddr ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
+265
-148
File diff suppressed because it is too large
Load Diff
+208
-48
@@ -190,13 +190,12 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
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||||
g_assert_not_reached();
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}
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||||
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||||
void *probe_access(CPUArchState *env, target_ulong addr, int size,
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||||
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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static int probe_access_internal(CPUArchState *env, target_ulong addr,
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int fault_size, MMUAccessType access_type,
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||||
bool nonfault, uintptr_t ra)
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||||
{
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int flags;
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g_assert(-(addr | TARGET_PAGE_MASK) >= size);
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switch (access_type) {
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case MMU_DATA_STORE:
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flags = PAGE_WRITE;
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@@ -211,13 +210,39 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
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g_assert_not_reached();
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}
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if (!guest_addr_valid(addr) || page_check_range(addr, size, flags) < 0) {
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CPUState *cpu = env_cpu(env);
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CPUClass *cc = CPU_GET_CLASS(cpu);
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cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
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retaddr);
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g_assert_not_reached();
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if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
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if (nonfault) {
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return TLB_INVALID_MASK;
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} else {
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CPUState *cpu = env_cpu(env);
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CPUClass *cc = CPU_GET_CLASS(cpu);
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cc->tlb_fill(cpu, addr, fault_size, access_type,
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MMU_USER_IDX, false, ra);
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g_assert_not_reached();
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}
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}
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return 0;
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}
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int probe_access_flags(CPUArchState *env, target_ulong addr,
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MMUAccessType access_type, int mmu_idx,
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bool nonfault, void **phost, uintptr_t ra)
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{
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int flags;
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flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra);
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*phost = flags ? NULL : g2h(addr);
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return flags;
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}
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void *probe_access(CPUArchState *env, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t ra)
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{
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int flags;
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g_assert(-(addr | TARGET_PAGE_MASK) >= size);
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flags = probe_access_internal(env, addr, size, access_type, false, ra);
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g_assert(flags == 0);
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return size ? g2h(addr) : NULL;
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}
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@@ -758,46 +783,90 @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
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return ret;
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}
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uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr)
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uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
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{
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uint32_t ret;
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uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, false);
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uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false);
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trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
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ret = lduw_p(g2h(ptr));
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ret = lduw_be_p(g2h(ptr));
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qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
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return ret;
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}
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int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr)
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int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
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{
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int ret;
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uint16_t meminfo = trace_mem_get_info(MO_TESW, MMU_USER_IDX, false);
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uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false);
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trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
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ret = ldsw_p(g2h(ptr));
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ret = ldsw_be_p(g2h(ptr));
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qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
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return ret;
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}
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uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr)
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uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
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{
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uint32_t ret;
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uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, false);
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uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false);
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trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
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ret = ldl_p(g2h(ptr));
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ret = ldl_be_p(g2h(ptr));
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qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
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return ret;
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}
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uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr)
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uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
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{
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uint64_t ret;
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uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, false);
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||||
uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false);
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trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
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ret = ldq_p(g2h(ptr));
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ret = ldq_be_p(g2h(ptr));
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qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
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return ret;
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}
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uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
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||||
{
|
||||
uint32_t ret;
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uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false);
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trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
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ret = lduw_le_p(g2h(ptr));
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qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
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return ret;
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}
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int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
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||||
{
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||||
int ret;
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uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false);
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||||
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
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ret = ldsw_le_p(g2h(ptr));
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qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
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return ret;
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}
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||||
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
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{
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||||
uint32_t ret;
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uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false);
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trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
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ret = ldl_le_p(g2h(ptr));
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qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
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return ret;
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}
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||||
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||||
uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
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||||
{
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uint64_t ret;
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uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false);
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||||
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||||
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
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||||
ret = ldq_le_p(g2h(ptr));
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qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
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return ret;
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||||
}
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||||
@@ -822,42 +891,82 @@ int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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||||
return ret;
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||||
}
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||||
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uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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||||
{
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||||
uint32_t ret;
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set_helper_retaddr(retaddr);
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ret = cpu_lduw_data(env, ptr);
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ret = cpu_lduw_be_data(env, ptr);
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clear_helper_retaddr();
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return ret;
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}
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int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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||||
{
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int ret;
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set_helper_retaddr(retaddr);
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ret = cpu_ldsw_data(env, ptr);
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ret = cpu_ldsw_be_data(env, ptr);
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clear_helper_retaddr();
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return ret;
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}
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uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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{
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uint32_t ret;
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set_helper_retaddr(retaddr);
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ret = cpu_ldl_data(env, ptr);
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ret = cpu_ldl_be_data(env, ptr);
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clear_helper_retaddr();
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return ret;
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}
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uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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{
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uint64_t ret;
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set_helper_retaddr(retaddr);
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ret = cpu_ldq_data(env, ptr);
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ret = cpu_ldq_be_data(env, ptr);
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clear_helper_retaddr();
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return ret;
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}
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uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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||||
{
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||||
uint32_t ret;
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set_helper_retaddr(retaddr);
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ret = cpu_lduw_le_data(env, ptr);
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||||
clear_helper_retaddr();
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return ret;
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||||
}
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||||
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||||
int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
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||||
{
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||||
int ret;
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||||
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||||
set_helper_retaddr(retaddr);
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ret = cpu_ldsw_le_data(env, ptr);
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clear_helper_retaddr();
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||||
return ret;
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||||
}
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||||
|
||||
uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
|
||||
{
|
||||
uint32_t ret;
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||||
|
||||
set_helper_retaddr(retaddr);
|
||||
ret = cpu_ldl_le_data(env, ptr);
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||||
clear_helper_retaddr();
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||||
return ret;
|
||||
}
|
||||
|
||||
uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
|
||||
{
|
||||
uint64_t ret;
|
||||
|
||||
set_helper_retaddr(retaddr);
|
||||
ret = cpu_ldq_le_data(env, ptr);
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||||
clear_helper_retaddr();
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||||
return ret;
|
||||
}
|
||||
@@ -871,30 +980,57 @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
|
||||
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
|
||||
}
|
||||
|
||||
void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
|
||||
void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
|
||||
{
|
||||
uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, true);
|
||||
uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true);
|
||||
|
||||
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
|
||||
stw_p(g2h(ptr), val);
|
||||
stw_be_p(g2h(ptr), val);
|
||||
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
|
||||
}
|
||||
|
||||
void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
|
||||
void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
|
||||
{
|
||||
uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, true);
|
||||
uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true);
|
||||
|
||||
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
|
||||
stl_p(g2h(ptr), val);
|
||||
stl_be_p(g2h(ptr), val);
|
||||
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
|
||||
}
|
||||
|
||||
void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
|
||||
void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
|
||||
{
|
||||
uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, true);
|
||||
uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true);
|
||||
|
||||
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
|
||||
stq_p(g2h(ptr), val);
|
||||
stq_be_p(g2h(ptr), val);
|
||||
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
|
||||
}
|
||||
|
||||
void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
|
||||
{
|
||||
uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true);
|
||||
|
||||
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
|
||||
stw_le_p(g2h(ptr), val);
|
||||
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
|
||||
}
|
||||
|
||||
void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
|
||||
{
|
||||
uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true);
|
||||
|
||||
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
|
||||
stl_le_p(g2h(ptr), val);
|
||||
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
|
||||
}
|
||||
|
||||
void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
|
||||
{
|
||||
uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true);
|
||||
|
||||
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
|
||||
stq_le_p(g2h(ptr), val);
|
||||
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
|
||||
}
|
||||
|
||||
@@ -906,27 +1042,51 @@ void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t retaddr)
|
||||
void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t retaddr)
|
||||
{
|
||||
set_helper_retaddr(retaddr);
|
||||
cpu_stw_data(env, ptr, val);
|
||||
cpu_stw_be_data(env, ptr, val);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t retaddr)
|
||||
void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t retaddr)
|
||||
{
|
||||
set_helper_retaddr(retaddr);
|
||||
cpu_stl_data(env, ptr, val);
|
||||
cpu_stl_be_data(env, ptr, val);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint64_t val, uintptr_t retaddr)
|
||||
void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint64_t val, uintptr_t retaddr)
|
||||
{
|
||||
set_helper_retaddr(retaddr);
|
||||
cpu_stq_data(env, ptr, val);
|
||||
cpu_stq_be_data(env, ptr, val);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t retaddr)
|
||||
{
|
||||
set_helper_retaddr(retaddr);
|
||||
cpu_stw_le_data(env, ptr, val);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t retaddr)
|
||||
{
|
||||
set_helper_retaddr(retaddr);
|
||||
cpu_stl_le_data(env, ptr, val);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint64_t val, uintptr_t retaddr)
|
||||
{
|
||||
set_helper_retaddr(retaddr);
|
||||
cpu_stq_le_data(env, ptr, val);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
|
||||
+27
-12
@@ -97,9 +97,9 @@ function, which is a return address into the generated code.
|
||||
|
||||
Function names follow the pattern:
|
||||
|
||||
load: ``cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
|
||||
load: ``cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
|
||||
|
||||
store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
|
||||
store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
|
||||
|
||||
``sign``
|
||||
- (empty) : for 32 or 64 bit sizes
|
||||
@@ -112,9 +112,14 @@ store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
|
||||
- ``l`` : 32 bits
|
||||
- ``q`` : 64 bits
|
||||
|
||||
``end``
|
||||
- (empty) : for target endian, or 8 bit sizes
|
||||
- ``_be`` : big endian
|
||||
- ``_le`` : little endian
|
||||
|
||||
Regexes for git grep:
|
||||
- ``\<cpu_ld[us]\?[bwlq]_mmuidx_ra\>``
|
||||
- ``\<cpu_st[bwlq]_mmuidx_ra\>``
|
||||
- ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_mmuidx_ra\>``
|
||||
- ``\<cpu_st[bwlq](_[bl]e)\?_mmuidx_ra\>``
|
||||
|
||||
``cpu_{ld,st}*_data_ra``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
@@ -129,9 +134,9 @@ be performed with a context other than the default.
|
||||
|
||||
Function names follow the pattern:
|
||||
|
||||
load: ``cpu_ld{sign}{size}_data_ra(env, ptr, ra)``
|
||||
load: ``cpu_ld{sign}{size}{end}_data_ra(env, ptr, ra)``
|
||||
|
||||
store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
|
||||
store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
|
||||
|
||||
``sign``
|
||||
- (empty) : for 32 or 64 bit sizes
|
||||
@@ -144,9 +149,14 @@ store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
|
||||
- ``l`` : 32 bits
|
||||
- ``q`` : 64 bits
|
||||
|
||||
``end``
|
||||
- (empty) : for target endian, or 8 bit sizes
|
||||
- ``_be`` : big endian
|
||||
- ``_le`` : little endian
|
||||
|
||||
Regexes for git grep:
|
||||
- ``\<cpu_ld[us]\?[bwlq]_data_ra\>``
|
||||
- ``\<cpu_st[bwlq]_data_ra\>``
|
||||
- ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data_ra\>``
|
||||
- ``\<cpu_st[bwlq](_[bl]e)\?_data_ra\>``
|
||||
|
||||
``cpu_{ld,st}*_data``
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
@@ -163,9 +173,9 @@ the CPU state anyway.
|
||||
|
||||
Function names follow the pattern:
|
||||
|
||||
load: ``cpu_ld{sign}{size}_data(env, ptr)``
|
||||
load: ``cpu_ld{sign}{size}{end}_data(env, ptr)``
|
||||
|
||||
store: ``cpu_st{size}_data(env, ptr, val)``
|
||||
store: ``cpu_st{size}{end}_data(env, ptr, val)``
|
||||
|
||||
``sign``
|
||||
- (empty) : for 32 or 64 bit sizes
|
||||
@@ -178,9 +188,14 @@ store: ``cpu_st{size}_data(env, ptr, val)``
|
||||
- ``l`` : 32 bits
|
||||
- ``q`` : 64 bits
|
||||
|
||||
``end``
|
||||
- (empty) : for target endian, or 8 bit sizes
|
||||
- ``_be`` : big endian
|
||||
- ``_le`` : little endian
|
||||
|
||||
Regexes for git grep
|
||||
- ``\<cpu_ld[us]\?[bwlq]_data\>``
|
||||
- ``\<cpu_st[bwlq]_data\+\>``
|
||||
- ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data\>``
|
||||
- ``\<cpu_st[bwlq](_[bl]e)\?_data\+\>``
|
||||
|
||||
``cpu_ld*_code``
|
||||
~~~~~~~~~~~~~~~~
|
||||
|
||||
@@ -1127,7 +1127,7 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
|
||||
int ret = 0;
|
||||
|
||||
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
|
||||
if (watchpoint_address_matches(wp, addr, TARGET_PAGE_SIZE)) {
|
||||
if (watchpoint_address_matches(wp, addr, len)) {
|
||||
ret |= wp->flags;
|
||||
}
|
||||
}
|
||||
|
||||
+69
-4
@@ -93,7 +93,7 @@ struct AspeedBoardState {
|
||||
|
||||
/* Tacoma hardware value */
|
||||
#define TACOMA_BMC_HW_STRAP1 0x00000000
|
||||
#define TACOMA_BMC_HW_STRAP2 0x00000000
|
||||
#define TACOMA_BMC_HW_STRAP2 0x00000040
|
||||
|
||||
/*
|
||||
* The max ram region is for firmwares that scan the address space
|
||||
@@ -116,6 +116,58 @@ static const MemoryRegionOps max_ram_ops = {
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
};
|
||||
|
||||
#define AST_SMP_MAILBOX_BASE 0x1e6e2180
|
||||
#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
|
||||
#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
|
||||
#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
|
||||
#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
|
||||
#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
|
||||
#define AST_SMP_MBOX_GOSIGN 0xabbaab00
|
||||
|
||||
static void aspeed_write_smpboot(ARMCPU *cpu,
|
||||
const struct arm_boot_info *info)
|
||||
{
|
||||
static const uint32_t poll_mailbox_ready[] = {
|
||||
/*
|
||||
* r2 = per-cpu go sign value
|
||||
* r1 = AST_SMP_MBOX_FIELD_ENTRY
|
||||
* r0 = AST_SMP_MBOX_FIELD_GOSIGN
|
||||
*/
|
||||
0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
|
||||
0xe21000ff, /* ands r0, r0, #255 */
|
||||
0xe59f201c, /* ldr r2, [pc, #28] */
|
||||
0xe1822000, /* orr r2, r2, r0 */
|
||||
|
||||
0xe59f1018, /* ldr r1, [pc, #24] */
|
||||
0xe59f0018, /* ldr r0, [pc, #24] */
|
||||
|
||||
0xe320f002, /* wfe */
|
||||
0xe5904000, /* ldr r4, [r0] */
|
||||
0xe1520004, /* cmp r2, r4 */
|
||||
0x1afffffb, /* bne <wfe> */
|
||||
0xe591f000, /* ldr pc, [r1] */
|
||||
AST_SMP_MBOX_GOSIGN,
|
||||
AST_SMP_MBOX_FIELD_ENTRY,
|
||||
AST_SMP_MBOX_FIELD_GOSIGN,
|
||||
};
|
||||
|
||||
rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
|
||||
sizeof(poll_mailbox_ready),
|
||||
info->smp_loader_start);
|
||||
}
|
||||
|
||||
static void aspeed_reset_secondary(ARMCPU *cpu,
|
||||
const struct arm_boot_info *info)
|
||||
{
|
||||
AddressSpace *as = arm_boot_address_space(cpu, info);
|
||||
CPUState *cs = CPU(cpu);
|
||||
|
||||
/* info->smp_bootreg_addr */
|
||||
address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
|
||||
MEMTXATTRS_UNSPECIFIED, NULL);
|
||||
cpu_set_pc(cs, info->smp_loader_start);
|
||||
}
|
||||
|
||||
#define FIRMWARE_ADDR 0x0
|
||||
|
||||
static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
|
||||
@@ -270,6 +322,19 @@ static void aspeed_machine_init(MachineState *machine)
|
||||
}
|
||||
}
|
||||
|
||||
if (machine->kernel_filename && bmc->soc.num_cpus > 1) {
|
||||
/* With no u-boot we must set up a boot stub for the secondary CPU */
|
||||
MemoryRegion *smpboot = g_new(MemoryRegion, 1);
|
||||
memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot",
|
||||
0x80, &error_abort);
|
||||
memory_region_add_subregion(get_system_memory(),
|
||||
AST_SMP_MAILBOX_BASE, smpboot);
|
||||
|
||||
aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
|
||||
aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
|
||||
aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
|
||||
}
|
||||
|
||||
aspeed_board_binfo.ram_size = ram_size;
|
||||
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
|
||||
aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
|
||||
@@ -520,7 +585,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
|
||||
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
|
||||
amc->soc_name = "ast2600-a0";
|
||||
amc->soc_name = "ast2600-a1";
|
||||
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
|
||||
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
|
||||
amc->fmc_model = "w25q512jv";
|
||||
@@ -535,8 +600,8 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
|
||||
amc->soc_name = "ast2600-a0";
|
||||
mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
|
||||
amc->soc_name = "ast2600-a1";
|
||||
amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
|
||||
amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
|
||||
amc->fmc_model = "mx66l1g45g";
|
||||
|
||||
@@ -557,9 +557,9 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
|
||||
|
||||
dc->realize = aspeed_soc_ast2600_realize;
|
||||
|
||||
sc->name = "ast2600-a0";
|
||||
sc->name = "ast2600-a1";
|
||||
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
|
||||
sc->silicon_rev = AST2600_A0_SILICON_REV;
|
||||
sc->silicon_rev = AST2600_A1_SILICON_REV;
|
||||
sc->sram_size = 0x10000;
|
||||
sc->spis_num = 2;
|
||||
sc->ehcis_num = 2;
|
||||
@@ -571,7 +571,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
|
||||
}
|
||||
|
||||
static const TypeInfo aspeed_soc_ast2600_type_info = {
|
||||
.name = "ast2600-a0",
|
||||
.name = "ast2600-a1",
|
||||
.parent = TYPE_ASPEED_SOC,
|
||||
.instance_size = sizeof(AspeedSoCState),
|
||||
.instance_init = aspeed_soc_ast2600_init,
|
||||
|
||||
+4
-8
@@ -1619,14 +1619,10 @@ static void musicpal_init(MachineState *machine)
|
||||
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
|
||||
pic[MP_TIMER4_IRQ], NULL);
|
||||
|
||||
if (serial_hd(0)) {
|
||||
serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
|
||||
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
|
||||
}
|
||||
if (serial_hd(1)) {
|
||||
serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
|
||||
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
|
||||
}
|
||||
serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
|
||||
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
|
||||
serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
|
||||
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
|
||||
|
||||
/* Register flash */
|
||||
dinfo = drive_get(IF_PFLASH, 0, 0);
|
||||
|
||||
+7
-2
@@ -150,13 +150,18 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
|
||||
|
||||
/* TIMER */
|
||||
for (i = 0; i < NRF51_NUM_TIMERS; i++) {
|
||||
object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err);
|
||||
if (err) {
|
||||
error_propagate(errp, err);
|
||||
return;
|
||||
}
|
||||
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
|
||||
if (err) {
|
||||
error_propagate(errp, err);
|
||||
return;
|
||||
}
|
||||
|
||||
base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE;
|
||||
base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
|
||||
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
|
||||
@@ -166,7 +171,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
|
||||
|
||||
/* STUB Peripherals */
|
||||
memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
|
||||
"nrf51_soc.clock", 0x1000);
|
||||
"nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
|
||||
memory_region_add_subregion_overlap(&s->container,
|
||||
NRF51_IOMEM_BASE, &s->clock, -1);
|
||||
|
||||
|
||||
@@ -100,7 +100,7 @@ static void microbit_i2c_realize(DeviceState *dev, Error **errp)
|
||||
MicrobitI2CState *s = MICROBIT_I2C(dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), µbit_i2c_ops, s,
|
||||
"microbit.twi", NRF51_TWI_SIZE);
|
||||
"microbit.twi", NRF51_PERIPHERAL_SIZE);
|
||||
sysbus_init_mmio(sbd, &s->iomem);
|
||||
}
|
||||
|
||||
|
||||
@@ -431,6 +431,7 @@ static uint32_t aspeed_silicon_revs[] = {
|
||||
AST2500_A0_SILICON_REV,
|
||||
AST2500_A1_SILICON_REV,
|
||||
AST2600_A0_SILICON_REV,
|
||||
AST2600_A1_SILICON_REV,
|
||||
};
|
||||
|
||||
bool is_supported_silicon_rev(uint32_t silicon_rev)
|
||||
@@ -649,12 +650,10 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = {
|
||||
.valid.unaligned = false,
|
||||
};
|
||||
|
||||
static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
|
||||
[AST2600_SILICON_REV] = AST2600_SILICON_REV,
|
||||
[AST2600_SILICON_REV2] = AST2600_SILICON_REV,
|
||||
[AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100,
|
||||
static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
|
||||
[AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
|
||||
[AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
|
||||
[AST2600_CLK_STOP_CTRL] = 0xEFF43E8B,
|
||||
[AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
|
||||
[AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
|
||||
[AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
|
||||
[AST2600_HPLL_PARAM] = 0x1000405F,
|
||||
@@ -684,7 +683,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
|
||||
|
||||
dc->desc = "ASPEED 2600 System Control Unit";
|
||||
dc->reset = aspeed_ast2600_scu_reset;
|
||||
asc->resets = ast2600_a0_resets;
|
||||
asc->resets = ast2600_a1_resets;
|
||||
asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
|
||||
asc->apb_divider = 4;
|
||||
asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
|
||||
|
||||
+45
-10
@@ -23,7 +23,12 @@
|
||||
|
||||
/* Protection Key Register */
|
||||
#define R_PROT (0x00 / 4)
|
||||
#define PROT_UNLOCKED 0x01
|
||||
#define PROT_HARDLOCKED 0x10 /* AST2600 */
|
||||
#define PROT_SOFTLOCKED 0x00
|
||||
|
||||
#define PROT_KEY_UNLOCK 0xFC600309
|
||||
#define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
|
||||
|
||||
/* Configuration Register */
|
||||
#define R_CONF (0x04 / 4)
|
||||
@@ -130,16 +135,6 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
|
||||
return;
|
||||
}
|
||||
|
||||
if (addr == R_PROT) {
|
||||
s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if (!s->regs[R_PROT]) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
asc->write(s, addr, data);
|
||||
}
|
||||
|
||||
@@ -320,6 +315,16 @@ static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
|
||||
static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
|
||||
uint32_t data)
|
||||
{
|
||||
if (reg == R_PROT) {
|
||||
s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
|
||||
return;
|
||||
}
|
||||
|
||||
if (!s->regs[R_PROT]) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
switch (reg) {
|
||||
case R_CONF:
|
||||
data = aspeed_2400_sdmc_compute_conf(s, data);
|
||||
@@ -368,6 +373,16 @@ static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
|
||||
static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
|
||||
uint32_t data)
|
||||
{
|
||||
if (reg == R_PROT) {
|
||||
s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
|
||||
return;
|
||||
}
|
||||
|
||||
if (!s->regs[R_PROT]) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
switch (reg) {
|
||||
case R_CONF:
|
||||
data = aspeed_2500_sdmc_compute_conf(s, data);
|
||||
@@ -424,7 +439,27 @@ static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
|
||||
static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
|
||||
uint32_t data)
|
||||
{
|
||||
if (s->regs[R_PROT] == PROT_HARDLOCKED) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
switch (reg) {
|
||||
case R_PROT:
|
||||
if (data == PROT_KEY_UNLOCK) {
|
||||
data = PROT_UNLOCKED;
|
||||
} else if (data == PROT_KEY_HARDLOCK) {
|
||||
data = PROT_HARDLOCKED;
|
||||
} else {
|
||||
data = PROT_SOFTLOCKED;
|
||||
}
|
||||
break;
|
||||
case R_CONF:
|
||||
data = aspeed_2600_sdmc_compute_conf(s, data);
|
||||
break;
|
||||
|
||||
+11
-3
@@ -17,6 +17,7 @@
|
||||
#include "hw/arm/nrf51.h"
|
||||
#include "hw/irq.h"
|
||||
#include "hw/timer/nrf51_timer.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "trace.h"
|
||||
|
||||
@@ -185,7 +186,7 @@ static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int size)
|
||||
__func__, offset);
|
||||
}
|
||||
|
||||
trace_nrf51_timer_read(offset, r, size);
|
||||
trace_nrf51_timer_read(s->id, offset, r, size);
|
||||
|
||||
return r;
|
||||
}
|
||||
@@ -197,7 +198,7 @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
|
||||
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
||||
size_t idx;
|
||||
|
||||
trace_nrf51_timer_write(offset, value, size);
|
||||
trace_nrf51_timer_write(s->id, offset, value, size);
|
||||
|
||||
switch (offset) {
|
||||
case NRF51_TIMER_TASK_START:
|
||||
@@ -239,6 +240,7 @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
|
||||
|
||||
idx = (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4;
|
||||
s->cc[idx] = s->counter;
|
||||
trace_nrf51_timer_set_count(s->id, idx, s->counter);
|
||||
}
|
||||
break;
|
||||
case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3:
|
||||
@@ -313,7 +315,7 @@ static void nrf51_timer_init(Object *obj)
|
||||
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||||
|
||||
memory_region_init_io(&s->iomem, obj, &rng_ops, s,
|
||||
TYPE_NRF51_TIMER, NRF51_TIMER_SIZE);
|
||||
TYPE_NRF51_TIMER, NRF51_PERIPHERAL_SIZE);
|
||||
sysbus_init_mmio(sbd, &s->iomem);
|
||||
sysbus_init_irq(sbd, &s->irq);
|
||||
|
||||
@@ -372,12 +374,18 @@ static const VMStateDescription vmstate_nrf51_timer = {
|
||||
}
|
||||
};
|
||||
|
||||
static Property nrf51_timer_properties[] = {
|
||||
DEFINE_PROP_UINT8("id", NRF51TimerState, id, 0),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void nrf51_timer_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->reset = nrf51_timer_reset;
|
||||
dc->vmsd = &vmstate_nrf51_timer;
|
||||
device_class_set_props(dc, nrf51_timer_properties);
|
||||
}
|
||||
|
||||
static const TypeInfo nrf51_timer_info = {
|
||||
|
||||
@@ -67,8 +67,9 @@ cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK
|
||||
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
|
||||
|
||||
# nrf51_timer.c
|
||||
nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
|
||||
nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
|
||||
nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
|
||||
nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
|
||||
nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32
|
||||
|
||||
# bcm2835_systmr.c
|
||||
bcm2835_systmr_irq(bool enable) "timer irq state %u"
|
||||
|
||||
+12
-1
@@ -328,7 +328,18 @@ CPUArchState *cpu_copy(CPUArchState *env);
|
||||
| CPU_INTERRUPT_TGT_EXT_3 \
|
||||
| CPU_INTERRUPT_TGT_EXT_4)
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
|
||||
/*
|
||||
* Allow some level of source compatibility with softmmu. We do not
|
||||
* support any of the more exotic features, so only invalid pages may
|
||||
* be signaled by probe_access_flags().
|
||||
*/
|
||||
#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
|
||||
#define TLB_MMIO 0
|
||||
#define TLB_WATCHPOINT 0
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* Flags stored in the low bits of the TLB virtual address.
|
||||
|
||||
+212
-71
@@ -25,13 +25,13 @@
|
||||
*
|
||||
* The syntax for the accessors is:
|
||||
*
|
||||
* load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
|
||||
* cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)
|
||||
* cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
|
||||
* load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
|
||||
* cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
|
||||
* cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
|
||||
*
|
||||
* store: cpu_st{size}_{mmusuffix}(env, ptr, val)
|
||||
* cpu_st{size}_{mmusuffix}_ra(env, ptr, val, retaddr)
|
||||
* cpu_st{size}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
|
||||
* store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
|
||||
* cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
|
||||
* cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
|
||||
*
|
||||
* sign is:
|
||||
* (empty): for 32 and 64 bit sizes
|
||||
@@ -44,6 +44,11 @@
|
||||
* l: 32 bits
|
||||
* q: 64 bits
|
||||
*
|
||||
* end is:
|
||||
* (empty): for target native endian, or for 8 bit access
|
||||
* _be: for forced big endian
|
||||
* _le: for forced little endian
|
||||
*
|
||||
* mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
|
||||
* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
|
||||
* the index to use; the "data" and "code" suffixes take the index from
|
||||
@@ -95,32 +100,57 @@ typedef target_ulong abi_ptr;
|
||||
#endif
|
||||
|
||||
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
|
||||
uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr);
|
||||
uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr);
|
||||
uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr);
|
||||
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
|
||||
int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr);
|
||||
|
||||
uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
|
||||
uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
|
||||
uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
|
||||
uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
|
||||
int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
|
||||
int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
|
||||
uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
|
||||
int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
|
||||
uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
|
||||
uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
|
||||
|
||||
uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
|
||||
int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
|
||||
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
|
||||
uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
|
||||
|
||||
uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
|
||||
int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
|
||||
|
||||
uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
|
||||
int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
|
||||
uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
|
||||
uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
|
||||
|
||||
uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
|
||||
int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
|
||||
uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
|
||||
uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
|
||||
|
||||
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
|
||||
void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
|
||||
void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
|
||||
void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
|
||||
|
||||
void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
|
||||
void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
|
||||
void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
|
||||
|
||||
void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
|
||||
void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
|
||||
void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
|
||||
|
||||
void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t retaddr);
|
||||
void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t retaddr);
|
||||
void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t retaddr);
|
||||
void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint64_t val, uintptr_t retaddr);
|
||||
uint32_t val, uintptr_t ra);
|
||||
|
||||
void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t ra);
|
||||
void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t ra);
|
||||
void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint64_t val, uintptr_t ra);
|
||||
|
||||
void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t ra);
|
||||
void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint32_t val, uintptr_t ra);
|
||||
void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
|
||||
uint64_t val, uintptr_t ra);
|
||||
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
|
||||
@@ -157,34 +187,58 @@ static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
return cpu_ldub_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_lduw_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_ldl_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_ldq_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_ldsb_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_ldsw_data_ra(env, addr, ra);
|
||||
return cpu_lduw_be_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_ldsw_be_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_ldl_be_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_ldq_be_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_lduw_le_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_ldsw_le_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_ldl_le_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra)
|
||||
{
|
||||
return cpu_ldq_le_data_ra(env, addr, ra);
|
||||
}
|
||||
|
||||
static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
@@ -193,22 +247,46 @@ static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
cpu_stb_data_ra(env, addr, val, ra);
|
||||
}
|
||||
|
||||
static inline void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
uint32_t val, int mmu_idx, uintptr_t ra)
|
||||
static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
uint32_t val, int mmu_idx,
|
||||
uintptr_t ra)
|
||||
{
|
||||
cpu_stw_data_ra(env, addr, val, ra);
|
||||
cpu_stw_be_data_ra(env, addr, val, ra);
|
||||
}
|
||||
|
||||
static inline void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
uint32_t val, int mmu_idx, uintptr_t ra)
|
||||
static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
uint32_t val, int mmu_idx,
|
||||
uintptr_t ra)
|
||||
{
|
||||
cpu_stl_data_ra(env, addr, val, ra);
|
||||
cpu_stl_be_data_ra(env, addr, val, ra);
|
||||
}
|
||||
|
||||
static inline void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
uint64_t val, int mmu_idx, uintptr_t ra)
|
||||
static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
uint64_t val, int mmu_idx,
|
||||
uintptr_t ra)
|
||||
{
|
||||
cpu_stq_data_ra(env, addr, val, ra);
|
||||
cpu_stq_be_data_ra(env, addr, val, ra);
|
||||
}
|
||||
|
||||
static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
uint32_t val, int mmu_idx,
|
||||
uintptr_t ra)
|
||||
{
|
||||
cpu_stw_le_data_ra(env, addr, val, ra);
|
||||
}
|
||||
|
||||
static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
uint32_t val, int mmu_idx,
|
||||
uintptr_t ra)
|
||||
{
|
||||
cpu_stl_le_data_ra(env, addr, val, ra);
|
||||
}
|
||||
|
||||
static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
uint64_t val, int mmu_idx,
|
||||
uintptr_t ra)
|
||||
{
|
||||
cpu_stq_le_data_ra(env, addr, val, ra);
|
||||
}
|
||||
|
||||
#else
|
||||
@@ -243,29 +321,92 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
|
||||
|
||||
uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
|
||||
int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
|
||||
uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
|
||||
uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
|
||||
int mmu_idx, uintptr_t ra);
|
||||
|
||||
void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
|
||||
void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
|
||||
void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
|
||||
int mmu_idx, uintptr_t retaddr);
|
||||
|
||||
#endif /* defined(CONFIG_USER_ONLY) */
|
||||
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
# define cpu_lduw_data cpu_lduw_be_data
|
||||
# define cpu_ldsw_data cpu_ldsw_be_data
|
||||
# define cpu_ldl_data cpu_ldl_be_data
|
||||
# define cpu_ldq_data cpu_ldq_be_data
|
||||
# define cpu_lduw_data_ra cpu_lduw_be_data_ra
|
||||
# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
|
||||
# define cpu_ldl_data_ra cpu_ldl_be_data_ra
|
||||
# define cpu_ldq_data_ra cpu_ldq_be_data_ra
|
||||
# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
|
||||
# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
|
||||
# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
|
||||
# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
|
||||
# define cpu_stw_data cpu_stw_be_data
|
||||
# define cpu_stl_data cpu_stl_be_data
|
||||
# define cpu_stq_data cpu_stq_be_data
|
||||
# define cpu_stw_data_ra cpu_stw_be_data_ra
|
||||
# define cpu_stl_data_ra cpu_stl_be_data_ra
|
||||
# define cpu_stq_data_ra cpu_stq_be_data_ra
|
||||
# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
|
||||
# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
|
||||
# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
|
||||
#else
|
||||
# define cpu_lduw_data cpu_lduw_le_data
|
||||
# define cpu_ldsw_data cpu_ldsw_le_data
|
||||
# define cpu_ldl_data cpu_ldl_le_data
|
||||
# define cpu_ldq_data cpu_ldq_le_data
|
||||
# define cpu_lduw_data_ra cpu_lduw_le_data_ra
|
||||
# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
|
||||
# define cpu_ldl_data_ra cpu_ldl_le_data_ra
|
||||
# define cpu_ldq_data_ra cpu_ldq_le_data_ra
|
||||
# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
|
||||
# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
|
||||
# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
|
||||
# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
|
||||
# define cpu_stw_data cpu_stw_le_data
|
||||
# define cpu_stl_data cpu_stl_le_data
|
||||
# define cpu_stq_data cpu_stq_le_data
|
||||
# define cpu_stw_data_ra cpu_stw_le_data_ra
|
||||
# define cpu_stl_data_ra cpu_stl_le_data_ra
|
||||
# define cpu_stq_data_ra cpu_stq_le_data_ra
|
||||
# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
|
||||
# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
|
||||
# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
|
||||
#endif
|
||||
|
||||
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
|
||||
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
|
||||
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
|
||||
|
||||
@@ -330,6 +330,23 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
||||
{
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* probe_access:
|
||||
* @env: CPUArchState
|
||||
* @addr: guest virtual address to look up
|
||||
* @size: size of the access
|
||||
* @access_type: read, write or execute permission
|
||||
* @mmu_idx: MMU index to use for lookup
|
||||
* @retaddr: return address for unwinding
|
||||
*
|
||||
* Look up the guest virtual address @addr. Raise an exception if the
|
||||
* page does not satisfy @access_type. Raise an exception if the
|
||||
* access (@addr, @size) hits a watchpoint. For writes, mark a clean
|
||||
* page as dirty.
|
||||
*
|
||||
* Finally, return the host address for a page that is backed by RAM,
|
||||
* or NULL if the page requires I/O.
|
||||
*/
|
||||
void *probe_access(CPUArchState *env, target_ulong addr, int size,
|
||||
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
|
||||
|
||||
@@ -345,6 +362,28 @@ static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
|
||||
return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
|
||||
}
|
||||
|
||||
/**
|
||||
* probe_access_flags:
|
||||
* @env: CPUArchState
|
||||
* @addr: guest virtual address to look up
|
||||
* @access_type: read, write or execute permission
|
||||
* @mmu_idx: MMU index to use for lookup
|
||||
* @nonfault: suppress the fault
|
||||
* @phost: return value for host address
|
||||
* @retaddr: return address for unwinding
|
||||
*
|
||||
* Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
|
||||
* the page, and storing the host address for RAM in @phost.
|
||||
*
|
||||
* If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
|
||||
* Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
|
||||
* Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
|
||||
* For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
|
||||
*/
|
||||
int probe_access_flags(CPUArchState *env, target_ulong addr,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
bool nonfault, void **phost, uintptr_t retaddr);
|
||||
|
||||
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
|
||||
|
||||
/* Estimated block size for TB allocation. */
|
||||
|
||||
@@ -24,11 +24,10 @@
|
||||
#define NRF51_IOMEM_BASE 0x40000000
|
||||
#define NRF51_IOMEM_SIZE 0x20000000
|
||||
|
||||
#define NRF51_PERIPHERAL_SIZE 0x00001000
|
||||
#define NRF51_UART_BASE 0x40002000
|
||||
#define NRF51_TWI_BASE 0x40003000
|
||||
#define NRF51_TWI_SIZE 0x00001000
|
||||
#define NRF51_TIMER_BASE 0x40008000
|
||||
#define NRF51_TIMER_SIZE 0x00001000
|
||||
#define NRF51_RNG_BASE 0x4000D000
|
||||
#define NRF51_NVMC_BASE 0x4001E000
|
||||
#define NRF51_GPIO_BASE 0x50000000
|
||||
|
||||
@@ -1100,8 +1100,31 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
|
||||
vaddr len, int flags);
|
||||
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
|
||||
void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
|
||||
|
||||
/**
|
||||
* cpu_check_watchpoint:
|
||||
* @cpu: cpu context
|
||||
* @addr: guest virtual address
|
||||
* @len: access length
|
||||
* @attrs: memory access attributes
|
||||
* @flags: watchpoint access type
|
||||
* @ra: unwind return address
|
||||
*
|
||||
* Check for a watchpoint hit in [addr, addr+len) of the type
|
||||
* specified by @flags. Exit via exception with a hit.
|
||||
*/
|
||||
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
|
||||
MemTxAttrs attrs, int flags, uintptr_t ra);
|
||||
|
||||
/**
|
||||
* cpu_watchpoint_address_matches:
|
||||
* @cpu: cpu context
|
||||
* @addr: guest virtual address
|
||||
* @len: access length
|
||||
*
|
||||
* Return the watchpoint flags that apply to [addr, addr+len).
|
||||
* If no watchpoint is registered for the range, the result is 0.
|
||||
*/
|
||||
int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
|
||||
#endif
|
||||
|
||||
|
||||
@@ -29,7 +29,7 @@
|
||||
#define MICROBIT_I2C(obj) \
|
||||
OBJECT_CHECK(MicrobitI2CState, (obj), TYPE_MICROBIT_I2C)
|
||||
|
||||
#define MICROBIT_I2C_NREGS (NRF51_TWI_SIZE / sizeof(uint32_t))
|
||||
#define MICROBIT_I2C_NREGS (NRF51_PERIPHERAL_SIZE / sizeof(uint32_t))
|
||||
|
||||
typedef struct {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
@@ -41,6 +41,7 @@ typedef struct AspeedSCUState {
|
||||
#define AST2500_A0_SILICON_REV 0x04000303U
|
||||
#define AST2500_A1_SILICON_REV 0x04010303U
|
||||
#define AST2600_A0_SILICON_REV 0x05000303U
|
||||
#define AST2600_A1_SILICON_REV 0x05010303U
|
||||
|
||||
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user