CRIS testsuite, based on the SIM testsuite, by Edgar E. Iglesias.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3365 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
2007-10-08 13:32:20 +00:00
parent 83fa1010ae
commit dd43edf4e1
103 changed files with 7014 additions and 0 deletions
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b main
b _fail
b exit
display /i $pc
display /x $srp
display /x $r0
display /x $r1
display /x $r2
display /x $r3
display /x $r4
display /t $ccs
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-include ../../config-host.mak
CROSS=crisv32-axis-linux-gnu-
SIM=../../cris-linux-user/qemu-cris -L ./
SIMG=cris-axis-linux-gnu-run --sysroot=./
CC = $(CROSS)gcc
#AS = $(CROSS)as
AS = $(CC) -x assembler-with-cpp
SIZE = $(CROSS)size
LD = $(CC)
OBJCOPY = $(CROSS)objcopy
# we rely on GCC inline:ing the stuff we tell it to in many places here.
CFLAGS = -Winline -Wall -g -O2 -static
NOSTDFLAGS = -nostartfiles -nostdlib
ASFLAGS += -g -Wa,-I,$(SRC_PATH)/tests/cris/
LDLIBS =
NOSTDLIBS = -lgcc
CRT = crt.o
SYS = sys.o
TESTCASES += check_abs.tst
TESTCASES += check_addc.tst
TESTCASES += check_addcm.tst
TESTCASES += check_addo.tst
TESTCASES += check_addoq.tst
TESTCASES += check_addi.tst
TESTCASES += check_addiv32.tst
TESTCASES += check_addm.tst
TESTCASES += check_addr.tst
TESTCASES += check_addq.tst
TESTCASES += check_addxc.tst
TESTCASES += check_addxm.tst
TESTCASES += check_addxr.tst
TESTCASES += check_andc.tst
TESTCASES += check_andm.tst
TESTCASES += check_andr.tst
TESTCASES += check_andq.tst
TESTCASES += check_asr.tst
TESTCASES += check_ba.tst
TESTCASES += check_bas.tst
TESTCASES += check_bcc.tst
TESTCASES += check_bound.tst
TESTCASES += check_boundc.tst
TESTCASES += check_boundr.tst
TESTCASES += check_btst.tst
TESTCASES += check_clearfv32.tst
TESTCASES += check_cmpc.tst
TESTCASES += check_cmpr.tst
TESTCASES += check_cmpq.tst
TESTCASES += check_cmpm.tst
TESTCASES += check_cmpxc.tst
TESTCASES += check_cmpxm.tst
TESTCASES += check_cmp-2.tst
TESTCASES += check_clrjmp1.tst
TESTCASES += check_dstep.tst
TESTCASES += check_int64.tst
# check_jsr is broken.
#TESTCASES += check_jsr.tst
TESTCASES += check_mcp.tst
TESTCASES += check_movei.tst
TESTCASES += check_mover.tst
TESTCASES += check_moverm.tst
TESTCASES += check_moveq.tst
TESTCASES += check_movemr.tst
TESTCASES += check_movemrv32.tst
TESTCASES += check_movecr.tst
TESTCASES += check_movmp.tst
TESTCASES += check_movpr.tst
TESTCASES += check_movprv32.tst
TESTCASES += check_movdelsr1.tst
TESTCASES += check_movpmv32.tst
TESTCASES += check_movsr.tst
TESTCASES += check_movsm.tst
TESTCASES += check_movscr.tst
TESTCASES += check_movur.tst
TESTCASES += check_movum.tst
TESTCASES += check_movucr.tst
TESTCASES += check_mulx.tst
TESTCASES += check_mulv32.tst
TESTCASES += check_neg.tst
TESTCASES += check_not.tst
TESTCASES += check_lz.tst
TESTCASES += check_lapc.tst
TESTCASES += check_lsl.tst
TESTCASES += check_lsr.tst
TESTCASES += check_orc.tst
TESTCASES += check_orm.tst
TESTCASES += check_orr.tst
TESTCASES += check_orq.tst
TESTCASES += check_ret.tst
TESTCASES += check_swap.tst
TESTCASES += check_scc.tst
TESTCASES += check_subc.tst
TESTCASES += check_subq.tst
TESTCASES += check_subr.tst
TESTCASES += check_subm.tst
TESTCASES += check_glibc_kernelversion.tst
TESTCASES += check_xarith.tst
TESTCASES += check_hello.ctst
TESTCASES += check_stat1.ctst
TESTCASES += check_stat2.ctst
TESTCASES += check_stat3.ctst
TESTCASES += check_stat4.ctst
TESTCASES += check_openpf1.ctst
TESTCASES += check_openpf2.ctst
TESTCASES += check_openpf3.ctst
TESTCASES += check_openpf4.ctst
TESTCASES += check_openpf5.ctst
TESTCASES += check_mapbrk.ctst
TESTCASES += check_mmap1.ctst
TESTCASES += check_mmap2.ctst
TESTCASES += check_mmap3.ctst
TESTCASES += check_time1.ctst
TESTCASES += check_time2.ctst
TESTCASES += check_gcctorture_pr28634-1.ctst
#TESTCASES += check_gcctorture_pr28634.ctst
all: build
%.o: $(SRC_PATH)/tests/cris/%.c
$(CC) $(CFLAGS) -c $< -o $@
%.o: $(SRC_PATH)/tests/cris/%.s
$(AS) $(ASFLAGS) -c $< -o $@
%.tst: %.o
$(CC) $(CFLAGS) $(NOSTDFLAGS) $(LDLIBS) $(NOSTDLIBS) $(CRT) $< $(SYS) -o $@
%.ctst: %.o
$(CC) $(CFLAGS) $(LDLIBS) $< -o $@
build: $(CRT) $(SYS) $(TESTCASES)
check: $(CRT) $(SYS) $(TESTCASES)
@echo -e "\nQEMU simulator."
@for case in $(TESTCASES); do \
echo -n "$$case "; \
$(SIM) $$case; \
done
check-g: $(CRT) $(SYS) $(TESTCASES)
@echo -e "\nGDB simulator."
@for case in $(TESTCASES); do \
echo -n "$$case "; \
$(SIMG) $$case; \
done
clean:
$(RM) -fr $(TESTCASES) $(CRT) $(SYS)
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Test-suite for the cris port. Heavily based on the test-suite for the CRIS port of sim by Hans-Peter Nilsson.
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#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include "sys.h"
#include "crisutils.h"
extern inline int cris_abs(int n) {
int r;
asm ("abs\t%1, %0\n" : "=r" (r) : "r" (n));
return r;
}
extern inline void
verify_abs(int val, int res,
const int n, const int z, const int v, const int c)
{
int r;
cris_tst_cc_init();
r = cris_abs(val);
cris_tst_cc(n, z, v, c);
if (r != res)
err();
}
int main(void)
{
verify_abs(-1, 1, 0, 0, 0, 0);
verify_abs(0x80000000, 0x80000000, 1, 0, 0, 0);
verify_abs(0x7fffffff, 0x7fffffff, 0, 0, 0, 0);
verify_abs(42, 42, 0, 0, 0, 0);
verify_abs(1, 1, 0, 0, 0, 0);
verify_abs(0xffff, 0xffff, 0, 0, 0, 0);
verify_abs(0xffff, 0xffff, 0, 0, 0, 0);
verify_abs(-31, 0x1f, 0, 0, 0, 0);
verify_abs(0, 0, 0, 1, 0, 0);
pass();
return 0;
}
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#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include "sys.h"
#include "crisutils.h"
extern inline int cris_addc(int a, const int b) {
asm ("addc\t%1, %0\n" : "+r" (a) : "r" (b));
return a;
}
#define verify_addc(a, b, res, n, z, v, c) \
{ \
int r; \
r = cris_addc((a), (b)); \
cris_tst_cc((n), (z), (v), (c)); \
if (r != (res)) \
err(); \
}
int main(void)
{
cris_tst_cc_init();
asm volatile ("clearf cz");
verify_addc(0, 0, 0, 0, 0, 0, 0);
cris_tst_cc_init();
asm volatile ("setf z");
verify_addc(0, 0, 0, 0, 1, 0, 0);
cris_tst_cc_init();
asm volatile ("setf cz");
verify_addc(0, 0, 1, 0, 0, 0, 0);
cris_tst_cc_init();
asm volatile ("clearf c");
verify_addc(-1, 2, 1, 0, 0, 0, 1);
cris_tst_cc_init();
asm volatile ("clearf nzv");
asm volatile ("setf c");
verify_addc(-1, 2, 2, 0, 0, 0, 1);
cris_tst_cc_init();
asm volatile ("setf c");
verify_addc(0xffff, 0xffff, 0x1ffff, 0, 0, 0, 0);
cris_tst_cc_init();
asm volatile ("clearf nzvc");
verify_addc(-1, -1, 0xfffffffe, 1, 0, 0, 1);
cris_tst_cc_init();
asm volatile ("setf c");
verify_addc(0x78134452, 0x5432f789, 0xcc463bdc, 1, 0, 1, 0);
pass();
return 0;
}
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#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include "sys.h"
#include "crisutils.h"
/* need to avoid acr as source here. */
extern inline int cris_addc_m(int a, const int *b) {
asm volatile ("addc [%1], %0\n" : "+r" (a) : "r" (b));
return a;
}
/* 'b' is a crisv32 constrain to avoid postinc with $acr. */
extern inline int cris_addc_pi_m(int a, int **b) {
asm volatile ("addc [%1+], %0\n" : "+r" (a), "+b" (*b));
return a;
}
#define verify_addc_m(a, b, res, n, z, v, c) \
{ \
int r; \
r = cris_addc_m((a), (b)); \
cris_tst_cc((n), (z), (v), (c)); \
if (r != (res)) \
err(); \
}
#define verify_addc_pi_m(a, b, res, n, z, v, c) \
{ \
int r; \
r = cris_addc_pi_m((a), (b)); \
cris_tst_cc((n), (z), (v), (c)); \
if (r != (res)) \
err(); \
}
int x[] = { 0, 0, 2, -1, 0xffff, -1, 0x5432f789};
int main(void)
{
int *p = (void *)&x[0];
#if 1
cris_tst_cc_init();
asm volatile ("clearf cz");
verify_addc_m(0, p, 0, 0, 0, 0, 0);
cris_tst_cc_init();
asm volatile ("setf z");
verify_addc_m(0, p, 0, 0, 1, 0, 0);
cris_tst_cc_init();
asm volatile ("setf c");
verify_addc_m(0, p, 1, 0, 0, 0, 0);
cris_tst_cc_init();
asm volatile ("clearf c");
verify_addc_pi_m(0, &p, 0, 0, 1, 0, 0);
p = &x[1];
cris_tst_cc_init();
asm volatile ("setf c");
verify_addc_pi_m(0, &p, 1, 0, 0, 0, 0);
if (p != &x[2])
err();
cris_tst_cc_init();
asm volatile ("clearf c");
verify_addc_pi_m(-1, &p, 1, 0, 0, 0, 1);
if (p != &x[3])
err();
#endif
p = &x[3];
/* TODO: investigate why this one fails. */
cris_tst_cc_init();
asm volatile ("setf c");
verify_addc_m(2, p, 2, 0, 0, 0, 1);
p += 4;
pass();
return 0;
}
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# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 0\n1\n2\n4\nbe02460f\n69d035a6\nc16c14d4\n
.include "testutils.inc"
start
moveq 0,r3
moveq 0,r4
clearf zcvn
addi r4.b,r3
test_cc 0 0 0 0
checkr3 0
moveq 0,r3
moveq 1,r4
setf zcvn
addi r4.b,r3
test_cc 1 1 1 1
checkr3 1
moveq 0,r3
moveq 1,r4
setf cv
clearf zn
addi r4.w,r3
test_cc 0 0 1 1
checkr3 2
moveq 0,r3
moveq 1,r4
clearf cv
setf zn
addi r4.d,r3
test_cc 1 1 0 0
checkr3 4
move.d 0x12345678,r3
move.d 0xabcdef97,r4
clearf cn
setf zv
addi r4.b,r3
test_cc 0 1 1 0
checkr3 be02460f
move.d 0x12345678,r3
move.d 0xabcdef97,r4
setf cn
clearf zv
addi r4.w,r3
test_cc 1 0 0 1
checkr3 69d035a6
move.d 0x12345678,r3
move.d 0xabcdef97,r4
addi r4.d,r3
checkr3 c16c14d4
quit
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# mach: crisv32
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
start
setf cv
moveq -1,r0
move.d x-32768,r5
move.d 32769,r6
addi r6.b,r5,acr
test_cc 0 0 1 1
move.d [acr],r3
checkr3 4455aa77
addu.w 32771,r5
setf znvc
moveq -1,r8
addi r8.w,r5,acr
test_cc 1 1 1 1
move.d [acr],r3
checkr3 4455aa77
moveq 5,r10
clearf znvc
addi r10.b,acr,acr
test_cc 0 0 0 0
move.d [acr],r3
checkr3 ee19ccff
subq 1,r5
move.d r5,r8
subq 1,r8
moveq 1,r9
addi r9.d,r8,acr
test_cc 0 0 0 0
movu.w [acr],r3
checkr3 ff22
moveq -2,r11
addi r11.w,acr,acr
move.d [acr],r3
checkr3 4455aa77
moveq 5,r9
addi r9.d,acr,acr
subq 18,acr
move.d [acr],r3
checkr3 ff224455
move.d -76789888/4,r12
addi r12.d,r5,acr
add.d 76789886,acr
move.d [acr],r3
checkr3 55aa77ff
quit
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# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n781344d0\n
.include "testutils.inc"
.data
x:
.dword 2,-1,0xffff,-1,0x5432f789
.word 2,-1,0xffff,0xf789
.byte 2,0xff,0x89
.byte 0x7e
start
moveq -1,r3
move.d x,r5
add.d [r5+],r3
test_cc 0 0 0 1
checkr3 1
moveq 2,r3
add.d [r5],r3
test_cc 0 0 0 1
addq 4,r5
checkr3 1
move.d 0xffff,r3
add.d [r5+],r3
test_cc 0 0 0 0
checkr3 1fffe
moveq -1,r3
add.d [r5+],r3
test_cc 1 0 0 1
checkr3 fffffffe
move.d 0x78134452,r3
add.d [r5+],r3
test_cc 1 0 1 0
checkr3 cc463bdb
moveq -1,r3
add.w [r5+],r3
test_cc 0 0 0 1
checkr3 ffff0001
moveq 2,r3
add.w [r5+],r3
test_cc 0 0 0 1
checkr3 1
move.d 0xffff,r3
add.w [r5],r3
test_cc 1 0 0 1
checkr3 fffe
move.d 0xfedaffff,r3
add.w [r5+],r3
test_cc 1 0 0 1
checkr3 fedafffe
move.d 0x78134452,r3
add.w [r5+],r3
test_cc 0 0 0 1
checkr3 78133bdb
moveq -1,r3
add.b [r5],r3
test_cc 0 0 0 1
addq 1,r5
checkr3 ffffff01
moveq 2,r3
add.b [r5],r3
test_cc 0 0 0 1
checkr3 1
move.d 0xff,r3
add.b [r5],r3
test_cc 1 0 0 1
checkr3 fe
move.d 0xfeda49ff,r3
add.b [r5+],r3
test_cc 1 0 0 1
checkr3 feda49fe
move.d 0x78134452,r3
add.b [r5+],r3
test_cc 1 0 0 0
checkr3 781344db
move.d 0x78134452,r3
add.b [r5],r3
test_cc 1 0 1 0
checkr3 781344d0
quit
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#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include "sys.h"
#include "crisutils.h"
/* this would be better to do in asm, it's an orgy in GCC inline asm now. */
#define cris_addo_b(o, v) \
asm volatile ("addo.b\t[%0], %1, $acr\n" : : "r" (o), "r" (v) : "acr");
#define cris_addo_w(o, v) \
asm volatile ("addo.w\t[%0], %1, $acr\n" : : "r" (o), "r" (v) : "acr");
#define cris_addo_d(o, v) \
asm volatile ("addo.d\t[%0], %1, $acr\n" : : "r" (o), "r" (v) : "acr");
#define cris_addo_pi_b(o, v) \
asm volatile ("addo.b\t[%0+], %1, $acr\n" \
: "+b" (o): "r" (v) : "acr");
#define cris_addo_pi_w(o, v) \
asm volatile ("addo.w\t[%0+], %1, $acr\n" \
: "+b" (o): "r" (v) : "acr");
#define cris_addo_pi_d(o, v) \
asm volatile ("addo.d\t[%0+], %1, $acr\n" \
: "+b" (o): "r" (v) : "acr");
struct {
uint32_t v1;
uint16_t v2;
uint32_t v3;
uint8_t v4;
uint8_t v5;
uint16_t v6;
uint32_t v7;
} y = {
32769,
-1,
5,
3, -4,
2,
-76789887
};
static int x[3] = {0x55aa77ff, 0xccff2244, 0x88ccee19};
int main(void)
{
int *r;
unsigned char *t, *p;
/* Note, this test-case will trig an unaligned access, partly
to x[0] and to [x1]. */
t = (unsigned char *)x;
t -= 32768;
p = (unsigned char *) &y.v1;
mb(); /* dont reorder anything beyond here. */
cris_tst_cc_init();
asm volatile ("setf\tzvnc\n");
cris_addo_pi_d(p, t);
cris_tst_cc(1, 1, 1, 1);
asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
if (*r != 0x4455aa77)
err();
t += 32770;
mb(); /* dont reorder anything beyond here. */
cris_tst_cc_init();
asm volatile ("setf\tzvnc\n");
cris_addo_pi_w(p, t);
cris_tst_cc(1, 1, 1, 1);
asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
if (*r != 0x4455aa77)
err();
mb(); /* dont reorder anything beyond here. */
cris_tst_cc_init();
asm volatile ("setf\tzvnc\n");
cris_addo_d(p, r);
cris_tst_cc(1, 1, 1, 1);
p += 4;
asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
if (*r != 0xee19ccff)
err();
mb(); /* dont reorder anything beyond here. */
cris_tst_cc_init();
asm volatile ("setf\tzvnc\n");
cris_addo_pi_b(p, t);
cris_tst_cc(1, 1, 1, 1);
asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
if (*(uint16_t*)r != 0xff22)
err();
mb(); /* dont reorder anything beyond here. */
cris_tst_cc_init();
asm volatile ("setf\tzvnc\n");
cris_addo_b(p, r);
cris_tst_cc(1, 1, 1, 1);
p += 1;
asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
if (*r != 0x4455aa77)
err();
mb(); /* dont reorder anything beyond here. */
cris_tst_cc_init();
asm volatile ("setf\tzvnc\n");
cris_addo_w(p, r);
cris_tst_cc(1, 1, 1, 1);
p += 2;
asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
if (*r != 0xff224455)
err();
mb(); /* dont reorder anything beyond here. */
cris_tst_cc_init();
asm volatile ("setf\tzvnc\n");
cris_addo_pi_d(p, t);
cris_tst_cc(1, 1, 1, 1);
asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
r = (void*)(((char *)r) + 76789885);
if (*r != 0x55aa77ff)
err();
pass();
return 0;
}
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#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include "sys.h"
#include "crisutils.h"
/* this would be better to do in asm, it's an orgy in GCC inline asm now. */
/* ACR will be clobbered. */
#define cris_addoq(o, v) \
asm volatile ("addoq\t%1, %0, $acr\n" : : "r" (v), "i" (o) : "acr");
int main(void)
{
int x[3] = {0x55aa77ff, 0xccff2244, 0x88ccee19};
int *p, *t = x + 1;
cris_tst_cc_init();
asm volatile ("setf\tzvnc\n");
cris_addoq(0, t);
cris_tst_cc(1, 1, 1, 1);
asm volatile ("move.d\t$acr, %0\n" : "=r" (p));
if (*p != 0xccff2244)
err();
cris_tst_cc_init();
asm volatile ("setf\tzvnc\n");
cris_addoq(4, t);
cris_tst_cc(1, 1, 1, 1);
asm volatile ("move.d\t$acr, %0\n" : "=r" (p));
if (*p != 0x88ccee19)
err();
cris_tst_cc_init();
asm volatile ("clearf\tzvnc\n");
cris_addoq(-8, t + 1);
cris_tst_cc(0, 0, 0, 0);
asm volatile ("move.d\t$acr, %0\n" : "=r" (p));
if (*p != 0x55aa77ff)
err();
pass();
return 0;
}
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# mach: crisv3 crisv8 crisv10 crisv32
# output: ffffffff\n0\n1\n100\n10000\n47\n67\na6\n80000001\n
.include "testutils.inc"
start
moveq -2,r3
addq 1,r3
test_cc 1 0 0 0
checkr3 ffffffff
addq 1,r3
test_cc 0 1 0 1
checkr3 0
addq 1,r3
test_cc 0 0 0 0
checkr3 1
move.d 0xff,r3
addq 1,r3
test_cc 0 0 0 0
checkr3 100
move.d 0xffff,r3
addq 1,r3
test_cc 0 0 0 0
checkr3 10000
move.d 0x42,r3
addq 5,r3
test_cc 0 0 0 0
checkr3 47
addq 32,r3
test_cc 0 0 0 0
checkr3 67
addq 63,r3
test_cc 0 0 0 0
checkr3 a6
move.d 0x7ffffffe,r3
addq 3,r3
test_cc 1 0 1 0
checkr3 80000001
quit
+96
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# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
add.d r4,r3
test_cc 0 0 0 1
checkr3 1
moveq 2,r3
moveq -1,r4
add.d r4,r3
test_cc 0 0 0 1
checkr3 1
move.d 0xffff,r4
move.d r4,r3
add.d r4,r3
test_cc 0 0 0 0
checkr3 1fffe
moveq -1,r4
move.d r4,r3
add.d r4,r3
test_cc 1 0 0 1
checkr3 fffffffe
move.d 0x5432f789,r4
move.d 0x78134452,r3
add.d r4,r3
test_cc 1 0 1 0
checkr3 cc463bdb
moveq -1,r3
moveq 2,r4
add.w r4,r3
test_cc 0 0 0 1
checkr3 ffff0001
moveq 2,r3
moveq -1,r4
add.w r4,r3
test_cc 0 0 0 1
checkr3 1
move.d 0xffff,r4
move.d r4,r3
add.w r4,r3
test_cc 1 0 0 1
checkr3 fffe
move.d 0xfedaffff,r4
move.d r4,r3
add.w r4,r3
test_cc 1 0 0 1
checkr3 fedafffe
move.d 0x5432f789,r4
move.d 0x78134452,r3
add.w r4,r3
test_cc 0 0 0 1
checkr3 78133bdb
moveq -1,r3
moveq 2,r4
add.b r4,r3
test_cc 0 0 0 1
checkr3 ffffff01
moveq 2,r3
moveq -1,r4
add.b r4,r3
test_cc 0 0 0 1
checkr3 1
move.d 0xff,r4
move.d r4,r3
add.b r4,r3
test_cc 1 0 0 1
checkr3 fe
move.d 0xfeda49ff,r4
move.d r4,r3
add.b r4,r3
test_cc 1 0 0 1
checkr3 feda49fe
move.d 0x5432f789,r4
move.d 0x78134452,r3
add.b r4,r3
test_cc 1 0 0 0
checkr3 781344db
quit
+91
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# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n
.include "testutils.inc"
start
moveq 2,r3
adds.b 0xff,r3
test_cc 0 0 0 1
checkr3 1
moveq 2,r3
adds.w 0xffff,r3
test_cc 0 0 0 1
checkr3 1
moveq 2,r3
addu.b 0xff,r3
checkr3 101
moveq 2,r3
move.d 0xffffffff,r4
addu.w -1,r3
test_cc 0 0 0 0
checkr3 10001
move.d 0xffff,r3
addu.b -1,r3
test_cc 0 0 0 0
checkr3 100fe
move.d 0xffff,r3
addu.w -1,r3
test_cc 0 0 0 0
checkr3 1fffe
move.d 0xffff,r3
adds.b 0xff,r3
test_cc 0 0 0 1
checkr3 fffe
move.d 0xffff,r3
adds.w 0xffff,r3
test_cc 0 0 0 1
checkr3 fffe
moveq -1,r3
adds.b 0xff,r3
test_cc 1 0 0 1
checkr3 fffffffe
moveq -1,r3
adds.w 0xff,r3
test_cc 0 0 0 1
checkr3 fe
moveq -1,r3
adds.w 0xffff,r3
test_cc 1 0 0 1
checkr3 fffffffe
move.d 0x78134452,r3
addu.b 0x89,r3
test_cc 0 0 0 0
checkr3 781344db
move.d 0x78134452,r3
adds.b 0x89,r3
test_cc 0 0 0 1
checkr3 781343db
move.d 0x78134452,r3
addu.w 0xf789,r3
test_cc 0 0 0 0
checkr3 78143bdb
move.d 0x78134452,r3
adds.w 0xf789,r3
test_cc 0 0 0 1
checkr3 78133bdb
move.d 0x7fffffee,r3
addu.b 0xff,r3
test_cc 1 0 1 0
checkr3 800000ed
move.d 0x1,r3
adds.w 0xffff,r3
test_cc 0 1 0 1
checkr3 0
quit
+106
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# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n
.include "testutils.inc"
.data
x:
.byte 0xff
.word 0xffff
.word 0xff
.word 0xffff
.byte 0x89
.word 0xf789
.byte 0xff
.word 0xffff
start
moveq 2,r3
move.d x,r5
adds.b [r5+],r3
test_cc 0 0 0 1
checkr3 1
moveq 2,r3
adds.w [r5+],r3
test_cc 0 0 0 1
checkr3 1
moveq 2,r3
subq 3,r5
addu.b [r5+],r3
test_cc 0 0 0 0
checkr3 101
moveq 2,r3
addu.w [r5+],r3
subq 3,r5
test_cc 0 0 0 0
checkr3 10001
move.d 0xffff,r3
addu.b [r5],r3
test_cc 0 0 0 0
checkr3 100fe
move.d 0xffff,r3
addu.w [r5],r3
test_cc 0 0 0 0
checkr3 1fffe
move.d 0xffff,r3
adds.b [r5],r3
test_cc 0 0 0 1
checkr3 fffe
move.d 0xffff,r3
adds.w [r5],r3
test_cc 0 0 0 1
checkr3 fffe
moveq -1,r3
adds.b [r5],r3
test_cc 1 0 0 1
addq 3,r5
checkr3 fffffffe
moveq -1,r3
adds.w [r5+],r3
test_cc 0 0 0 1
checkr3 fe
moveq -1,r3
adds.w [r5+],r3
test_cc 1 0 0 1
checkr3 fffffffe
move.d 0x78134452,r3
addu.b [r5],r3
test_cc 0 0 0 0
checkr3 781344db
move.d 0x78134452,r3
adds.b [r5+],r3
test_cc 0 0 0 1
checkr3 781343db
move.d 0x78134452,r3
addu.w [r5],r3
test_cc 0 0 0 0
checkr3 78143bdb
move.d 0x78134452,r3
adds.w [r5+],r3
test_cc 0 0 0 1
checkr3 78133bdb
move.d 0x7fffffee,r3
addu.b [r5+],r3
test_cc 1 0 1 0
checkr3 800000ed
move.d 0x1,r3
adds.w [r5+],r3
test_cc 0 1 0 1
checkr3 0
quit
+96
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# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
add.d r4,r3
test_cc 0 0 0 1
checkr3 1
moveq 2,r3
moveq -1,r4
add.d r4,r3
test_cc 0 0 0 1
checkr3 1
move.d 0xffff,r4
move.d r4,r3
add.d r4,r3
test_cc 0 0 0 0
checkr3 1fffe
moveq -1,r4
move.d r4,r3
add.d r4,r3
test_cc 1 0 0 1
checkr3 fffffffe
move.d 0x5432f789,r4
move.d 0x78134452,r3
add.d r4,r3
test_cc 1 0 1 0
checkr3 cc463bdb
moveq -1,r3
moveq 2,r4
add.w r4,r3
test_cc 0 0 0 1
checkr3 ffff0001
moveq 2,r3
moveq -1,r4
add.w r4,r3
test_cc 0 0 0 1
checkr3 1
move.d 0xffff,r4
move.d r4,r3
add.w r4,r3
test_cc 1 0 0 1
checkr3 fffe
move.d 0xfedaffff,r4
move.d r4,r3
add.w r4,r3
test_cc 1 0 0 1
checkr3 fedafffe
move.d 0x5432f789,r4
move.d 0x78134452,r3
add.w r4,r3
test_cc 0 0 0 1
checkr3 78133bdb
moveq -1,r3
moveq 2,r4
add.b r4,r3
test_cc 0 0 0 1
checkr3 ffffff01
moveq 2,r3
moveq -1,r4
add.b r4,r3
test_cc 0 0 0 1
checkr3 1
move.d 0xff,r4
move.d r4,r3
add.b r4,r3
test_cc 1 0 0 1
checkr3 fe
move.d 0xfeda49ff,r4
move.d r4,r3
add.b r4,r3
test_cc 1 0 0 1
checkr3 feda49fe
move.d 0x5432f789,r4
move.d 0x78134452,r3
add.b r4,r3
test_cc 1 0 0 0
checkr3 781344db
quit
+80
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@@ -0,0 +1,80 @@
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n
.include "testutils.inc"
start
moveq -1,r3
and.d 2,r3
test_move_cc 0 0 0 0
checkr3 2
moveq 2,r3
and.d -1,r3
test_move_cc 0 0 0 0
checkr3 2
move.d 0xffff,r3
and.d 0xffff,r3
test_move_cc 0 0 0 0
checkr3 ffff
moveq -1,r3
and.d -1,r3
test_move_cc 1 0 0 0
checkr3 ffffffff
move.d 0x78134452,r3
and.d 0x5432f789,r3
test_move_cc 0 0 0 0
checkr3 50124400
moveq -1,r3
and.w 2,r3
test_move_cc 0 0 0 0
checkr3 ffff0002
moveq 2,r3
and.w -1,r3
test_move_cc 0 0 0 0
checkr3 2
move.d 0xfffff,r3
and.w 0xffff,r3
test_move_cc 1 0 0 0
checkr3 fffff
move.d 0xfedaffaf,r3
and.w 0xff5f,r3
test_move_cc 1 0 0 0
checkr3 fedaff0f
move.d 0x78134452,r3
and.w 0xf789,r3
test_move_cc 0 0 0 0
checkr3 78134400
moveq -1,r3
and.b 2,r3
test_move_cc 0 0 0 0
checkr3 ffffff02
moveq 2,r3
and.b -1,r3
test_move_cc 0 0 0 0
checkr3 2
move.d 0xfa7,r3
and.b 0x5a,r3
test_move_cc 0 0 0 0
checkr3 f02
move.d 0x78134453,r3
and.b 0x89,r3
test_move_cc 0 0 0 0
checkr3 78134401
and.b 0,r3
test_move_cc 0 1 0 0
checkr3 78134400
quit
+90
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@@ -0,0 +1,90 @@
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n
.include "testutils.inc"
.data
x:
.dword 2,-1,0xffff,-1,0x5432f789
.word 2,-1,0xffff,0xff5f,0xf789
.byte 2,-1,0x5a,0x89,0
start
moveq -1,r3
move.d x,r5
and.d [r5+],r3
test_move_cc 0 0 0 0
checkr3 2
moveq 2,r3
and.d [r5],r3
test_move_cc 0 0 0 0
addq 4,r5
checkr3 2
move.d 0xffff,r3
and.d [r5+],r3
test_move_cc 0 0 0 0
checkr3 ffff
moveq -1,r3
and.d [r5+],r3
test_move_cc 1 0 0 0
checkr3 ffffffff
move.d 0x78134452,r3
and.d [r5+],r3
test_move_cc 0 0 0 0
checkr3 50124400
moveq -1,r3
and.w [r5+],r3
test_move_cc 0 0 0 0
checkr3 ffff0002
moveq 2,r3
and.w [r5+],r3
test_move_cc 0 0 0 0
checkr3 2
move.d 0xfffff,r3
and.w [r5],r3
test_move_cc 1 0 0 0
addq 2,r5
checkr3 fffff
move.d 0xfedaffaf,r3
and.w [r5+],r3
test_move_cc 1 0 0 0
checkr3 fedaff0f
move.d 0x78134452,r3
and.w [r5+],r3
test_move_cc 0 0 0 0
checkr3 78134400
moveq -1,r3
and.b [r5],r3
test_move_cc 0 0 0 0
addq 1,r5
checkr3 ffffff02
moveq 2,r3
and.b [r5+],r3
test_move_cc 0 0 0 0
checkr3 2
move.d 0xfa7,r3
and.b [r5+],r3
test_move_cc 0 0 0 0
checkr3 f02
move.d 0x78134453,r3
and.b [r5+],r3
test_move_cc 0 0 0 0
checkr3 78134401
and.b [r5],r3
test_move_cc 0 1 0 0
checkr3 78134400
quit
+46
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@@ -0,0 +1,46 @@
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\nffff\nffffffff\n1f\nffffffe0\n78134452\n0\n
.include "testutils.inc"
start
moveq -1,r3
andq 2,r3
test_move_cc 0 0 0 0
checkr3 2
moveq 2,r3
andq -1,r3
test_move_cc 0 0 0 0
checkr3 2
move.d 0xffff,r3
andq -1,r3
test_move_cc 0 0 0 0
checkr3 ffff
moveq -1,r3
andq -1,r3
test_move_cc 1 0 0 0
checkr3 ffffffff
moveq -1,r3
andq 31,r3
test_move_cc 0 0 0 0
checkr3 1f
moveq -1,r3
andq -32,r3
test_move_cc 1 0 0 0
checkr3 ffffffe0
move.d 0x78134457,r3
andq -14,r3
test_move_cc 0 0 0 0
checkr3 78134452
moveq 0,r3
andq -14,r3
test_move_cc 0 1 0 0
checkr3 0
quit
+95
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@@ -0,0 +1,95 @@
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
and.d r4,r3
test_move_cc 0 0 0 0
checkr3 2
moveq 2,r3
moveq -1,r4
and.d r4,r3
test_move_cc 0 0 0 0
checkr3 2
move.d 0xffff,r4
move.d r4,r3
and.d r4,r3
test_move_cc 0 0 0 0
checkr3 ffff
moveq -1,r4
move.d r4,r3
and.d r4,r3
test_move_cc 1 0 0 0
checkr3 ffffffff
move.d 0x5432f789,r4
move.d 0x78134452,r3
and.d r4,r3
test_move_cc 0 0 0 0
checkr3 50124400
moveq -1,r3
moveq 2,r4
and.w r4,r3
test_move_cc 0 0 0 0
checkr3 ffff0002
moveq 2,r3
moveq -1,r4
and.w r4,r3
test_move_cc 0 0 0 0
checkr3 2
move.d 0xfffff,r3
move.d 0xffff,r4
and.w r4,r3
test_move_cc 1 0 0 0
checkr3 fffff
move.d 0xfedaffaf,r3
move.d 0xff5f,r4
and.w r4,r3
test_move_cc 1 0 0 0
checkr3 fedaff0f
move.d 0x5432f789,r4
move.d 0x78134452,r3
and.w r4,r3
test_move_cc 0 0 0 0
checkr3 78134400
moveq -1,r3
moveq 2,r4
and.b r4,r3
test_move_cc 0 0 0 0
checkr3 ffffff02
moveq 2,r3
moveq -1,r4
and.b r4,r3
test_move_cc 0 0 0 0
checkr3 2
move.d 0x5a,r4
move.d 0xfa7,r3
and.b r4,r3
test_move_cc 0 0 0 0
checkr3 f02
move.d 0x5432f789,r4
move.d 0x78134453,r3
and.b r4,r3
test_move_cc 0 0 0 0
checkr3 78134401
moveq 0,r7
and.b r7,r3
test_move_cc 0 1 0 0
checkr3 78134400
quit

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