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target/sparc: Loosen decode of RDWIM for v7

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For v7, bits [18:0] are ignored.
For v8, bits [18:14] are reserved and bits [13:0] are ignored.

Fixes: 5d617bfba0 ("target/sparc: Move RDWIM, RDPR to decodetree")
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2025-09-23 16:51:11 -07:00
parent a0345f6283
commit dc9678cc97
1 changed files with 21 additions and 19 deletions
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target/sparc/insns.decode
+21 -19
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@@ -180,26 +180,28 @@ RESTORED 10 00001 110001 00000 0 0000000000000
# UA2005 INVALW
{
RDWIM 10 rd:5 101010 00000 0 0000000000000
RDPR_tpc 10 rd:5 101010 00000 0 0000000000000
[
RDPR_tpc 10 rd:5 101010 00000 0 0000000000000
RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000
RDPR_tstate 10 rd:5 101010 00010 0 0000000000000
RDPR_tt 10 rd:5 101010 00011 0 0000000000000
RDPR_tick 10 rd:5 101010 00100 0 0000000000000
RDPR_tba 10 rd:5 101010 00101 0 0000000000000
RDPR_pstate 10 rd:5 101010 00110 0 0000000000000
RDPR_tl 10 rd:5 101010 00111 0 0000000000000
RDPR_pil 10 rd:5 101010 01000 0 0000000000000
RDPR_cwp 10 rd:5 101010 01001 0 0000000000000
RDPR_cansave 10 rd:5 101010 01010 0 0000000000000
RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000
RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000
RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000
RDPR_wstate 10 rd:5 101010 01110 0 0000000000000
RDPR_gl 10 rd:5 101010 10000 0 0000000000000
RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000
RDPR_ver 10 rd:5 101010 11111 0 0000000000000
]
RDWIM 10 rd:5 101010 ----- - -------------
}
RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000
RDPR_tstate 10 rd:5 101010 00010 0 0000000000000
RDPR_tt 10 rd:5 101010 00011 0 0000000000000
RDPR_tick 10 rd:5 101010 00100 0 0000000000000
RDPR_tba 10 rd:5 101010 00101 0 0000000000000
RDPR_pstate 10 rd:5 101010 00110 0 0000000000000
RDPR_tl 10 rd:5 101010 00111 0 0000000000000
RDPR_pil 10 rd:5 101010 01000 0 0000000000000
RDPR_cwp 10 rd:5 101010 01001 0 0000000000000
RDPR_cansave 10 rd:5 101010 01010 0 0000000000000
RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000
RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000
RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000
RDPR_wstate 10 rd:5 101010 01110 0 0000000000000
RDPR_gl 10 rd:5 101010 10000 0 0000000000000
RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000
RDPR_ver 10 rd:5 101010 11111 0 0000000000000
{
WRWIM 10 00000 110010 ..... . ............. @n_r_ri