mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge tag 'pull-target-arm-20240305' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * raspi: Implement Broadcom Serial Controller (BSC) for BCM2835 boards * hw/char/pl011: Add support for loopback * STM32L4x5: Implement RCC clock control device * target/arm: Do memory type alignment checks * atomic.h: Reword confusing comment for qatomic_cmpxchg * qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmXnI4gZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3p5ED/wOtAHA3PK+WbQhVhnji3+k # gdhvVcldf+HLaI2v4tfaW152xjY80/j3PQFNkzptoXENA9U51F47oNYOIfULLZZX # FTKmw/mjTBc2LqJ8gLpS8Wkr/PFtDq9JJzDwZd0MwguXpzIJp31JJpESvXlAqjjv # FhuAcqNNuGwI2SXCBmp2lPoEMn8ExLDoG9rmzjxVZeZCyzUjVnJYM61ykhC4ByvK # j5+/a7pUcpgHSX5cbq7kFloPOx3JXI5lS6xUKhGXXk75qHRwiQIsxMcPq8PD1+ok # yrmp7cySwK8I7AlIPdDjpJmhU0OiBu+PkYiXmHlF2nvaUy6M0nVX2lSTzqj6VpVV # 7yYhvWXHrtIA9AUspqTRsX7tP7iMJkco7qWfKSzYl+3pTbxS4+rEoee4jNR3hqsU # lbWC47sNVtTN507qIL1dcsu+BaeSsYVftfxtFql3odTqRB+ticsjDfKg69dRSFyk # SS0t8Zy3TdomcEoQkAv/ZSpkQnQUGavbRumCG58lJdiTwTuJUmGi1ufKBrD/GeKj # IlDEl9yvKiR8uvdjj6EQqr5kOj09mmN5nvokNsq5a4aNXBYoesszWK2xodzXE2x5 # M9DHJ3S8xnN++p1idS2bikwEklG1XVQ/q52bDXQkUmQSNerVS1PCvg9hzYqA+x53 # ihJtMcsmGVfxY8aQHyHweA== # =isAe # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Mar 2024 13:52:08 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240305' of https://git.linaro.org/people/pmaydell/qemu-arm: qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports atomic.h: Reword confusing comment for qatomic_cmpxchg target/arm: Do memory type alignment check when translation enabled target/arm: Do memory type alignment check when translation disabled accel/tcg: Add TLB_CHECK_ALIGNED accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull exec/memattrs: Remove target_tlb_bit* target/arm: Support 32-byte alignment in pow2_align tests/qtest/stm32l4x5_rcc-test.c: Add tests for the STM32L4x5_RCC hw/arm/stm32l4x5_soc.c: Use the RCC Sysclk hw/misc/stm32l4x5_rcc: Add write protections to CR register hw/misc/stm32l4x5_rcc: Handle Register Updates hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexers hw/misc/stm32l4x5_rcc: Add an internal PLL Clock object hw/misc/stm32l4x5_rcc: Add an internal clock multiplexer object hw/misc/stm32l4x5_rcc: Implement STM32L4x5_RCC skeleton hw/char/pl011: Add support for loopback tests/qtest: Add testcase for BCM2835 BSC hw/arm: Connect BSC to BCM2835 board as I2C0, I2C1 and I2C2 hw/i2c: Implement Broadcom Serial Controller (BSC) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
+4
-1
@@ -1130,7 +1130,10 @@ M: Inès Varhol <ines.varhol@telecom-paris.fr>
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L: qemu-arm@nongnu.org
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S: Maintained
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F: hw/arm/stm32l4x5_soc.c
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F: include/hw/arm/stm32l4x5_soc.h
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F: hw/misc/stm32l4x5_exti.c
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F: hw/misc/stm32l4x5_syscfg.c
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F: hw/misc/stm32l4x5_rcc.c
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F: include/hw/*/stm32l4x5_*.h
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B-L475E-IOT01A IoT Node
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M: Arnaud Minier <arnaud.minier@telecom-paris.fr>
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+28
-7
@@ -1145,14 +1145,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
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" prot=%x idx=%d\n",
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addr, full->phys_addr, prot, mmu_idx);
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read_flags = 0;
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read_flags = full->tlb_fill_flags;
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if (full->lg_page_size < TARGET_PAGE_BITS) {
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/* Repeat the MMU check and TLB fill on every access. */
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read_flags |= TLB_INVALID_MASK;
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}
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if (full->attrs.byte_swap) {
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read_flags |= TLB_BSWAP;
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}
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is_ram = memory_region_is_ram(section->mr);
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is_romd = memory_region_is_romd(section->mr);
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@@ -1456,9 +1453,8 @@ static int probe_access_internal(CPUState *cpu, vaddr addr,
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flags |= full->slow_flags[access_type];
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/* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
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if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))
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||
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(access_type != MMU_INST_FETCH && force_mmio)) {
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if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY | TLB_CHECK_ALIGNED))
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|| (access_type != MMU_INST_FETCH && force_mmio)) {
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*phost = NULL;
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return TLB_MMIO;
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}
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@@ -1839,6 +1835,31 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi,
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tcg_debug_assert((flags & TLB_BSWAP) == 0);
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}
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/*
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* This alignment check differs from the one above, in that this is
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* based on the atomicity of the operation. The intended use case is
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* the ARM memory type field of each PTE, where access to pages with
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* Device memory type require alignment.
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*/
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if (unlikely(flags & TLB_CHECK_ALIGNED)) {
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MemOp size = l->memop & MO_SIZE;
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switch (l->memop & MO_ATOM_MASK) {
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case MO_ATOM_NONE:
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size = MO_8;
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break;
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case MO_ATOM_IFALIGN_PAIR:
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case MO_ATOM_WITHIN16_PAIR:
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size = size ? size - 1 : 0;
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break;
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default:
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break;
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}
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if (addr & ((1 << size) - 1)) {
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cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra);
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}
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}
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return crosspage;
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}
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@@ -17,13 +17,13 @@ Currently B-L475E-IOT01A machine's only supports the following devices:
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- Cortex-M4F based STM32L4x5 SoC
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- STM32L4x5 EXTI (Extended interrupts and events controller)
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- STM32L4x5 SYSCFG (System configuration controller)
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- STM32L4x5 RCC (Reset and clock control)
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Missing devices
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"""""""""""""""
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The B-L475E-IOT01A does *not* support the following devices:
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- Reset and clock control (RCC)
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- Serial ports (UART)
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- General-purpose I/Os (GPIO)
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- Analog to Digital Converter (ADC)
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@@ -35,6 +35,7 @@ Implemented devices
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* MailBox controller (MBOX)
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* VideoCore firmware (property)
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* Peripheral SPI controller (SPI)
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* Broadcom Serial Controller (I2C)
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Missing devices
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---------------
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@@ -438,6 +438,7 @@ config RASPI
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select SDHCI
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select USB_DWC2
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select BCM2835_SPI
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select BCM2835_I2C
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config STM32F100_SOC
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bool
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@@ -474,6 +475,7 @@ config STM32L4X5_SOC
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select OR_IRQ
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select STM32L4X5_SYSCFG
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select STM32L4X5_EXTI
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select STM32L4X5_RCC
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config XLNX_ZYNQMP_ARM
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bool
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@@ -26,27 +26,19 @@
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-clock.h"
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#include "qemu/error-report.h"
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#include "hw/arm/stm32l4x5_soc.h"
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#include "hw/arm/boot.h"
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/* Main SYSCLK frequency in Hz (80MHz) */
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#define MAIN_SYSCLK_FREQ_HZ 80000000ULL
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/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
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static void b_l475e_iot01a_init(MachineState *machine)
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{
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const Stm32l4x5SocClass *sc;
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DeviceState *dev;
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Clock *sysclk;
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/* This clock doesn't need migration because it is fixed-frequency */
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sysclk = clock_new(OBJECT(machine), "SYSCLK");
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clock_set_hz(sysclk, MAIN_SYSCLK_FREQ_HZ);
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dev = qdev_new(TYPE_STM32L4X5XG_SOC);
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object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
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qdev_connect_clock_in(dev, "sysclk", sysclk);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sc = STM32L4X5_SOC_GET_CLASS(dev);
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@@ -30,6 +30,9 @@
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#define SEPARATE_DMA_IRQ_MAX 10
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#define ORGATED_DMA_IRQ_COUNT 4
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/* All three I2C controllers share the same IRQ */
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#define ORGATED_I2C_IRQ_COUNT 3
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void create_unimp(BCMSocPeripheralBaseState *ps,
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UnimplementedDeviceState *uds,
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const char *name, hwaddr ofs, hwaddr size)
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@@ -157,6 +160,19 @@ static void raspi_peripherals_base_init(Object *obj)
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/* SPI */
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object_initialize_child(obj, "bcm2835-spi0", &s->spi[0],
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TYPE_BCM2835_SPI);
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/* I2C */
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object_initialize_child(obj, "bcm2835-i2c0", &s->i2c[0],
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TYPE_BCM2835_I2C);
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object_initialize_child(obj, "bcm2835-i2c1", &s->i2c[1],
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TYPE_BCM2835_I2C);
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object_initialize_child(obj, "bcm2835-i2c2", &s->i2c[2],
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TYPE_BCM2835_I2C);
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object_initialize_child(obj, "orgated-i2c-irq",
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&s->orgated_i2c_irq, TYPE_OR_IRQ);
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object_property_set_int(OBJECT(&s->orgated_i2c_irq), "num-lines",
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ORGATED_I2C_IRQ_COUNT, &error_abort);
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}
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static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
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@@ -453,14 +469,37 @@ void bcm_soc_peripherals_common_realize(DeviceState *dev, Error **errp)
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BCM2835_IC_GPU_IRQ,
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INTERRUPT_SPI));
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/* I2C */
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for (n = 0; n < 3; n++) {
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[n]), errp)) {
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return;
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}
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}
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memory_region_add_subregion(&s->peri_mr, BSC0_OFFSET,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[0]), 0));
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memory_region_add_subregion(&s->peri_mr, BSC1_OFFSET,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[1]), 0));
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memory_region_add_subregion(&s->peri_mr, BSC2_OFFSET,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[2]), 0));
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if (!qdev_realize(DEVICE(&s->orgated_i2c_irq), NULL, errp)) {
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return;
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}
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for (n = 0; n < ORGATED_I2C_IRQ_COUNT; n++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[n]), 0,
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qdev_get_gpio_in(DEVICE(&s->orgated_i2c_irq), n));
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}
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qdev_connect_gpio_out(DEVICE(&s->orgated_i2c_irq), 0,
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qdev_get_gpio_in_named(DEVICE(&s->ic),
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BCM2835_IC_GPU_IRQ,
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INTERRUPT_I2C));
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create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
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create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
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create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
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create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
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create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100);
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create_unimp(s, &s->i2c[0], "bcm2835-i2c0", BSC0_OFFSET, 0x20);
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create_unimp(s, &s->i2c[1], "bcm2835-i2c1", BSC1_OFFSET, 0x20);
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create_unimp(s, &s->i2c[2], "bcm2835-i2c2", BSC2_OFFSET, 0x20);
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create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
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create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
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create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
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+15
-30
@@ -76,6 +76,8 @@ static const int exti_irq[NUM_EXTI_IRQ] = {
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-1, -1, -1, -1, /* PVM[1..4] OR gate 1 */
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78 /* LCD wakeup, Direct */
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};
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#define RCC_BASE_ADDRESS 0x40021000
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#define RCC_IRQ 5
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static const int exti_or_gates_out[NUM_EXTI_OR_GATES] = {
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23, 40, 63, 1,
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@@ -107,9 +109,7 @@ static void stm32l4x5_soc_initfn(Object *obj)
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TYPE_OR_IRQ);
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}
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object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
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s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
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s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
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object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);
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}
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static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
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@@ -121,30 +121,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
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DeviceState *armv7m;
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SysBusDevice *busdev;
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||||
|
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/*
|
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* We use s->refclk internally and only define it with qdev_init_clock_in()
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* so it is correctly parented and not leaked on an init/deinit; it is not
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||||
* intended as an externally exposed clock.
|
||||
*/
|
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if (clock_has_source(s->refclk)) {
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error_setg(errp, "refclk clock must not be wired up by the board code");
|
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return;
|
||||
}
|
||||
|
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if (!clock_has_source(s->sysclk)) {
|
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error_setg(errp, "sysclk clock must be wired up by the board code");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* TODO: ideally we should model the SoC RCC and its ability to
|
||||
* change the sysclk frequency and define different sysclk sources.
|
||||
*/
|
||||
|
||||
/* The refclk always runs at frequency HCLK / 8 */
|
||||
clock_set_mul_div(s->refclk, 8, 1);
|
||||
clock_set_source(s->refclk, s->sysclk);
|
||||
|
||||
if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
|
||||
sc->flash_size, errp)) {
|
||||
return;
|
||||
@@ -174,8 +150,10 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
|
||||
qdev_prop_set_uint32(armv7m, "num-prio-bits", 4);
|
||||
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
|
||||
qdev_prop_set_bit(armv7m, "enable-bitband", true);
|
||||
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
|
||||
qdev_connect_clock_in(armv7m, "refclk", s->refclk);
|
||||
qdev_connect_clock_in(armv7m, "cpuclk",
|
||||
qdev_get_clock_out(DEVICE(&(s->rcc)), "cortex-fclk-out"));
|
||||
qdev_connect_clock_in(armv7m, "refclk",
|
||||
qdev_get_clock_out(DEVICE(&(s->rcc)), "cortex-refclk-out"));
|
||||
object_property_set_link(OBJECT(&s->armv7m), "memory",
|
||||
OBJECT(system_memory), &error_abort);
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
|
||||
@@ -244,6 +222,14 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
|
||||
qdev_get_gpio_in(DEVICE(&s->exti), i));
|
||||
}
|
||||
|
||||
/* RCC device */
|
||||
busdev = SYS_BUS_DEVICE(&s->rcc);
|
||||
if (!sysbus_realize(busdev, errp)) {
|
||||
return;
|
||||
}
|
||||
sysbus_mmio_map(busdev, 0, RCC_BASE_ADDRESS);
|
||||
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, RCC_IRQ));
|
||||
|
||||
/* APB1 BUS */
|
||||
create_unimplemented_device("TIM2", 0x40000000, 0x400);
|
||||
create_unimplemented_device("TIM3", 0x40000400, 0x400);
|
||||
@@ -306,7 +292,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
|
||||
create_unimplemented_device("DMA1", 0x40020000, 0x400);
|
||||
create_unimplemented_device("DMA2", 0x40020400, 0x400);
|
||||
/* RESERVED: 0x40020800, 0x800 */
|
||||
create_unimplemented_device("RCC", 0x40021000, 0x400);
|
||||
/* RESERVED: 0x40021400, 0xC00 */
|
||||
create_unimplemented_device("FLASH", 0x40022000, 0x400);
|
||||
/* RESERVED: 0x40022400, 0xC00 */
|
||||
|
||||
+108
-2
@@ -49,10 +49,14 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
|
||||
}
|
||||
|
||||
/* Flag Register, UARTFR */
|
||||
#define PL011_FLAG_RI 0x100
|
||||
#define PL011_FLAG_TXFE 0x80
|
||||
#define PL011_FLAG_RXFF 0x40
|
||||
#define PL011_FLAG_TXFF 0x20
|
||||
#define PL011_FLAG_RXFE 0x10
|
||||
#define PL011_FLAG_DCD 0x04
|
||||
#define PL011_FLAG_DSR 0x02
|
||||
#define PL011_FLAG_CTS 0x01
|
||||
|
||||
/* Data Register, UARTDR */
|
||||
#define DR_BE (1 << 10)
|
||||
@@ -76,6 +80,13 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
|
||||
#define LCR_FEN (1 << 4)
|
||||
#define LCR_BRK (1 << 0)
|
||||
|
||||
/* Control Register, UARTCR */
|
||||
#define CR_OUT2 (1 << 13)
|
||||
#define CR_OUT1 (1 << 12)
|
||||
#define CR_RTS (1 << 11)
|
||||
#define CR_DTR (1 << 10)
|
||||
#define CR_LBE (1 << 7)
|
||||
|
||||
static const unsigned char pl011_id_arm[8] =
|
||||
{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
|
||||
static const unsigned char pl011_id_luminary[8] =
|
||||
@@ -251,6 +262,89 @@ static void pl011_trace_baudrate_change(const PL011State *s)
|
||||
s->ibrd, s->fbrd);
|
||||
}
|
||||
|
||||
static bool pl011_loopback_enabled(PL011State *s)
|
||||
{
|
||||
return !!(s->cr & CR_LBE);
|
||||
}
|
||||
|
||||
static void pl011_loopback_mdmctrl(PL011State *s)
|
||||
{
|
||||
uint32_t cr, fr, il;
|
||||
|
||||
if (!pl011_loopback_enabled(s)) {
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Loopback software-driven modem control outputs to modem status inputs:
|
||||
* FR.RI <= CR.Out2
|
||||
* FR.DCD <= CR.Out1
|
||||
* FR.CTS <= CR.RTS
|
||||
* FR.DSR <= CR.DTR
|
||||
*
|
||||
* The loopback happens immediately even if this call is triggered
|
||||
* by setting only CR.LBE.
|
||||
*
|
||||
* CTS/RTS updates due to enabled hardware flow controls are not
|
||||
* dealt with here.
|
||||
*/
|
||||
cr = s->cr;
|
||||
fr = s->flags & ~(PL011_FLAG_RI | PL011_FLAG_DCD |
|
||||
PL011_FLAG_DSR | PL011_FLAG_CTS);
|
||||
fr |= (cr & CR_OUT2) ? PL011_FLAG_RI : 0;
|
||||
fr |= (cr & CR_OUT1) ? PL011_FLAG_DCD : 0;
|
||||
fr |= (cr & CR_RTS) ? PL011_FLAG_CTS : 0;
|
||||
fr |= (cr & CR_DTR) ? PL011_FLAG_DSR : 0;
|
||||
|
||||
/* Change interrupts based on updated FR */
|
||||
il = s->int_level & ~(INT_DSR | INT_DCD | INT_CTS | INT_RI);
|
||||
il |= (fr & PL011_FLAG_DSR) ? INT_DSR : 0;
|
||||
il |= (fr & PL011_FLAG_DCD) ? INT_DCD : 0;
|
||||
il |= (fr & PL011_FLAG_CTS) ? INT_CTS : 0;
|
||||
il |= (fr & PL011_FLAG_RI) ? INT_RI : 0;
|
||||
|
||||
s->flags = fr;
|
||||
s->int_level = il;
|
||||
pl011_update(s);
|
||||
}
|
||||
|
||||
static void pl011_put_fifo(void *opaque, uint32_t value);
|
||||
|
||||
static void pl011_loopback_tx(PL011State *s, uint32_t value)
|
||||
{
|
||||
if (!pl011_loopback_enabled(s)) {
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Caveat:
|
||||
*
|
||||
* In real hardware, TX loopback happens at the serial-bit level
|
||||
* and then reassembled by the RX logics back into bytes and placed
|
||||
* into the RX fifo. That is, loopback happens after TX fifo.
|
||||
*
|
||||
* Because the real hardware TX fifo is time-drained at the frame
|
||||
* rate governed by the configured serial format, some loopback
|
||||
* bytes in TX fifo may still be able to get into the RX fifo
|
||||
* that could be full at times while being drained at software
|
||||
* pace.
|
||||
*
|
||||
* In such scenario, the RX draining pace is the major factor
|
||||
* deciding which loopback bytes get into the RX fifo, unless
|
||||
* hardware flow-control is enabled.
|
||||
*
|
||||
* For simplicity, the above described is not emulated.
|
||||
*/
|
||||
pl011_put_fifo(s, value);
|
||||
}
|
||||
|
||||
static void pl011_loopback_break(PL011State *s, int brk_enable)
|
||||
{
|
||||
if (brk_enable) {
|
||||
pl011_loopback_tx(s, DR_BE);
|
||||
}
|
||||
}
|
||||
|
||||
static void pl011_write(void *opaque, hwaddr offset,
|
||||
uint64_t value, unsigned size)
|
||||
{
|
||||
@@ -266,6 +360,7 @@ static void pl011_write(void *opaque, hwaddr offset,
|
||||
/* XXX this blocks entire thread. Rewrite to use
|
||||
* qemu_chr_fe_write and background I/O callbacks */
|
||||
qemu_chr_fe_write_all(&s->chr, &ch, 1);
|
||||
pl011_loopback_tx(s, ch);
|
||||
s->int_level |= INT_TX;
|
||||
pl011_update(s);
|
||||
break;
|
||||
@@ -295,13 +390,15 @@ static void pl011_write(void *opaque, hwaddr offset,
|
||||
int break_enable = value & LCR_BRK;
|
||||
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
|
||||
&break_enable);
|
||||
pl011_loopback_break(s, break_enable);
|
||||
}
|
||||
s->lcr = value;
|
||||
pl011_set_read_trigger(s);
|
||||
break;
|
||||
case 12: /* UARTCR */
|
||||
/* ??? Need to implement the enable and loopback bits. */
|
||||
/* ??? Need to implement the enable bit. */
|
||||
s->cr = value;
|
||||
pl011_loopback_mdmctrl(s);
|
||||
break;
|
||||
case 13: /* UARTIFS */
|
||||
s->ifl = value;
|
||||
@@ -361,12 +458,21 @@ static void pl011_put_fifo(void *opaque, uint32_t value)
|
||||
|
||||
static void pl011_receive(void *opaque, const uint8_t *buf, int size)
|
||||
{
|
||||
/*
|
||||
* In loopback mode, the RX input signal is internally disconnected
|
||||
* from the entire receiving logics; thus, all inputs are ignored,
|
||||
* and BREAK detection on RX input signal is also not performed.
|
||||
*/
|
||||
if (pl011_loopback_enabled(opaque)) {
|
||||
return;
|
||||
}
|
||||
|
||||
pl011_put_fifo(opaque, *buf);
|
||||
}
|
||||
|
||||
static void pl011_event(void *opaque, QEMUChrEvent event)
|
||||
{
|
||||
if (event == CHR_EVENT_BREAK) {
|
||||
if (event == CHR_EVENT_BREAK && !pl011_loopback_enabled(opaque)) {
|
||||
pl011_put_fifo(opaque, DR_BE);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -45,3 +45,7 @@ config PCA954X
|
||||
config PMBUS
|
||||
bool
|
||||
select SMBUS
|
||||
|
||||
config BCM2835_I2C
|
||||
bool
|
||||
select I2C
|
||||
|
||||
@@ -0,0 +1,282 @@
|
||||
/*
|
||||
* Broadcom Serial Controller (BSC)
|
||||
*
|
||||
* Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qemu/log.h"
|
||||
#include "hw/i2c/bcm2835_i2c.h"
|
||||
#include "hw/irq.h"
|
||||
#include "migration/vmstate.h"
|
||||
|
||||
static void bcm2835_i2c_update_interrupt(BCM2835I2CState *s)
|
||||
{
|
||||
int do_interrupt = 0;
|
||||
/* Interrupt on RXR (Needs reading) */
|
||||
if (s->c & BCM2835_I2C_C_INTR && s->s & BCM2835_I2C_S_RXR) {
|
||||
do_interrupt = 1;
|
||||
}
|
||||
|
||||
/* Interrupt on TXW (Needs writing) */
|
||||
if (s->c & BCM2835_I2C_C_INTT && s->s & BCM2835_I2C_S_TXW) {
|
||||
do_interrupt = 1;
|
||||
}
|
||||
|
||||
/* Interrupt on DONE (Transfer complete) */
|
||||
if (s->c & BCM2835_I2C_C_INTD && s->s & BCM2835_I2C_S_DONE) {
|
||||
do_interrupt = 1;
|
||||
}
|
||||
qemu_set_irq(s->irq, do_interrupt);
|
||||
}
|
||||
|
||||
static void bcm2835_i2c_begin_transfer(BCM2835I2CState *s)
|
||||
{
|
||||
int direction = s->c & BCM2835_I2C_C_READ;
|
||||
if (i2c_start_transfer(s->bus, s->a, direction)) {
|
||||
s->s |= BCM2835_I2C_S_ERR;
|
||||
}
|
||||
s->s |= BCM2835_I2C_S_TA;
|
||||
|
||||
if (direction) {
|
||||
s->s |= BCM2835_I2C_S_RXR | BCM2835_I2C_S_RXD;
|
||||
} else {
|
||||
s->s |= BCM2835_I2C_S_TXW;
|
||||
}
|
||||
}
|
||||
|
||||
static void bcm2835_i2c_finish_transfer(BCM2835I2CState *s)
|
||||
{
|
||||
/*
|
||||
* STOP is sent when DLEN counts down to zero.
|
||||
*
|
||||
* https://github.com/torvalds/linux/blob/v6.7/drivers/i2c/busses/i2c-bcm2835.c#L223-L261
|
||||
* It is possible to initiate repeated starts on real hardware.
|
||||
* However, this requires sending another ST request before the bytes in
|
||||
* TX FIFO are shifted out.
|
||||
*
|
||||
* This is not emulated currently.
|
||||
*/
|
||||
i2c_end_transfer(s->bus);
|
||||
s->s |= BCM2835_I2C_S_DONE;
|
||||
|
||||
/* Ensure RXD is cleared, otherwise the driver registers an error */
|
||||
s->s &= ~(BCM2835_I2C_S_TA | BCM2835_I2C_S_RXR |
|
||||
BCM2835_I2C_S_TXW | BCM2835_I2C_S_RXD);
|
||||
}
|
||||
|
||||
static uint64_t bcm2835_i2c_read(void *opaque, hwaddr addr, unsigned size)
|
||||
{
|
||||
BCM2835I2CState *s = opaque;
|
||||
uint32_t readval = 0;
|
||||
|
||||
switch (addr) {
|
||||
case BCM2835_I2C_C:
|
||||
readval = s->c;
|
||||
break;
|
||||
case BCM2835_I2C_S:
|
||||
readval = s->s;
|
||||
break;
|
||||
case BCM2835_I2C_DLEN:
|
||||
readval = s->dlen;
|
||||
break;
|
||||
case BCM2835_I2C_A:
|
||||
readval = s->a;
|
||||
break;
|
||||
case BCM2835_I2C_FIFO:
|
||||
/* We receive I2C messages directly instead of using FIFOs */
|
||||
if (s->s & BCM2835_I2C_S_TA) {
|
||||
readval = i2c_recv(s->bus);
|
||||
s->dlen -= 1;
|
||||
|
||||
if (s->dlen == 0) {
|
||||
bcm2835_i2c_finish_transfer(s);
|
||||
}
|
||||
}
|
||||
bcm2835_i2c_update_interrupt(s);
|
||||
break;
|
||||
case BCM2835_I2C_DIV:
|
||||
readval = s->div;
|
||||
break;
|
||||
case BCM2835_I2C_DEL:
|
||||
readval = s->del;
|
||||
break;
|
||||
case BCM2835_I2C_CLKT:
|
||||
readval = s->clkt;
|
||||
break;
|
||||
default:
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
|
||||
}
|
||||
|
||||
return readval;
|
||||
}
|
||||
|
||||
static void bcm2835_i2c_write(void *opaque, hwaddr addr,
|
||||
uint64_t value, unsigned int size)
|
||||
{
|
||||
BCM2835I2CState *s = opaque;
|
||||
uint32_t writeval = value;
|
||||
|
||||
switch (addr) {
|
||||
case BCM2835_I2C_C:
|
||||
/* ST is a one-shot operation; it must read back as 0 */
|
||||
s->c = writeval & ~BCM2835_I2C_C_ST;
|
||||
|
||||
/* Start transfer */
|
||||
if (writeval & (BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN)) {
|
||||
bcm2835_i2c_begin_transfer(s);
|
||||
/*
|
||||
* Handle special case where transfer starts with zero data length.
|
||||
* Required for zero length i2c quick messages to work.
|
||||
*/
|
||||
if (s->dlen == 0) {
|
||||
bcm2835_i2c_finish_transfer(s);
|
||||
}
|
||||
}
|
||||
|
||||
bcm2835_i2c_update_interrupt(s);
|
||||
break;
|
||||
case BCM2835_I2C_S:
|
||||
if (writeval & BCM2835_I2C_S_DONE && s->s & BCM2835_I2C_S_DONE) {
|
||||
/* When DONE is cleared, DLEN should read last written value. */
|
||||
s->dlen = s->last_dlen;
|
||||
}
|
||||
|
||||
/* Clear DONE, CLKT and ERR by writing 1 */
|
||||
s->s &= ~(writeval & (BCM2835_I2C_S_DONE |
|
||||
BCM2835_I2C_S_ERR | BCM2835_I2C_S_CLKT));
|
||||
break;
|
||||
case BCM2835_I2C_DLEN:
|
||||
s->dlen = writeval;
|
||||
s->last_dlen = writeval;
|
||||
break;
|
||||
case BCM2835_I2C_A:
|
||||
s->a = writeval;
|
||||
break;
|
||||
case BCM2835_I2C_FIFO:
|
||||
/* We send I2C messages directly instead of using FIFOs */
|
||||
if (s->s & BCM2835_I2C_S_TA) {
|
||||
if (s->s & BCM2835_I2C_S_TXD) {
|
||||
if (!i2c_send(s->bus, writeval & 0xff)) {
|
||||
s->dlen -= 1;
|
||||
} else {
|
||||
s->s |= BCM2835_I2C_S_ERR;
|
||||
}
|
||||
}
|
||||
|
||||
if (s->dlen == 0) {
|
||||
bcm2835_i2c_finish_transfer(s);
|
||||
}
|
||||
}
|
||||
bcm2835_i2c_update_interrupt(s);
|
||||
break;
|
||||
case BCM2835_I2C_DIV:
|
||||
s->div = writeval;
|
||||
break;
|
||||
case BCM2835_I2C_DEL:
|
||||
s->del = writeval;
|
||||
break;
|
||||
case BCM2835_I2C_CLKT:
|
||||
s->clkt = writeval;
|
||||
break;
|
||||
default:
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
|
||||
}
|
||||
}
|
||||
|
||||
static const MemoryRegionOps bcm2835_i2c_ops = {
|
||||
.read = bcm2835_i2c_read,
|
||||
.write = bcm2835_i2c_write,
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
},
|
||||
};
|
||||
|
||||
static void bcm2835_i2c_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
BCM2835I2CState *s = BCM2835_I2C(dev);
|
||||
s->bus = i2c_init_bus(dev, NULL);
|
||||
|
||||
memory_region_init_io(&s->iomem, OBJECT(dev), &bcm2835_i2c_ops, s,
|
||||
TYPE_BCM2835_I2C, 0x24);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
|
||||
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
|
||||
}
|
||||
|
||||
static void bcm2835_i2c_reset(DeviceState *dev)
|
||||
{
|
||||
BCM2835I2CState *s = BCM2835_I2C(dev);
|
||||
|
||||
/* Reset values according to BCM2835 Peripheral Documentation */
|
||||
s->c = 0x0;
|
||||
s->s = BCM2835_I2C_S_TXD | BCM2835_I2C_S_TXE;
|
||||
s->dlen = 0x0;
|
||||
s->a = 0x0;
|
||||
s->div = 0x5dc;
|
||||
s->del = 0x00300030;
|
||||
s->clkt = 0x40;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_bcm2835_i2c = {
|
||||
.name = TYPE_BCM2835_I2C,
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (const VMStateField[]) {
|
||||
VMSTATE_UINT32(c, BCM2835I2CState),
|
||||
VMSTATE_UINT32(s, BCM2835I2CState),
|
||||
VMSTATE_UINT32(dlen, BCM2835I2CState),
|
||||
VMSTATE_UINT32(a, BCM2835I2CState),
|
||||
VMSTATE_UINT32(div, BCM2835I2CState),
|
||||
VMSTATE_UINT32(del, BCM2835I2CState),
|
||||
VMSTATE_UINT32(clkt, BCM2835I2CState),
|
||||
VMSTATE_UINT32(last_dlen, BCM2835I2CState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static void bcm2835_i2c_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->reset = bcm2835_i2c_reset;
|
||||
dc->realize = bcm2835_i2c_realize;
|
||||
dc->vmsd = &vmstate_bcm2835_i2c;
|
||||
}
|
||||
|
||||
static const TypeInfo bcm2835_i2c_info = {
|
||||
.name = TYPE_BCM2835_I2C,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(BCM2835I2CState),
|
||||
.class_init = bcm2835_i2c_class_init,
|
||||
};
|
||||
|
||||
static void bcm2835_i2c_register_types(void)
|
||||
{
|
||||
type_register_static(&bcm2835_i2c_info);
|
||||
}
|
||||
|
||||
type_init(bcm2835_i2c_register_types)
|
||||
@@ -17,4 +17,5 @@ i2c_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_i2c.c'))
|
||||
i2c_ss.add(when: 'CONFIG_PPC4XX', if_true: files('ppc4xx_i2c.c'))
|
||||
i2c_ss.add(when: 'CONFIG_PCA954X', if_true: files('i2c_mux_pca954x.c'))
|
||||
i2c_ss.add(when: 'CONFIG_PMBUS', if_true: files('pmbus_device.c'))
|
||||
i2c_ss.add(when: 'CONFIG_BCM2835_I2C', if_true: files('bcm2835_i2c.c'))
|
||||
system_ss.add_all(when: 'CONFIG_I2C', if_true: i2c_ss)
|
||||
|
||||
@@ -97,6 +97,9 @@ config STM32L4X5_EXTI
|
||||
config STM32L4X5_SYSCFG
|
||||
bool
|
||||
|
||||
config STM32L4X5_RCC
|
||||
bool
|
||||
|
||||
config MIPS_ITU
|
||||
bool
|
||||
|
||||
|
||||
@@ -113,6 +113,7 @@ system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.
|
||||
system_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))
|
||||
system_ss.add(when: 'CONFIG_STM32L4X5_EXTI', if_true: files('stm32l4x5_exti.c'))
|
||||
system_ss.add(when: 'CONFIG_STM32L4X5_SYSCFG', if_true: files('stm32l4x5_syscfg.c'))
|
||||
system_ss.add(when: 'CONFIG_STM32L4X5_RCC', if_true: files('stm32l4x5_rcc.c'))
|
||||
system_ss.add(when: 'CONFIG_MPS2_FPGAIO', if_true: files('mps2-fpgaio.c'))
|
||||
system_ss.add(when: 'CONFIG_MPS2_SCC', if_true: files('mps2-scc.c'))
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -174,6 +174,20 @@ stm32l4x5_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
|
||||
stm32l4x5_exti_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
|
||||
stm32l4x5_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
|
||||
|
||||
# stm32l4x5_rcc.c
|
||||
stm32l4x5_rcc_read(uint64_t addr, uint32_t data) "RCC: Read <0x%" PRIx64 "> -> 0x%" PRIx32
|
||||
stm32l4x5_rcc_write(uint64_t addr, uint32_t data) "RCC: Write <0x%" PRIx64 "> <- 0x%" PRIx32
|
||||
stm32l4x5_rcc_mux_enable(uint32_t mux_id) "RCC: Mux %d enabled"
|
||||
stm32l4x5_rcc_mux_disable(uint32_t mux_id) "RCC: Mux %d disabled"
|
||||
stm32l4x5_rcc_mux_set_factor(uint32_t mux_id, uint32_t old_multiplier, uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider) "RCC: Mux %d factor changed: multiplier (%u -> %u), divider (%u -> %u)"
|
||||
stm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src) "RCC: Mux %d source changed: from %u to %u"
|
||||
stm32l4x5_rcc_mux_update(uint32_t mux_id, uint32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider) "RCC: Mux %d src %d update: src_freq %" PRIu64 " multiplier %" PRIu32 " divider %" PRIu32
|
||||
stm32l4x5_rcc_pll_set_vco_multiplier(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) "RCC: PLL %u: vco_multiplier changed (%u -> %u)"
|
||||
stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u enabled"
|
||||
stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u disabled"
|
||||
stm32l4x5_rcc_pll_set_channel_divider(uint32_t pll_id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider) "RCC: PLL %u, channel %u: divider changed (%u -> %u)"
|
||||
stm32l4x5_rcc_pll_update(uint32_t pll_id, uint32_t channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq) "RCC: PLL %d channel %d update: vco_freq %" PRIu64 " old_freq %" PRIu64 " new_freq %" PRIu64
|
||||
|
||||
# tz-mpc.c
|
||||
tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
|
||||
tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
|
||||
|
||||
@@ -357,8 +357,10 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
|
||||
#define TLB_BSWAP (1 << 0)
|
||||
/* Set if TLB entry contains a watchpoint. */
|
||||
#define TLB_WATCHPOINT (1 << 1)
|
||||
/* Set if TLB entry requires aligned accesses. */
|
||||
#define TLB_CHECK_ALIGNED (1 << 2)
|
||||
|
||||
#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT)
|
||||
#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED)
|
||||
|
||||
/* The two sets of flags must not overlap. */
|
||||
QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
|
||||
|
||||
@@ -52,18 +52,6 @@ typedef struct MemTxAttrs {
|
||||
unsigned int memory:1;
|
||||
/* Requester ID (for MSI for example) */
|
||||
unsigned int requester_id:16;
|
||||
/* Invert endianness for this page */
|
||||
unsigned int byte_swap:1;
|
||||
/*
|
||||
* The following are target-specific page-table bits. These are not
|
||||
* related to actual memory transactions at all. However, this structure
|
||||
* is part of the tlb_fill interface, cached in the cputlb structure,
|
||||
* and has unused bits. These fields will be read by target-specific
|
||||
* helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN.
|
||||
*/
|
||||
unsigned int target_tlb_bit0 : 1;
|
||||
unsigned int target_tlb_bit1 : 1;
|
||||
unsigned int target_tlb_bit2 : 1;
|
||||
} MemTxAttrs;
|
||||
|
||||
/* Bus masters which don't specify any attributes will get this,
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
#include "hw/timer/bcm2835_systmr.h"
|
||||
#include "hw/usb/hcd-dwc2.h"
|
||||
#include "hw/ssi/bcm2835_spi.h"
|
||||
#include "hw/i2c/bcm2835_i2c.h"
|
||||
#include "hw/misc/unimp.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
@@ -68,7 +69,8 @@ struct BCMSocPeripheralBaseState {
|
||||
BCM2835SDHostState sdhost;
|
||||
UnimplementedDeviceState i2s;
|
||||
BCM2835SPIState spi[1];
|
||||
UnimplementedDeviceState i2c[3];
|
||||
BCM2835I2CState i2c[3];
|
||||
OrIRQState orgated_i2c_irq;
|
||||
UnimplementedDeviceState otp;
|
||||
UnimplementedDeviceState dbus;
|
||||
UnimplementedDeviceState ave0;
|
||||
|
||||
@@ -29,6 +29,7 @@
|
||||
#include "hw/or-irq.h"
|
||||
#include "hw/misc/stm32l4x5_syscfg.h"
|
||||
#include "hw/misc/stm32l4x5_exti.h"
|
||||
#include "hw/misc/stm32l4x5_rcc.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
|
||||
@@ -47,14 +48,12 @@ struct Stm32l4x5SocState {
|
||||
Stm32l4x5ExtiState exti;
|
||||
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
|
||||
Stm32l4x5SyscfgState syscfg;
|
||||
Stm32l4x5RccState rcc;
|
||||
|
||||
MemoryRegion sram1;
|
||||
MemoryRegion sram2;
|
||||
MemoryRegion flash;
|
||||
MemoryRegion flash_alias;
|
||||
|
||||
Clock *sysclk;
|
||||
Clock *refclk;
|
||||
};
|
||||
|
||||
struct Stm32l4x5SocClass {
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user