izzy/xemu
0
0
Fork 0
mirror of https://github.com/izzy2lost/xemu.git synced 2026-07-06 00:20:22 -07:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu into staging

Browse Source 
Misc HW patch queue

- Remove unused MIPS SAAR* registers (Phil)
- Remove warning when testing the TC58128 NAND EEPROM (Peter)
- KConfig cleanups around ISA SuperI/O and MIPS (Paolo)
- QDev API uses sanitization (Philippe)
- Split AHCI model as PCI / SysBus (Philippe)
- Add SMP support to SPARC Leon3 board (Clément)

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmXOUD4ACgkQ4+MsLN6t
# wN6gWRAAjf+6Z9VUvvHqZoaSJW49k+GRUelTI2tyN+eGfetAx9dk8aIbpbV1X12d
# pc56jsSi6ICT7baCegtxHszhYJr2e9A2QLCAOJt+Oz87kEGes3ONVVKAk7pwjKxt
# m8pmU3uXWgFvU6PoFBhGBa6LiZBulgLNXBUwzmEhc9PpPkR49ULdDp/qxtWvxOV5
# xYBktFlkiT+AvHq3QWCnDIaw+pH5ghEq9BI4xFOvvvqSqdHEqsGAaiKPa9Po0Gfz
# Ap9qsm4FxKxhGoeQWtAIP8TvN3pFFSXMysziP6Xt1rffKsvF9ioghGKRM6BgQfqD
# ZetjcFbcf7dQu3zZVy8ljYcymMxfZcWWVVq4CMC68lPQE97hz1CT3PJjgd77dKfi
# z60uRkOGaiPW5iIGT9+vdQxZ5K3HivKyjuHOdV8V4HnWO3oqgfDtNHn5RKed0qUg
# g1FoWriJGsDixdx1vd0EoH2/oTxy4HIsFv7a1OjiZyBLjO+EeEZ3+H9pqUHqBxva
# +Dv70z9F1sv5dzcUXH+oCgTbnKlJ90Q+e3vj0wGdlBncVsgIwbtgqYelhUEl+xJX
# Mu6KNUo5ANVP38ZKG0GSMCZHfcUjc5s+5rG55NbTN0HiF56a6D2KlQAuXdUsGE1J
# 7i4cwipJmfxzbdPDlSb3kBxm5pFexEk6nROF9kTHQj3ZBMMvIls=
# =nOX+
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 15 Feb 2024 17:56:14 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20240215' of https://github.com/philmd/qemu: (56 commits)
  hw/ide/ich9: Use AHCIPCIState typedef
  hw/ide/ahci: Move SysBus definitions to 'ahci-sysbus.h'
  hw/ide/ahci: Remove SysbusAHCIState::num_ports field
  hw/ide/ahci: Do not pass 'ports' argument to ahci_realize()
  hw/ide/ahci: Convert AHCIState::ports to unsigned
  hw/ide/ahci: Pass AHCI context to ahci_ide_create_devs()
  hw/ide/ahci: Inline ahci_get_num_ports()
  hw/ide/ahci: Rename AHCI PCI function as 'pdev'
  hw/ide/ahci: Expose AHCIPCIState structure
  hw/i386/q35: Use DEVICE() cast macro with PCIDevice object
  hw/i386/q35: Simplify pc_q35_init() since PCI is always enabled
  MAINTAINERS: Add myself as reviewer for TCG Plugins
  MAINTAINERS: replace Fabien by myself as Leon3 maintainer
  hw/sparc/leon3: Initialize GPIO before realizing CPU devices
  hw/sparc/leon3: Pass DeviceState opaque argument to leon3_start_cpu()
  hw/sparc/leon3: Pass DeviceState opaque argument to leon3_set_pil_in()
  hw/sparc/leon3: check cpu_id in the tiny bootloader
  hw/sparc/leon3: implement multiprocessor
  hw/sparc/leon3: remove SP initialization
  target/sparc: implement asr17 feature for smp
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2024-02-16 11:05:14 +00:00
parent 8e31b744fd 9a4b35f57e
commit da96ad4a6a
59 changed files with 488 additions and 460 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+3 -1
View File
@@ -1358,6 +1358,7 @@ M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Aurelien Jarno <aurelien@aurel32.net>
S: Odd Fixes
F: hw/isa/piix.c
F: hw/isa/fdc37m81x-superio.c
F: hw/acpi/piix4.c
F: hw/mips/malta.c
F: hw/pci-host/gt64120.c
@@ -1709,7 +1710,7 @@ F: hw/rtc/sun4v-rtc.c
F: include/hw/rtc/sun4v-rtc.h
Leon3
M: Fabien Chouteau <chouteau@adacore.com>
M: Clément Chigot <chigot@adacore.com>
M: Frederic Konrad <konrad.frederic@yahoo.fr>
S: Maintained
F: hw/sparc/leon3.c
@@ -3706,6 +3707,7 @@ TCG Plugins
M: Alex Bennée <alex.bennee@linaro.org>
R: Alexandre Iooss <erdnaxe@crans.org>
R: Mahmoud Mandour <ma.mandourr@gmail.com>
R: Pierrick Bouvier <pierrick.bouvier@linaro.org>
S: Maintained
F: docs/devel/tcg-plugins.rst
F: plugins/
hw/arm/highbank.c
+1 -1
View File
@@ -30,7 +30,7 @@
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "hw/char/pl011.h"
#include "hw/ide/ahci.h"
#include "hw/ide/ahci-sysbus.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/cpu/a15mpcore.h"
#include "qemu/log.h"
hw/arm/sbsa-ref.c
+1
View File
@@ -38,6 +38,7 @@
#include "hw/boards.h"
#include "hw/ide/internal.h"
#include "hw/ide/ahci_internal.h"
#include "hw/ide/ahci-sysbus.h"
#include "hw/intc/arm_gicv3_common.h"
#include "hw/intc/arm_gicv3_its_common.h"
#include "hw/loader.h"
hw/char/grlib_apbuart.c
+4 -2
View File
@@ -1,7 +1,9 @@
/*
* QEMU GRLIB APB UART Emulator
*
* Copyright (c) 2010-2019 AdaCore
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2010-2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -26,7 +28,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "hw/sparc/grlib.h"
#include "hw/char/grlib_uart.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "chardev/char-fe.h"
hw/dma/i82374.c
+1 -1
View File
@@ -129,7 +129,7 @@ static void i82374_realize(DeviceState *dev, Error **errp)
error_setg(errp, "DMA already initialized on ISA bus");
return;
}
i8257_dma_init(isa_bus, true);
i8257_dma_init(OBJECT(dev), isa_bus, true);
portio_list_init(&s->port_list, OBJECT(s), i82374_portio_list, s,
"i82374");
hw/dma/i8257.c
+3 -1
View File
@@ -632,12 +632,13 @@ static void i8257_register_types(void)
type_init(i8257_register_types)
void i8257_dma_init(ISABus *bus, bool high_page_enable)
void i8257_dma_init(Object *parent, ISABus *bus, bool high_page_enable)
{
ISADevice *isa1, *isa2;
DeviceState *d;
isa1 = isa_new(TYPE_I8257);
object_property_add_child(parent, "dma[*]", OBJECT(isa1));
d = DEVICE(isa1);
qdev_prop_set_int32(d, "base", 0x00);
qdev_prop_set_int32(d, "page-base", 0x80);
@@ -646,6 +647,7 @@ void i8257_dma_init(ISABus *bus, bool high_page_enable)
isa_realize_and_unref(isa1, bus, &error_fatal);
isa2 = isa_new(TYPE_I8257);
object_property_add_child(parent, "dma[*]", OBJECT(isa2));
d = DEVICE(isa2);
qdev_prop_set_int32(d, "base", 0xc0);
qdev_prop_set_int32(d, "page-base", 0x88);
hw/i386/pc_piix.c
+1 -1
View File
@@ -310,7 +310,7 @@ static void pc_init1(MachineState *machine,
qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000);
isa_realize_and_unref(rtc_state, isa_bus, &error_fatal);
i8257_dma_init(isa_bus, 0);
i8257_dma_init(OBJECT(machine), isa_bus, 0);
pcms->hpet_enabled = false;
idebus[0] = NULL;
idebus[1] = NULL;
hw/i386/pc_q35.c
+24 -33
View File
@@ -47,7 +47,7 @@
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/ide/ahci-pci.h"
#include "hw/intc/ioapic.h"
#include "hw/southbridge/ich9.h"
#include "hw/usb.h"
@@ -130,12 +130,10 @@ static void pc_q35_init(MachineState *machine)
ISADevice *rtc_state;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
MemoryRegion *pci_memory = g_new(MemoryRegion, 1);
GSIState *gsi_state;
ISABus *isa_bus;
int i;
PCIDevice *ahci;
ram_addr_t lowmem;
DriveInfo *hd[MAX_SATA_PORTS];
MachineClass *mc = MACHINE_GET_CLASS(machine);
@@ -143,6 +141,8 @@ static void pc_q35_init(MachineState *machine)
bool keep_pci_slot_hpc;
uint64_t pci_hole64_size = 0;
assert(pcmc->pci_enabled);
/* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
* and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
* also known as MMCFG).
@@ -189,16 +189,6 @@ static void pc_q35_init(MachineState *machine)
kvmclock_create(pcmc->kvmclock_create_always);
}
/* pci enabled */
if (pcmc->pci_enabled) {
pci_memory = g_new(MemoryRegion, 1);
memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
rom_memory = pci_memory;
} else {
pci_memory = NULL;
rom_memory = system_memory;
}
pc_guest_info_init(pcms);
if (pcmc->smbios_defaults) {
@@ -212,14 +202,13 @@ static void pc_q35_init(MachineState *machine)
/* create pci host bus */
phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE));
if (pcmc->pci_enabled) {
pci_hole64_size = object_property_get_uint(phb,
PCI_HOST_PROP_PCI_HOLE64_SIZE,
&error_abort);
}
pci_hole64_size = object_property_get_uint(phb,
PCI_HOST_PROP_PCI_HOLE64_SIZE,
&error_abort);
/* allocate ram and load rom/bios */
pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size);
memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size);
object_property_add_child(OBJECT(machine), "q35", phb);
object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM,
@@ -243,18 +232,18 @@ static void pc_q35_init(MachineState *machine)
pcms->bus = host_bus;
/* irq lines */
gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
gsi_state = pc_gsi_create(&x86ms->gsi, true);
/* create ISA bus */
lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC),
TYPE_ICH9_LPC_DEVICE);
qdev_prop_set_bit(DEVICE(lpc), "smm-enabled",
x86_machine_is_smm_enabled(x86ms));
lpc_dev = DEVICE(lpc);
qdev_prop_set_bit(lpc_dev, "smm-enabled",
x86_machine_is_smm_enabled(x86ms));
pci_realize_and_unref(lpc, host_bus, &error_fatal);
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
pci_realize_and_unref(lpc, host_bus, &error_fatal);
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc"));
@@ -286,9 +275,7 @@ static void pc_q35_init(MachineState *machine)
pc_i8259_create(isa_bus, gsi_state->i8259_irq);
}
if (pcmc->pci_enabled) {
ioapic_init_gsi(gsi_state, "q35");
}
ioapic_init_gsi(gsi_state, "q35");
if (tcg_enabled()) {
x86_register_ferr_irq(x86ms->gsi[13]);
@@ -304,16 +291,20 @@ static void pc_q35_init(MachineState *machine)
0xff0104);
if (pcms->sata_enabled) {
PCIDevice *pdev;
AHCIPCIState *ich9;
/* ahci and SATA device, for q35 1 ahci controller is built-in */
ahci = pci_create_simple_multifunction(host_bus,
pdev = pci_create_simple_multifunction(host_bus,
PCI_DEVFN(ICH9_SATA1_DEV,
ICH9_SATA1_FUNC),
"ich9-ahci");
idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
ide_drive_get(hd, ahci_get_num_ports(ahci));
ahci_ide_create_devs(ahci, hd);
ich9 = ICH9_AHCI(pdev);
idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0");
idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1");
g_assert(MAX_SATA_PORTS == ich9->ahci.ports);
ide_drive_get(hd, ich9->ahci.ports);
ahci_ide_create_devs(&ich9->ahci, hd);
} else {
idebus[0] = idebus[1] = NULL;
}
hw/ide/ahci-allwinner.c
+1 -2
View File
@@ -19,9 +19,8 @@
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "hw/ide/internal.h"
#include "migration/vmstate.h"
#include "ahci_internal.h"
#include "hw/ide/ahci-sysbus.h"
#include "trace.h"
hw/ide/ahci.c
+10 -19
View File
@@ -36,6 +36,8 @@
#include "sysemu/dma.h"
#include "hw/ide/internal.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci-pci.h"
#include "hw/ide/ahci-sysbus.h"
#include "ahci_internal.h"
#include "trace.h"
@@ -1613,14 +1615,14 @@ void ahci_init(AHCIState *s, DeviceState *qdev)
"ahci-idp", 32);
}
void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as)
{
qemu_irq *irqs;
int i;
s->as = as;
s->ports = ports;
s->dev = g_new0(AHCIDevice, ports);
assert(s->ports > 0);
s->dev = g_new0(AHCIDevice, s->ports);
ahci_reg_init(s);
irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
for (i = 0; i < s->ports; i++) {
@@ -1818,7 +1820,7 @@ const VMStateDescription vmstate_ahci = {
.version_id = 1,
.post_load = ahci_state_post_load,
.fields = (const VMStateField[]) {
VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports,
VMSTATE_STRUCT_VARRAY_POINTER_UINT32(dev, AHCIState, ports,
vmstate_ahci_device, AHCIDevice),
VMSTATE_UINT32(control_regs.cap, AHCIState),
VMSTATE_UINT32(control_regs.ghc, AHCIState),
@@ -1826,7 +1828,7 @@ const VMStateDescription vmstate_ahci = {
VMSTATE_UINT32(control_regs.impl, AHCIState),
VMSTATE_UINT32(control_regs.version, AHCIState),
VMSTATE_UINT32(idp_index, AHCIState),
VMSTATE_INT32_EQUAL(ports, AHCIState, NULL),
VMSTATE_UINT32_EQUAL(ports, AHCIState, NULL),
VMSTATE_END_OF_LIST()
},
};
@@ -1861,11 +1863,11 @@ static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
{
SysbusAHCIState *s = SYSBUS_AHCI(dev);
ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports);
ahci_realize(&s->ahci, dev, &address_space_memory);
}
static Property sysbus_ahci_properties[] = {
DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, ahci.ports, 1),
DEFINE_PROP_END_OF_LIST(),
};
@@ -1895,18 +1897,8 @@ static void sysbus_ahci_register_types(void)
type_init(sysbus_ahci_register_types)
int32_t ahci_get_num_ports(PCIDevice *dev)
void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd)
{
AHCIPCIState *d = ICH9_AHCI(dev);
AHCIState *ahci = &d->ahci;
return ahci->ports;
}
void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
{
AHCIPCIState *d = ICH9_AHCI(dev);
AHCIState *ahci = &d->ahci;
int i;
for (i = 0; i < ahci->ports; i++) {
@@ -1915,5 +1907,4 @@ void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
}
ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
}
}
hw/ide/ahci_internal.h
+1 -9
View File
@@ -324,14 +324,6 @@ struct AHCIDevice {
MemReentrancyGuard mem_reentrancy_guard;
};
struct AHCIPCIState {
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
AHCIState ahci;
};
extern const VMStateDescription vmstate_ahci;
#define VMSTATE_AHCI(_field, _state) { \
@@ -385,7 +377,7 @@ typedef struct SDBFIS {
uint32_t payload;
} QEMU_PACKED SDBFIS;
void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as);
void ahci_init(AHCIState *s, DeviceState *qdev);
void ahci_uninit(AHCIState *s);
hw/ide/ich.c
+6 -4
View File
@@ -69,6 +69,7 @@
#include "hw/isa/isa.h"
#include "sysemu/dma.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci-pci.h"
#include "ahci_internal.h"
#define ICH9_MSI_CAP_OFFSET 0x80
@@ -99,20 +100,21 @@ static void pci_ich9_reset(DeviceState *dev)
static void pci_ich9_ahci_init(Object *obj)
{
struct AHCIPCIState *d = ICH9_AHCI(obj);
AHCIPCIState *d = ICH9_AHCI(obj);
ahci_init(&d->ahci, DEVICE(obj));
}
static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
{
struct AHCIPCIState *d;
AHCIPCIState *d;
int sata_cap_offset;
uint8_t *sata_cap;
d = ICH9_AHCI(dev);
int ret;
ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
d->ahci.ports = 6;
ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev));
pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
@@ -154,7 +156,7 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
static void pci_ich9_uninit(PCIDevice *dev)
{
struct AHCIPCIState *d;
AHCIPCIState *d;
d = ICH9_AHCI(dev);
msi_uninit(dev);
hw/intc/grlib_irqmp.c
+76 -34
View File
@@ -1,9 +1,11 @@
/*
* QEMU GRLIB IRQMP Emulator
*
* (Multiprocessor and extended interrupt not supported)
* (Extended interrupt not supported)
*
* Copyright (c) 2010-2019 AdaCore
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2010-2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -29,7 +31,7 @@
#include "hw/sysbus.h"
#include "hw/qdev-properties.h"
#include "hw/sparc/grlib.h"
#include "hw/intc/grlib_irqmp.h"
#include "trace.h"
#include "qapi/error.h"
@@ -50,6 +52,10 @@
#define FORCE_OFFSET 0x80
#define EXTENDED_OFFSET 0xC0
/* Multiprocessor Status Register */
#define MP_STATUS_CPU_STATUS_MASK ((1 << IRQMP_MAX_CPU)-2)
#define MP_STATUS_NCPU_SHIFT 28
#define MAX_PILS 16
OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP)
@@ -61,14 +67,17 @@ struct IRQMP {
MemoryRegion iomem;
unsigned int ncpus;
IRQMPState *state;
qemu_irq irq;
qemu_irq start_signal[IRQMP_MAX_CPU];
qemu_irq irq[IRQMP_MAX_CPU];
};
struct IRQMPState {
uint32_t level;
uint32_t pending;
uint32_t clear;
uint32_t mpstatus;
uint32_t broadcast;
uint32_t mask[IRQMP_MAX_CPU];
@@ -80,37 +89,35 @@ struct IRQMPState {
static void grlib_irqmp_check_irqs(IRQMPState *state)
{
uint32_t pend = 0;
uint32_t level0 = 0;
uint32_t level1 = 0;
int i;
assert(state != NULL);
assert(state->parent != NULL);
/* IRQ for CPU 0 (no SMP support) */
pend = (state->pending | state->force[0])
& state->mask[0];
for (i = 0; i < state->parent->ncpus; i++) {
uint32_t pend = (state->pending | state->force[i]) & state->mask[i];
uint32_t level0 = pend & ~state->level;
uint32_t level1 = pend & state->level;
level0 = pend & ~state->level;
level1 = pend & state->level;
trace_grlib_irqmp_check_irqs(state->pending, state->force[i],
state->mask[i], level1, level0);
trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
state->mask[0], level1, level0);
/* Trigger level1 interrupt first and level0 if there is no level1 */
qemu_set_irq(state->parent->irq, level1 ?: level0);
/* Trigger level1 interrupt first and level0 if there is no level1 */
qemu_set_irq(state->parent->irq[i], level1 ?: level0);
}
}
static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask)
static void grlib_irqmp_ack_mask(IRQMPState *state, unsigned int cpu,
uint32_t mask)
{
/* Clear registers */
state->pending &= ~mask;
state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
state->force[cpu] &= ~mask;
grlib_irqmp_check_irqs(state);
}
void grlib_irqmp_ack(DeviceState *dev, int intno)
void grlib_irqmp_ack(DeviceState *dev, unsigned int cpu, int intno)
{
IRQMP *irqmp = GRLIB_IRQMP(dev);
IRQMPState *state;
@@ -124,7 +131,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno)
trace_grlib_irqmp_ack(intno);
grlib_irqmp_ack_mask(state, mask);
grlib_irqmp_ack_mask(state, cpu, mask);
}
static void grlib_irqmp_set_irq(void *opaque, int irq, int level)
@@ -150,7 +157,6 @@ static void grlib_irqmp_set_irq(void *opaque, int irq, int level)
s->pending |= 1 << irq;
}
grlib_irqmp_check_irqs(s);
}
}
@@ -179,10 +185,12 @@ static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
return state->force[0];
case CLEAR_OFFSET:
case MP_STATUS_OFFSET:
/* Always read as 0 */
return 0;
case MP_STATUS_OFFSET:
return state->mpstatus;
case BROADCAST_OFFSET:
return state->broadcast;
@@ -221,8 +229,9 @@ static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
static void grlib_irqmp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
IRQMP *irqmp = opaque;
IRQMP *irqmp = opaque;
IRQMPState *state;
int i;
assert(irqmp != NULL);
state = irqmp->state;
@@ -251,11 +260,24 @@ static void grlib_irqmp_write(void *opaque, hwaddr addr,
case CLEAR_OFFSET:
value &= ~1; /* clean up the value */
grlib_irqmp_ack_mask(state, value);
for (i = 0; i < irqmp->ncpus; i++) {
grlib_irqmp_ack_mask(state, i, value);
}
return;
case MP_STATUS_OFFSET:
/* Read Only (no SMP support) */
/*
* Writing and reading operations are reversed for the CPU status.
* Writing "1" will start the CPU, but reading "1" means that the CPU
* is power-down.
*/
value &= MP_STATUS_CPU_STATUS_MASK;
for (i = 0; i < irqmp->ncpus; i++) {
if ((value >> i) & 1) {
qemu_set_irq(irqmp->start_signal[i], 1);
state->mpstatus &= ~(1 << i);
}
}
return;
case BROADCAST_OFFSET:
@@ -322,35 +344,55 @@ static void grlib_irqmp_reset(DeviceState *d)
memset(irqmp->state, 0, sizeof *irqmp->state);
irqmp->state->parent = irqmp;
irqmp->state->mpstatus = ((irqmp->ncpus - 1) << MP_STATUS_NCPU_SHIFT) |
((1 << irqmp->ncpus) - 2);
}
static void grlib_irqmp_init(Object *obj)
static void grlib_irqmp_realize(DeviceState *dev, Error **errp)
{
IRQMP *irqmp = GRLIB_IRQMP(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
IRQMP *irqmp = GRLIB_IRQMP(dev);
qdev_init_gpio_in(DEVICE(obj), grlib_irqmp_set_irq, MAX_PILS);
qdev_init_gpio_out_named(DEVICE(obj), &irqmp->irq, "grlib-irq", 1);
memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp,
if ((!irqmp->ncpus) || (irqmp->ncpus > IRQMP_MAX_CPU)) {
error_setg(errp, "Invalid ncpus properties: "
"%u, must be 0 < ncpus =< %u.", irqmp->ncpus,
IRQMP_MAX_CPU);
}
qdev_init_gpio_in(dev, grlib_irqmp_set_irq, MAX_PILS);
/*
* Transitionning from 0 to 1 starts the CPUs. The opposite can't
* happen.
*/
qdev_init_gpio_out_named(dev, irqmp->start_signal, "grlib-start-cpu",
IRQMP_MAX_CPU);
qdev_init_gpio_out_named(dev, irqmp->irq, "grlib-irq", irqmp->ncpus);
memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp,
"irqmp", IRQMP_REG_SIZE);
irqmp->state = g_malloc0(sizeof *irqmp->state);
sysbus_init_mmio(dev, &irqmp->iomem);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &irqmp->iomem);
}
static Property grlib_irqmp_properties[] = {
DEFINE_PROP_UINT32("ncpus", IRQMP, ncpus, 1),
DEFINE_PROP_END_OF_LIST(),
};
static void grlib_irqmp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = grlib_irqmp_realize;
dc->reset = grlib_irqmp_reset;
device_class_set_props(dc, grlib_irqmp_properties);
}
static const TypeInfo grlib_irqmp_info = {
.name = TYPE_GRLIB_IRQMP,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IRQMP),
.instance_init = grlib_irqmp_init,
.class_init = grlib_irqmp_class_init,
};
hw/isa/Kconfig
+10 -10
View File
@@ -15,9 +15,17 @@ config I82378
config ISA_SUPERIO
bool
select ISA_BUS
depends on ISA_BUS
select PCKBD
select PARALLEL
select SERIAL_ISA
select FDC_ISA
# Some users of ISA_SUPERIO do not use it
#select IDE_ISA
config FDC37M81X
bool
select ISA_SUPERIO
config PC87312
bool
@@ -26,9 +34,6 @@ config PC87312
select I8254
select I8257
select MC146818RTC
select SERIAL_ISA
select PARALLEL
select FDC_ISA
select IDE_ISA
config PIIX
@@ -46,11 +51,10 @@ config PIIX
config VT82C686
bool
select ISA_BUS
select ISA_SUPERIO
select ACPI
select ACPI_SMBUS
select SERIAL_ISA
select FDC_ISA
select USB_UHCI
select APM
select I8254
@@ -58,14 +62,10 @@ config VT82C686
select I8259
select IDE_VIA
select MC146818RTC
select PARALLEL
config SMC37C669
bool
select ISA_SUPERIO
select SERIAL_ISA
select PARALLEL
select FDC_ISA
config LPC_ICH9
bool
hw/isa/fdc37m81x-superio.c
+32
View File
@@ -0,0 +1,32 @@
/*
* SMS FDC37M817 Super I/O
*
* Copyright (c) 2018 Philippe Mathieu-Daudé
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "hw/isa/superio.h"
static void fdc37m81x_class_init(ObjectClass *klass, void *data)
{
ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
sc->serial.count = 2; /* NS16C550A */
sc->parallel.count = 1;
sc->floppy.count = 1; /* SMSC 82077AA Compatible */
sc->ide.count = 0;
}
static const TypeInfo types[] = {
{
.name = TYPE_FDC37M81X_SUPERIO,
.parent = TYPE_ISA_SUPERIO,
.class_init = fdc37m81x_class_init,
},
};
DEFINE_TYPES(types)
hw/isa/isa-superio.c
-18
View File
@@ -185,30 +185,12 @@ static const TypeInfo isa_superio_type_info = {
.abstract = true,
.class_size = sizeof(ISASuperIOClass),
.class_init = isa_superio_class_init,
};
/* SMS FDC37M817 Super I/O */
static void fdc37m81x_class_init(ObjectClass *klass, void *data)
{
ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
sc->serial.count = 2; /* NS16C550A */
sc->parallel.count = 1;
sc->floppy.count = 1; /* SMSC 82077AA Compatible */
sc->ide.count = 0;
}
static const TypeInfo fdc37m81x_type_info = {
.name = TYPE_FDC37M81X_SUPERIO,
.parent = TYPE_ISA_SUPERIO,
.instance_size = sizeof(ISASuperIODevice),
.class_init = fdc37m81x_class_init,
};
static void isa_superio_register_types(void)
{
type_register_static(&isa_superio_type_info);
type_register_static(&fdc37m81x_type_info);
}
type_init(isa_superio_register_types)
hw/isa/lpc_ich9.c
+1 -1
View File
@@ -739,7 +739,7 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
isa_bus_register_input_irqs(isa_bus, lpc->gsi);
i8257_dma_init(isa_bus, 0);
i8257_dma_init(OBJECT(d), isa_bus, 0);
/* RTC */
qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000);
hw/isa/meson.build
+1
View File
@@ -4,6 +4,7 @@ system_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c'))
system_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c'))
system_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c'))
system_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c'))
system_ss.add(when: 'CONFIG_FDC37M81X', if_true: files('fdc37m81x-superio.c'))
system_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio.c'))
system_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c'))
hw/isa/piix.c
+1 -1
View File
@@ -336,7 +336,7 @@ static void pci_piix_realize(PCIDevice *dev, const char *uhci_type,
i8254_pit_init(isa_bus, 0x40, 0, NULL);
}
i8257_dma_init(isa_bus, 0);
i8257_dma_init(OBJECT(dev), isa_bus, 0);
/* RTC */
qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000);
hw/isa/smc37c669-superio.c
-1
View File
@@ -103,7 +103,6 @@ static void smc37c669_class_init(ObjectClass *klass, void *data)
static const TypeInfo smc37c669_type_info = {
.name = TYPE_SMC37C669_SUPERIO,
.parent = TYPE_ISA_SUPERIO,
.instance_size = sizeof(ISASuperIODevice),
.class_size = sizeof(ISASuperIOClass),
.class_init = smc37c669_class_init,
};

Some files were not shown because too many files have changed in this diff Show More