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Clean up debugging code #ifdefs (Eduardo Habkost)

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Use macros to avoid #ifdefs on debugging code.

This patch doesn't try to merge logging macros from different files,
but just unify the debugging code #ifdefs onto a macro on each file. A
further cleanup can unify the debugging macros on a common header, later

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6332 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori
2009-01-15 21:48:06 +00:00
parent 40a4539e20
commit d12d51d5ba
15 changed files with 532 additions and 963 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/ppc.c
+68 -245
View File
File diff suppressed because it is too large Load Diff
hw/ppc4xx_devs.c
+18 -40
View File
@@ -31,6 +31,16 @@
//#define DEBUG_UNASSIGNED
#define DEBUG_UIC
#ifdef DEBUG_UIC
# define LOG_UIC(...) do { \
if (loglevel & CPU_LOG_INT) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_UIC(...) do { } while (0)
#endif
/*****************************************************************************/
/* Generic PowerPC 4xx processor instanciation */
CPUState *ppc4xx_init (const char *cpu_model,
@@ -294,28 +304,16 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
/* Trigger interrupt if any is pending */
ir = uic->uicsr & uic->uicer & (~uic->uiccr);
cr = uic->uicsr & uic->uicer & uic->uiccr;
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32
LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
" uiccr %08" PRIx32 "\n"
" %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
__func__, uic->uicsr, uic->uicer, uic->uiccr,
uic->uicsr & uic->uicer, ir, cr);
}
#endif
if (ir != 0x0000000) {
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Raise UIC interrupt\n");
}
#endif
LOG_UIC("Raise UIC interrupt\n");
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
} else {
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Lower UIC interrupt\n");
}
#endif
LOG_UIC("Lower UIC interrupt\n");
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
}
/* Trigger critical interrupt if any is pending and update vector */
@@ -340,18 +338,10 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
}
}
}
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Raise UIC critical interrupt - "
LOG_UIC("Raise UIC critical interrupt - "
"vector %08" PRIx32 "\n", uic->uicvr);
}
#endif
} else {
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Lower UIC critical interrupt\n");
}
#endif
LOG_UIC("Lower UIC critical interrupt\n");
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
uic->uicvr = 0x00000000;
}
@@ -364,14 +354,10 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
uic = opaque;
mask = 1 << (31-irq_num);
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
__func__, irq_num, level,
uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
}
#endif
if (irq_num < 0 || irq_num > 31)
return;
sr = uic->uicsr;
@@ -391,12 +377,8 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
uic->level &= ~mask;
}
}
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => "
LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
}
#endif
if (sr != uic->uicsr)
ppcuic_trigger_irq(uic);
}
@@ -453,11 +435,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
uic = opaque;
dcrn -= uic->dcr_base;
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
}
#endif
LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;
kqemu.c
+28 -49
View File
@@ -47,6 +47,22 @@
#define DEBUG
//#define PROFILE
#ifdef DEBUG
# define LOG_INT(...) do { \
if (loglevel & CPU_LOG_INT) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
# define LOG_INT_STATE(env) \
do { \
if (loglevel & CPU_LOG_INT) \
cpu_dump_state(env, logfile, fprintf, 0); \
} while (0)
#else
# define LOG_INT(...) do { } while (0)
# define LOG_INT_STATE(env) do { } while (0)
#endif
#include <unistd.h>
#include <fcntl.h>
#include "kqemu.h"
@@ -241,11 +257,7 @@ int kqemu_init(CPUState *env)
void kqemu_flush_page(CPUState *env, target_ulong addr)
{
#if defined(DEBUG)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu_flush_page: addr=" TARGET_FMT_lx "\n", addr);
}
#endif
LOG_INT("kqemu_flush_page: addr=" TARGET_FMT_lx "\n", addr);
if (nb_pages_to_flush >= KQEMU_MAX_PAGES_TO_FLUSH)
nb_pages_to_flush = KQEMU_FLUSH_ALL;
else
@@ -254,22 +266,14 @@ void kqemu_flush_page(CPUState *env, target_ulong addr)
void kqemu_flush(CPUState *env, int global)
{
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu_flush:\n");
}
#endif
LOG_INT("kqemu_flush:\n");
nb_pages_to_flush = KQEMU_FLUSH_ALL;
}
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr)
{
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu_set_notdirty: addr=%08lx\n",
LOG_INT("kqemu_set_notdirty: addr=%08lx\n",
(unsigned long)ram_addr);
}
#endif
/* we only track transitions to dirty state */
if (phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] != 0xff)
return;
@@ -703,12 +707,8 @@ int kqemu_cpu_exec(CPUState *env)
#ifdef CONFIG_PROFILER
ti = profile_getclock();
#endif
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu: cpu_exec: enter\n");
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
LOG_INT("kqemu: cpu_exec: enter\n");
LOG_INT_STATE(env);
for(i = 0; i < CPU_NB_REGS; i++)
kenv->regs[i] = env->regs[i];
kenv->eip = env->eip;
@@ -867,11 +867,7 @@ int kqemu_cpu_exec(CPUState *env)
else
env->hflags &= ~HF_OSFXSR_MASK;
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu: kqemu_cpu_exec: ret=0x%x\n", ret);
}
#endif
LOG_INT("kqemu: kqemu_cpu_exec: ret=0x%x\n", ret);
if (ret == KQEMU_RET_SYSCALL) {
/* syscall instruction */
return do_syscall(env, kenv);
@@ -884,13 +880,8 @@ int kqemu_cpu_exec(CPUState *env)
#ifdef CONFIG_PROFILER
kqemu_ret_int_count++;
#endif
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu: interrupt v=%02x:\n",
env->exception_index);
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
LOG_INT("kqemu: interrupt v=%02x:\n", env->exception_index);
LOG_INT_STATE(env);
return 1;
} else if ((ret & 0xff00) == KQEMU_RET_EXCEPTION) {
env->exception_index = ret & 0xff;
@@ -900,23 +891,15 @@ int kqemu_cpu_exec(CPUState *env)
#ifdef CONFIG_PROFILER
kqemu_ret_excp_count++;
#endif
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu: exception v=%02x e=%04x:\n",
LOG_INT("kqemu: exception v=%02x e=%04x:\n",
env->exception_index, env->error_code);
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
LOG_INT_STATE(env);
return 1;
} else if (ret == KQEMU_RET_INTR) {
#ifdef CONFIG_PROFILER
kqemu_ret_intr_count++;
#endif
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
LOG_INT_STATE(env);
return 0;
} else if (ret == KQEMU_RET_SOFTMMU) {
#ifdef CONFIG_PROFILER
@@ -925,11 +908,7 @@ int kqemu_cpu_exec(CPUState *env)
kqemu_record_pc(pc);
}
#endif
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
LOG_INT_STATE(env);
return 2;
} else {
cpu_dump_state(env, stderr, fprintf, 0);
linux-user/vm86.c
+17 -22
View File
@@ -29,6 +29,13 @@
//#define DEBUG_VM86
#ifdef DEBUG_VM86
# define LOG_VM86(...) fprintf(logfile, ## __VA_ARGS__);
#else
# define LOG_VM86(...) do { } while (0)
#endif
#define set_flags(X,new,mask) \
((X) = ((X) & ~(mask)) | ((new) & (mask)))
@@ -92,10 +99,8 @@ void save_v86_state(CPUX86State *env)
set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
target_v86->regs.eflags = tswap32(env->eflags);
unlock_user_struct(target_v86, ts->target_v86, 1);
#ifdef DEBUG_VM86
fprintf(logfile, "save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
env->eflags, env->segs[R_CS].selector, env->eip);
#endif
LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
env->eflags, env->segs[R_CS].selector, env->eip);
/* restore 32 bit registers */
env->regs[R_EAX] = ts->vm86_saved_regs.eax;
@@ -121,9 +126,7 @@ void save_v86_state(CPUX86State *env)
'retval' */
static inline void return_to_32bit(CPUX86State *env, int retval)
{
#ifdef DEBUG_VM86
fprintf(logfile, "return_to_32bit: ret=0x%x\n", retval);
#endif
LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
save_v86_state(env);
env->regs[R_EAX] = retval;
}
@@ -216,10 +219,8 @@ static void do_int(CPUX86State *env, int intno)
segoffs = ldl(int_addr);
if ((segoffs >> 16) == TARGET_BIOSSEG)
goto cannot_handle;
#if defined(DEBUG_VM86)
fprintf(logfile, "VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
intno, segoffs >> 16, segoffs & 0xffff);
#endif
LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
intno, segoffs >> 16, segoffs & 0xffff);
/* save old state */
ssp = env->segs[R_SS].selector << 4;
sp = env->regs[R_ESP] & 0xffff;
@@ -235,9 +236,7 @@ static void do_int(CPUX86State *env, int intno)
clear_AC(env);
return;
cannot_handle:
#if defined(DEBUG_VM86)
fprintf(logfile, "VM86: return to 32 bits int 0x%x\n", intno);
#endif
LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
}
@@ -274,10 +273,8 @@ void handle_vm86_fault(CPUX86State *env)
ssp = env->segs[R_SS].selector << 4;
sp = env->regs[R_ESP] & 0xffff;
#if defined(DEBUG_VM86)
fprintf(logfile, "VM86 exception %04x:%08x\n",
env->segs[R_CS].selector, env->eip);
#endif
LOG_VM86("VM86 exception %04x:%08x\n",
env->segs[R_CS].selector, env->eip);
data32 = 0;
pref_done = 0;
@@ -478,10 +475,8 @@ int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
target_v86->vm86plus.vm86dbg_intxxtab, 32);
unlock_user_struct(target_v86, vm86_addr, 0);
#ifdef DEBUG_VM86
fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n",
env->segs[R_CS].selector, env->eip);
#endif
LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
env->segs[R_CS].selector, env->eip);
/* now the virtual CPU is ready for vm86 execution ! */
out:
return ret;
target-alpha/translate.c
+15 -13
View File
@@ -37,6 +37,16 @@
#define ALPHA_DEBUG_DISAS
/* #define DO_TB_FLUSH */
#ifdef ALPHA_DEBUG_DISAS
# define LOG_DISAS(...) do { \
if (logfile) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_DISAS(...) do { } while (0)
#endif
typedef struct DisasContext DisasContext;
struct DisasContext {
uint64_t pc;
@@ -671,12 +681,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
fn7 = (insn >> 5) & 0x0000007F;
fn2 = (insn >> 5) & 0x00000003;
ret = 0;
#if defined ALPHA_DEBUG_DISAS
if (logfile != NULL) {
fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
opc, ra, rb, rc, disp16);
}
#endif
LOG_DISAS("opc %02x ra %d rb %d rc %d disp16 %04x\n",
opc, ra, rb, rc, disp16);
switch (opc) {
case 0x00:
/* CALL_PAL */
@@ -2386,17 +2392,13 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
gen_io_start();
#if defined ALPHA_DEBUG_DISAS
insn_count++;
if (logfile != NULL) {
fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
ctx.pc, ctx.mem_idx);
}
LOG_DISAS("pc " TARGET_FMT_lx " mem_idx %d\n",
ctx.pc, ctx.mem_idx);
#endif
insn = ldl_code(ctx.pc);
#if defined ALPHA_DEBUG_DISAS
insn_count++;
if (logfile != NULL) {
fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
}
LOG_DISAS("opcode %08x %d\n", insn, insn_count);
#endif
num_insns++;
ctx.pc += 4;
target-cris/helper.c
+18 -8
View File
@@ -28,7 +28,17 @@
#include "exec-all.h"
#include "host-utils.h"
//#define CRIS_HELPER_DEBUG
#ifdef CRIS_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif
#if defined(CONFIG_USER_ONLY)
@@ -98,10 +108,10 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
}
if (r > 0)
D(fprintf(logfile, "%s returns %d irqreq=%x addr=%x"
D_LOG("%s returns %d irqreq=%x addr=%x"
" phy=%x ismmu=%d vec=%x pc=%x\n",
__func__, r, env->interrupt_request,
address, res.phy, is_softmmu, res.bf_vec, env->pc));
address, res.phy, is_softmmu, res.bf_vec, env->pc);
return r;
}
@@ -109,9 +119,9 @@ void do_interrupt(CPUState *env)
{
int ex_vec = -1;
D(fprintf (logfile, "exception index=%d interrupt_req=%d\n",
D_LOG( "exception index=%d interrupt_req=%d\n",
env->exception_index,
env->interrupt_request));
env->interrupt_request);
switch (env->exception_index)
{
@@ -147,13 +157,13 @@ void do_interrupt(CPUState *env)
env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
if (env->dslot) {
D(fprintf(logfile, "excp isr=%x PC=%x ds=%d SP=%x"
D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
" ERP=%x pid=%x ccs=%x cc=%d %x\n",
ex_vec, env->pc, env->dslot,
env->regs[R_SP],
env->pregs[PR_ERP], env->pregs[PR_PID],
env->pregs[PR_CCS],
env->cc_op, env->cc_mask));
env->cc_op, env->cc_mask);
/* We loose the btarget, btaken state here so rexec the
branch. */
env->pregs[PR_ERP] -= env->dslot;
@@ -171,11 +181,11 @@ void do_interrupt(CPUState *env)
/* Apply the CRIS CCS shift. Clears U if set. */
cris_shift_ccs(env);
D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
__func__, env->pc, ex_vec,
env->pregs[PR_CCS],
env->pregs[PR_PID],
env->pregs[PR_ERP]));
env->pregs[PR_ERP]);
}
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
target-cris/mmu.c
+6 -6
View File
@@ -32,8 +32,10 @@
#ifdef DEBUG
#define D(x) x
#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif
void cris_mmu_init(CPUState *env)
@@ -180,9 +182,8 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
tlb_pid = EXTRACT_FIELD(hi, 0, 7);
tlb_g = EXTRACT_FIELD(lo, 4, 4);
D(fprintf(logfile,
"TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
mmu, set, idx, tlb_vpn, vpage, lo, hi));
D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
mmu, set, idx, tlb_vpn, vpage, lo, hi);
if ((tlb_g || (tlb_pid == pid))
&& tlb_vpn == vpage) {
match = 1;
@@ -314,9 +315,8 @@ void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
if (tlb_v && !tlb_g && (tlb_pid == pid)) {
vaddr = tlb_vpn << TARGET_PAGE_BITS;
D(fprintf(logfile,
"flush pid=%x vaddr=%x\n",
pid, vaddr));
D_LOG("flush pid=%x vaddr=%x\n",
pid, vaddr);
tlb_flush_page(env, vaddr);
}
}
target-cris/op_helper.c
+17 -9
View File
@@ -25,7 +25,16 @@
#include "helper.h"
#include "host-utils.h"
//#define CRIS_OP_HELPER_DEBUG
#ifdef CRIS_OP_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif
#if !defined(CONFIG_USER_ONLY)
@@ -59,8 +68,8 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
D(fprintf(logfile, "%s pc=%x tpc=%x ra=%x\n", __func__,
env->pc, env->debug1, retaddr));
D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
env->pc, env->debug1, retaddr);
ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
if (unlikely(ret)) {
if (retaddr) {
@@ -155,9 +164,8 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
env->tlbsets[srs - 1][set][idx].lo = lo;
env->tlbsets[srs - 1][set][idx].hi = hi;
D(fprintf(logfile,
"tlb flush vaddr=%x v=%d pc=%x\n",
vaddr, tlb_v, env->pc));
D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
vaddr, tlb_v, env->pc);
tlb_flush_page(env, vaddr);
}
}
@@ -213,10 +221,10 @@ void helper_rfe(void)
{
int rflag = env->pregs[PR_CCS] & R_FLAG;
D(fprintf(logfile, "rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
env->pregs[PR_ERP], env->pregs[PR_PID],
env->pregs[PR_CCS],
env->btarget));
env->btarget);
cris_ccs_rshift(env);
@@ -229,10 +237,10 @@ void helper_rfn(void)
{
int rflag = env->pregs[PR_CCS] & R_FLAG;
D(fprintf(logfile, "rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
env->pregs[PR_ERP], env->pregs[PR_PID],
env->pregs[PR_CCS],
env->btarget));
env->btarget);
cris_ccs_rshift(env);
target-cris/translate.c
+146 -143
View File
File diff suppressed because it is too large Load Diff
target-i386/op_helper.c
+25 -32
View File
@@ -24,6 +24,22 @@
//#define DEBUG_PCALL
#ifdef DEBUG_PCALL
# define LOG_PCALL(...) do { \
if (loglevel & CPU_LOG_PCALL) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
# define LOG_PCALL_STATE(env) do { \
if (loglevel & CPU_LOG_PCALL) \
cpu_dump_state((env), logfile, fprintf, X86_DUMP_CCOP); \
} while (0)
#else
# define LOG_PCALL(...) do { } while (0)
# define LOG_PCALL_STATE(env) do { } while (0)
#endif
#if 0
#define raise_exception_err(a, b)\
do {\
@@ -277,10 +293,7 @@ static void switch_tss(int tss_selector,
target_ulong ptr;
type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL)
fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
#endif
LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
/* if task gate, we read the TSS segment and we load it */
if (type == 5) {
@@ -2276,23 +2289,14 @@ void helper_lcall_protected(int new_cs, target_ulong new_eip,
target_ulong ssp, old_ssp, next_eip;
next_eip = env->eip + next_eip_addend;
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL) {
fprintf(logfile, "lcall %04x:%08x s=%d\n",
new_cs, (uint32_t)new_eip, shift);
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
}
#endif
LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
LOG_PCALL_STATE(env);
if ((new_cs & 0xfffc) == 0)
raise_exception_err(EXCP0D_GPF, 0);
if (load_segment(&e1, &e2, new_cs) != 0)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
cpl = env->hflags & HF_CPL_MASK;
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL) {
fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
}
#endif
LOG_PCALL("desc=%08x:%08x\n", e1, e2);
if (e2 & DESC_S_MASK) {
if (!(e2 & DESC_CS_MASK))
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
@@ -2396,11 +2400,8 @@ void helper_lcall_protected(int new_cs, target_ulong new_eip,
if (!(e2 & DESC_C_MASK) && dpl < cpl) {
/* to inner privilege */
get_ss_esp_from_tss(&ss, &sp, dpl);
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL)
fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
LOG_PCALL("new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
ss, sp, param_count, ESP);
#endif
if ((ss & 0xfffc) == 0)
raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
if ((ss & 3) != dpl)
@@ -2587,13 +2588,9 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend)
if (is_iret)
POPW(ssp, sp, sp_mask, new_eflags);
}
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL) {
fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
new_cs, new_eip, shift, addend);
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
}
#endif
LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
new_cs, new_eip, shift, addend);
LOG_PCALL_STATE(env);
if ((new_cs & 0xfffc) == 0)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
if (load_segment(&e1, &e2, new_cs) != 0)
@@ -2643,12 +2640,8 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend)
POPW(ssp, sp, sp_mask, new_esp);
POPW(ssp, sp, sp_mask, new_ss);
}
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL) {
fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
new_ss, new_esp);
}
#endif
if ((new_ss & 0xfffc) == 0) {
#ifdef TARGET_X86_64
/* NULL ss is allowed in long mode if cpl != 3*/
target-mips/translate.c
+22 -92
View File
@@ -521,8 +521,14 @@ do { \
ctx->pc, ctx->opcode , ##args); \
} \
} while (0)
#define LOG_DISAS(...) \
do { \
if (loglevel & CPU_LOG_TB_IN_ASM) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
#define MIPS_DEBUG(fmt, args...) do { } while(0)
#define LOG_DISAS(...) do { } while (0)
#endif
#define MIPS_INVAL(op) \
@@ -758,12 +764,7 @@ static inline void gen_save_pc(target_ulong pc)
static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
{
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "hflags %08x saved %08x\n",
ctx->hflags, ctx->saved_hflags);
}
#endif
LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
if (do_save_pc && ctx->pc != ctx->saved_pc) {
gen_save_pc(ctx->pc);
ctx->saved_pc = ctx->pc;
@@ -2314,11 +2315,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile,
"Branch in delay slot at PC 0x" TARGET_FMT_lx "\n",
ctx->pc);
}
LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
#endif
generate_exception(ctx, EXCP_RI);
goto out;
@@ -3295,21 +3292,11 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
generate_exception(ctx, EXCP_RI);
}
@@ -3899,12 +3886,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
if (use_icount) {
gen_io_end();
@@ -3913,12 +3895,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
generate_exception(ctx, EXCP_RI);
}
@@ -4481,21 +4458,11 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
generate_exception(ctx, EXCP_RI);
}
@@ -5072,12 +5039,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
if (use_icount) {
gen_io_end();
@@ -5086,12 +5048,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
generate_exception(ctx, EXCP_RI);
}
#endif /* TARGET_MIPS64 */
@@ -5249,24 +5206,14 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",
rt, u, sel, h);
}
#endif
LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
gen_store_gpr(t0, rd);
tcg_temp_free(t0);
return;
die:
tcg_temp_free(t0);
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",
rt, u, sel, h);
}
#endif
LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
generate_exception(ctx, EXCP_RI);
}
@@ -5424,23 +5371,13 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",
rd, u, sel, h);
}
#endif
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
tcg_temp_free(t0);
return;
die:
tcg_temp_free(t0);
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",
rd, u, sel, h);
}
#endif
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
generate_exception(ctx, EXCP_RI);
}
@@ -8272,11 +8209,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
#ifdef MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
fprintf(logfile, "\ntb %p idx %d hflags %04x\n",
tb, ctx.mem_idx, ctx.hflags);
#endif
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
gen_icount_start();
while (ctx.bstate == BS_NONE) {
if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
@@ -8364,10 +8297,7 @@ done_generating:
tb->icount = num_insns;
}
#ifdef DEBUG_DISAS
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
fprintf(logfile, "\n");
#endif
LOG_DISAS("\n");
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
target-ppc/helper.c
+105 -223
View File
File diff suppressed because it is too large Load Diff
target-ppc/op_helper.c
+19 -45
View File
@@ -28,6 +28,16 @@
//#define DEBUG_EXCEPTIONS
//#define DEBUG_SOFTWARE_TLB
#ifdef DEBUG_SOFTWARE_TLB
# define LOG_SWTLB(...) do { \
if (loglevel) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_SWTLB(...) do { } while (0)
#endif
/*****************************************************************************/
/* Exceptions processing helpers */
@@ -3564,13 +3574,9 @@ static void do_6xx_tlb (target_ulong new_EPN, int is_code)
EPN = env->spr[SPR_DMISS];
}
way = (env->spr[SPR_SRR1] >> 17) & 1;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
" PTE1 " ADDRX " way %d\n",
__func__, new_EPN, EPN, CMP, RPN, way);
}
#endif
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
@@ -3596,13 +3602,9 @@ static void do_74xx_tlb (target_ulong new_EPN, int is_code)
CMP = env->spr[SPR_PTEHI];
EPN = env->spr[SPR_TLBMISS] & ~0x3;
way = env->spr[SPR_TLBMISS] & 0x3;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
" PTE1 " ADDRX " way %d\n",
__func__, new_EPN, EPN, CMP, RPN, way);
}
#endif
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
@@ -3726,22 +3728,14 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
ppcemb_tlb_t *tlb;
target_ulong page, end;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
}
#endif
LOG_SWTLB("%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
/* Invalidate previous TLB (if it's valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
LOG_SWTLB("%s: invalidate old TLB %d start " ADDRX
" end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
}
#endif
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
@@ -3766,26 +3760,18 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
}
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
tlb->attr = val & 0xFF;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
}
#endif
/* Invalidate new TLB (if valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
LOG_SWTLB("%s: invalidate TLB %d start " ADDRX
" end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
}
#endif
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
@@ -3795,11 +3781,7 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
{
ppcemb_tlb_t *tlb;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
}
#endif
LOG_SWTLB("%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
tlb->RPN = val & 0xFFFFFC00;
@@ -3808,17 +3790,13 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
tlb->prot |= PAGE_EXEC;
if (val & 0x100)
tlb->prot |= PAGE_WRITE;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
}
#endif
}
target_ulong helper_4xx_tlbsx (target_ulong address)
@@ -3833,12 +3811,8 @@ void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
target_ulong EPN, RPN, size;
int do_flush_tlbs;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
LOG_SWTLB("%s word %d entry %d value " ADDRX "\n",
__func__, word, (int)entry, value);
}
#endif
do_flush_tlbs = 0;
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
target-ppc/translate.c
+12 -12
View File
@@ -42,6 +42,14 @@
//#define PPC_DEBUG_DISAS
//#define DO_PPC_STATISTICS
#ifdef PPC_DEBUG_DISAS
# define LOG_DISAS(...) do { \
if (loglevel & CPU_LOG_TB_IN_ASM) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_DISAS(...) do { } while (0)
#endif
/*****************************************************************************/
/* Code translation helpers */
@@ -8232,13 +8240,9 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
gen_opc_icount[lj] = num_insns;
}
}
#if defined PPC_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "----------------\n");
fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir);
}
#endif
LOG_DISAS("----------------\n");
LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
if (unlikely(ctx.le_mode)) {
@@ -8246,13 +8250,9 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
} else {
ctx.opcode = ldl_code(ctx.nip);
}
#if defined PPC_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), little_endian ? "little" : "big");
}
#endif
ctx.nip += 4;
table = env->opcodes;
num_insns++;
vl.c
+16 -24
View File
@@ -154,6 +154,16 @@
//#define DEBUG_NET
//#define DEBUG_SLIRP
#ifdef DEBUG_IOPORT
# define LOG_IOPORT(...) do { \
if (loglevel & CPU_LOG_IOPORT) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_IOPORT(...) do { } while (0)
#endif
#ifdef TARGET_PPC
#define DEFAULT_RAM_SIZE 144
#else
@@ -409,10 +419,7 @@ void isa_unassign_ioport(int start, int length)
void cpu_outb(CPUState *env, int addr, int val)
{
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "outb: %04x %02x\n", addr, val);
#endif
LOG_IOPORT("outb: %04x %02x\n", addr, val);
ioport_write(0, addr, val);
#ifdef USE_KQEMU
if (env)
@@ -422,10 +429,7 @@ void cpu_outb(CPUState *env, int addr, int val)
void cpu_outw(CPUState *env, int addr, int val)
{
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "outw: %04x %04x\n", addr, val);
#endif
LOG_IOPORT("outw: %04x %04x\n", addr, val);
ioport_write(1, addr, val);
#ifdef USE_KQEMU
if (env)
@@ -435,10 +439,7 @@ void cpu_outw(CPUState *env, int addr, int val)
void cpu_outl(CPUState *env, int addr, int val)
{
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "outl: %04x %08x\n", addr, val);
#endif
LOG_IOPORT("outl: %04x %08x\n", addr, val);
ioport_write(2, addr, val);
#ifdef USE_KQEMU
if (env)
@@ -450,10 +451,7 @@ int cpu_inb(CPUState *env, int addr)
{
int val;
val = ioport_read(0, addr);
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "inb : %04x %02x\n", addr, val);
#endif
LOG_IOPORT("inb : %04x %02x\n", addr, val);
#ifdef USE_KQEMU
if (env)
env->last_io_time = cpu_get_time_fast();
@@ -465,10 +463,7 @@ int cpu_inw(CPUState *env, int addr)
{
int val;
val = ioport_read(1, addr);
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "inw : %04x %04x\n", addr, val);
#endif
LOG_IOPORT("inw : %04x %04x\n", addr, val);
#ifdef USE_KQEMU
if (env)
env->last_io_time = cpu_get_time_fast();
@@ -480,10 +475,7 @@ int cpu_inl(CPUState *env, int addr)
{
int val;
val = ioport_read(2, addr);
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "inl : %04x %08x\n", addr, val);
#endif
LOG_IOPORT("inl : %04x %08x\n", addr, val);
#ifdef USE_KQEMU
if (env)
env->last_io_time = cpu_get_time_fast();