mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180820' into staging
First round of s390x patches for 3.1: - add compat machine for 3.1 - remove deprecated 's390-squash-mcss' option - cpu models: add "max" cpu model, enhance feature group code - kvm: add support for etoken facility and huge page backing # gpg: Signature made Mon 20 Aug 2018 13:47:38 BST # gpg: using RSA key DECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # gpg: aka "Cornelia Huck <cohuck@kernel.org>" # gpg: aka "Cornelia Huck <cohuck@redhat.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20180820: s390x: Enable KVM huge page backing support s390x/kvm: add etoken facility linux-headers: update s390x/cpumodel: Add "-cpu max" support s390x: remove 's390-squash-mcss' option s390x/cpumodel: enum type S390FeatGroup now gets generated s390x: introduce 3.1 compat machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
+1
-4
@@ -98,13 +98,10 @@ static void emulated_ccw_3270_realize(DeviceState *ds, Error **errp)
|
||||
EmulatedCcw3270Class *ck = EMULATED_CCW_3270_GET_CLASS(dev);
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||||
CcwDevice *cdev = CCW_DEVICE(ds);
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CCWDeviceClass *cdk = CCW_DEVICE_GET_CLASS(cdev);
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DeviceState *parent = DEVICE(cdev);
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BusState *qbus = qdev_get_parent_bus(parent);
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VirtualCssBus *cbus = VIRTUAL_CSS_BUS(qbus);
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SubchDev *sch;
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Error *err = NULL;
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sch = css_create_sch(cdev->devno, cbus->squash_mcss, errp);
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sch = css_create_sch(cdev->devno, errp);
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if (!sch) {
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return;
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}
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@@ -106,7 +106,6 @@ VirtualCssBus *virtual_css_bus_init(void)
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/* Create bus on bridge device */
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bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
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cbus = VIRTUAL_CSS_BUS(bus);
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cbus->squash_mcss = s390_get_squash_mcss();
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/* Enable hotplugging */
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qbus_set_hotplug_handler(bus, dev, &error_abort);
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+2
-4
@@ -2359,15 +2359,13 @@ const PropertyInfo css_devid_ro_propinfo = {
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.get = get_css_devid,
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};
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SubchDev *css_create_sch(CssDevId bus_id, bool squash_mcss, Error **errp)
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SubchDev *css_create_sch(CssDevId bus_id, Error **errp)
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{
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uint16_t schid = 0;
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SubchDev *sch;
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if (bus_id.valid) {
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if (squash_mcss) {
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bus_id.cssid = channel_subsys.default_cssid;
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} else if (!channel_subsys.css[bus_id.cssid]) {
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if (!channel_subsys.css[bus_id.cssid]) {
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css_create_css_image(bus_id.cssid, false);
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}
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+1
-3
@@ -67,8 +67,6 @@ static void s390_ccw_realize(S390CCWDevice *cdev, char *sysfsdev, Error **errp)
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CcwDevice *ccw_dev = CCW_DEVICE(cdev);
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CCWDeviceClass *ck = CCW_DEVICE_GET_CLASS(ccw_dev);
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DeviceState *parent = DEVICE(ccw_dev);
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BusState *qbus = qdev_get_parent_bus(parent);
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VirtualCssBus *cbus = VIRTUAL_CSS_BUS(qbus);
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SubchDev *sch;
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int ret;
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Error *err = NULL;
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@@ -78,7 +76,7 @@ static void s390_ccw_realize(S390CCWDevice *cdev, char *sysfsdev, Error **errp)
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goto out_err_propagate;
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}
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sch = css_create_sch(ccw_dev->devno, cbus->squash_mcss, &err);
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sch = css_create_sch(ccw_dev->devno, &err);
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if (!sch) {
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goto out_mdevid_free;
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}
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+18
-36
@@ -282,19 +282,8 @@ static void ccw_init(MachineState *machine)
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virtio_ccw_register_hcalls();
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s390_enable_css_support(s390_cpu_addr2state(0));
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/*
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* Non mcss-e enabled guests only see the devices from the default
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* css, which is determined by the value of the squash_mcss property.
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*/
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if (css_bus->squash_mcss) {
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ret = css_create_css_image(0, true);
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} else {
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ret = css_create_css_image(VIRTUAL_CSSID, true);
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}
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if (qemu_opt_get(qemu_get_machine_opts(), "s390-squash-mcss")) {
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warn_report("The machine property 's390-squash-mcss' is deprecated"
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" (obsoleted by lifting the cssid restrictions).");
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}
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ret = css_create_css_image(VIRTUAL_CSSID, true);
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assert(ret == 0);
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if (css_migration_enabled()) {
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@@ -575,21 +564,6 @@ static void machine_set_loadparm(Object *obj, const char *val, Error **errp)
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ms->loadparm[i] = ' '; /* pad right with spaces */
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}
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}
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static inline bool machine_get_squash_mcss(Object *obj, Error **errp)
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{
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S390CcwMachineState *ms = S390_CCW_MACHINE(obj);
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return ms->s390_squash_mcss;
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}
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static inline void machine_set_squash_mcss(Object *obj, bool value,
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Error **errp)
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{
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S390CcwMachineState *ms = S390_CCW_MACHINE(obj);
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ms->s390_squash_mcss = value;
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}
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static inline void s390_machine_initfn(Object *obj)
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{
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object_property_add_bool(obj, "aes-key-wrap",
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@@ -614,13 +588,6 @@ static inline void s390_machine_initfn(Object *obj)
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" to upper case) to pass to machine loader, boot manager,"
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" and guest kernel",
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NULL);
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object_property_add_bool(obj, "s390-squash-mcss",
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machine_get_squash_mcss,
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machine_set_squash_mcss, NULL);
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object_property_set_description(obj, "s390-squash-mcss", "(deprecated) "
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"enable/disable squashing subchannels into the default css",
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NULL);
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object_property_set_bool(obj, false, "s390-squash-mcss", NULL);
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}
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static const TypeInfo ccw_machine_info = {
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@@ -673,6 +640,9 @@ bool css_migration_enabled(void)
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} \
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type_init(ccw_machine_register_##suffix)
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#define CCW_COMPAT_3_0 \
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HW_COMPAT_3_0
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#define CCW_COMPAT_2_12 \
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HW_COMPAT_2_12
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@@ -761,14 +731,26 @@ bool css_migration_enabled(void)
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.value = "0",\
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},
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static void ccw_machine_3_1_instance_options(MachineState *machine)
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{
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||||
}
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||||
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static void ccw_machine_3_1_class_options(MachineClass *mc)
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{
|
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}
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DEFINE_CCW_MACHINE(3_1, "3.1", true);
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static void ccw_machine_3_0_instance_options(MachineState *machine)
|
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{
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ccw_machine_3_1_instance_options(machine);
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}
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||||
static void ccw_machine_3_0_class_options(MachineClass *mc)
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{
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ccw_machine_3_1_class_options(mc);
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SET_MACHINE_COMPAT(mc, CCW_COMPAT_3_0);
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}
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DEFINE_CCW_MACHINE(3_0, "3.0", true);
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DEFINE_CCW_MACHINE(3_0, "3.0", false);
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static void ccw_machine_2_12_instance_options(MachineState *machine)
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{
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@@ -694,13 +694,10 @@ static void virtio_ccw_device_realize(VirtioCcwDevice *dev, Error **errp)
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VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_GET_CLASS(dev);
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CcwDevice *ccw_dev = CCW_DEVICE(dev);
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CCWDeviceClass *ck = CCW_DEVICE_GET_CLASS(ccw_dev);
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DeviceState *parent = DEVICE(ccw_dev);
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BusState *qbus = qdev_get_parent_bus(parent);
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VirtualCssBus *cbus = VIRTUAL_CSS_BUS(qbus);
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SubchDev *sch;
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Error *err = NULL;
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sch = css_create_sch(ccw_dev->devno, cbus->squash_mcss, errp);
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sch = css_create_sch(ccw_dev->devno, errp);
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if (!sch) {
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return;
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}
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@@ -1,6 +1,9 @@
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#ifndef HW_COMPAT_H
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#define HW_COMPAT_H
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#define HW_COMPAT_3_0 \
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/* empty */
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#define HW_COMPAT_2_12 \
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{\
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.driver = "migration",\
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@@ -28,7 +28,6 @@ typedef struct VirtualCssBridge {
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/* virtual css bus type */
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typedef struct VirtualCssBus {
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BusState parent_obj;
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bool squash_mcss;
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} VirtualCssBus;
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#define TYPE_VIRTUAL_CSS_BUS "virtual-css-bus"
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@@ -266,11 +266,8 @@ extern const PropertyInfo css_devid_ro_propinfo;
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/**
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* Create a subchannel for the given bus id.
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*
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* If @p bus_id is valid, and @p squash_mcss is true, verify that it is
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* not already in use in the default css, and find a free devno from the
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* default css image for it.
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* If @p bus_id is valid, and @p squash_mcss is false, verify that it is
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* not already in use, and find a free devno for it.
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* If @p bus_id is valid, verify that it is not already in use, and find a
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* free devno for it.
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* If @p bus_id is not valid find a free subchannel id and device number
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* across all subchannel sets and all css images starting from the default
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* css image.
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@@ -282,7 +279,7 @@ extern const PropertyInfo css_devid_ro_propinfo;
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* The caller becomes owner of the returned subchannel structure and
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* is responsible for unregistering and freeing it.
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*/
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SubchDev *css_create_sch(CssDevId bus_id, bool squash_mcss, Error **errp);
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SubchDev *css_create_sch(CssDevId bus_id, Error **errp);
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/** Turn on css migration */
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void css_register_vmstate(void);
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@@ -29,7 +29,6 @@ typedef struct S390CcwMachineState {
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bool aes_key_wrap;
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bool dea_key_wrap;
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uint8_t loadparm[8];
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bool s390_squash_mcss;
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} S390CcwMachineState;
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typedef struct S390CcwMachineClass {
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@@ -28,6 +28,7 @@
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#define KVM_FEATURE_PV_UNHALT 7
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#define KVM_FEATURE_PV_TLB_FLUSH 9
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#define KVM_FEATURE_ASYNC_PF_VMEXIT 10
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#define KVM_FEATURE_PV_SEND_IPI 11
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#define KVM_HINTS_REALTIME 0
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@@ -182,6 +182,7 @@ extern "C" {
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#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
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#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
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#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
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#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
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/* add more to the end as needed */
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#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
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@@ -297,6 +298,19 @@ extern "C" {
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||||
*/
|
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#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
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||||
|
||||
/*
|
||||
* Qualcomm Compressed Format
|
||||
*
|
||||
* Refers to a compressed variant of the base format that is compressed.
|
||||
* Implementation may be platform and base-format specific.
|
||||
*
|
||||
* Each macrotile consists of m x n (mostly 4 x 4) tiles.
|
||||
* Pixel data pitch/stride is aligned with macrotile width.
|
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* Pixel data height is aligned with macrotile height.
|
||||
* Entire pixel data buffer is aligned with 4k(bytes).
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
|
||||
|
||||
/* Vivante framebuffer modifiers */
|
||||
|
||||
/*
|
||||
@@ -383,6 +397,23 @@ extern "C" {
|
||||
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
|
||||
fourcc_mod_code(NVIDIA, 0x15)
|
||||
|
||||
/*
|
||||
* Some Broadcom modifiers take parameters, for example the number of
|
||||
* vertical lines in the image. Reserve the lower 32 bits for modifier
|
||||
* type, and the next 24 bits for parameters. Top 8 bits are the
|
||||
* vendor code.
|
||||
*/
|
||||
#define __fourcc_mod_broadcom_param_shift 8
|
||||
#define __fourcc_mod_broadcom_param_bits 48
|
||||
#define fourcc_mod_broadcom_code(val, params) \
|
||||
fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val))
|
||||
#define fourcc_mod_broadcom_param(m) \
|
||||
((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
|
||||
((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
|
||||
#define fourcc_mod_broadcom_mod(m) \
|
||||
((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
|
||||
__fourcc_mod_broadcom_param_shift))
|
||||
|
||||
/*
|
||||
* Broadcom VC4 "T" format
|
||||
*
|
||||
@@ -404,6 +435,151 @@ extern "C" {
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
|
||||
|
||||
/*
|
||||
* Broadcom SAND format
|
||||
*
|
||||
* This is the native format that the H.264 codec block uses. For VC4
|
||||
* HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
|
||||
*
|
||||
* The image can be considered to be split into columns, and the
|
||||
* columns are placed consecutively into memory. The width of those
|
||||
* columns can be either 32, 64, 128, or 256 pixels, but in practice
|
||||
* only 128 pixel columns are used.
|
||||
*
|
||||
* The pitch between the start of each column is set to optimally
|
||||
* switch between SDRAM banks. This is passed as the number of lines
|
||||
* of column width in the modifier (we can't use the stride value due
|
||||
* to various core checks that look at it , so you should set the
|
||||
* stride to width*cpp).
|
||||
*
|
||||
* Note that the column height for this format modifier is the same
|
||||
* for all of the planes, assuming that each column contains both Y
|
||||
* and UV. Some SAND-using hardware stores UV in a separate tiled
|
||||
* image from Y to reduce the column height, which is not supported
|
||||
* with these modifiers.
|
||||
*/
|
||||
|
||||
#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
|
||||
fourcc_mod_broadcom_code(2, v)
|
||||
#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
|
||||
fourcc_mod_broadcom_code(3, v)
|
||||
#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
|
||||
fourcc_mod_broadcom_code(4, v)
|
||||
#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
|
||||
fourcc_mod_broadcom_code(5, v)
|
||||
|
||||
#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
|
||||
DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
|
||||
#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
|
||||
DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
|
||||
#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
|
||||
DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
|
||||
#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
|
||||
DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
|
||||
|
||||
/* Broadcom UIF format
|
||||
*
|
||||
* This is the common format for the current Broadcom multimedia
|
||||
* blocks, including V3D 3.x and newer, newer video codecs, and
|
||||
* displays.
|
||||
*
|
||||
* The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
|
||||
* and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
|
||||
* stored in columns, with padding between the columns to ensure that
|
||||
* moving from one column to the next doesn't hit the same SDRAM page
|
||||
* bank.
|
||||
*
|
||||
* To calculate the padding, it is assumed that each hardware block
|
||||
* and the software driving it knows the platform's SDRAM page size,
|
||||
* number of banks, and XOR address, and that it's identical between
|
||||
* all blocks using the format. This tiling modifier will use XOR as
|
||||
* necessary to reduce the padding. If a hardware block can't do XOR,
|
||||
* the assumption is that a no-XOR tiling modifier will be created.
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
|
||||
|
||||
/*
|
||||
* Arm Framebuffer Compression (AFBC) modifiers
|
||||
*
|
||||
* AFBC is a proprietary lossless image compression protocol and format.
|
||||
* It provides fine-grained random access and minimizes the amount of data
|
||||
* transferred between IP blocks.
|
||||
*
|
||||
* AFBC has several features which may be supported and/or used, which are
|
||||
* represented using bits in the modifier. Not all combinations are valid,
|
||||
* and different devices or use-cases may support different combinations.
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
|
||||
|
||||
/*
|
||||
* AFBC superblock size
|
||||
*
|
||||
* Indicates the superblock size(s) used for the AFBC buffer. The buffer
|
||||
* size (in pixels) must be aligned to a multiple of the superblock size.
|
||||
* Four lowest significant bits(LSBs) are reserved for block size.
|
||||
*/
|
||||
#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
|
||||
#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
|
||||
#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
|
||||
|
||||
/*
|
||||
* AFBC lossless colorspace transform
|
||||
*
|
||||
* Indicates that the buffer makes use of the AFBC lossless colorspace
|
||||
* transform.
|
||||
*/
|
||||
#define AFBC_FORMAT_MOD_YTR (1ULL << 4)
|
||||
|
||||
/*
|
||||
* AFBC block-split
|
||||
*
|
||||
* Indicates that the payload of each superblock is split. The second
|
||||
* half of the payload is positioned at a predefined offset from the start
|
||||
* of the superblock payload.
|
||||
*/
|
||||
#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
|
||||
|
||||
/*
|
||||
* AFBC sparse layout
|
||||
*
|
||||
* This flag indicates that the payload of each superblock must be stored at a
|
||||
* predefined position relative to the other superblocks in the same AFBC
|
||||
* buffer. This order is the same order used by the header buffer. In this mode
|
||||
* each superblock is given the same amount of space as an uncompressed
|
||||
* superblock of the particular format would require, rounding up to the next
|
||||
* multiple of 128 bytes in size.
|
||||
*/
|
||||
#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
|
||||
|
||||
/*
|
||||
* AFBC copy-block restrict
|
||||
*
|
||||
* Buffers with this flag must obey the copy-block restriction. The restriction
|
||||
* is such that there are no copy-blocks referring across the border of 8x8
|
||||
* blocks. For the subsampled data the 8x8 limitation is also subsampled.
|
||||
*/
|
||||
#define AFBC_FORMAT_MOD_CBR (1ULL << 7)
|
||||
|
||||
/*
|
||||
* AFBC tiled layout
|
||||
*
|
||||
* The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
|
||||
* superblocks inside a tile are stored together in memory. 8x8 tiles are used
|
||||
* for pixel formats up to and including 32 bpp while 4x4 tiles are used for
|
||||
* larger bpp formats. The order between the tiles is scan line.
|
||||
* When the tiled layout is used, the buffer size (in pixels) must be aligned
|
||||
* to the tile size.
|
||||
*/
|
||||
#define AFBC_FORMAT_MOD_TILED (1ULL << 8)
|
||||
|
||||
/*
|
||||
* AFBC solid color blocks
|
||||
*
|
||||
* Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
|
||||
* can be reduced if a whole superblock is a single color.
|
||||
*/
|
||||
#define AFBC_FORMAT_MOD_SC (1ULL << 9)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -226,7 +226,7 @@ enum tunable_id {
|
||||
ETHTOOL_TX_COPYBREAK,
|
||||
ETHTOOL_PFC_PREVENTION_TOUT, /* timeout in msecs */
|
||||
/*
|
||||
* Add your fresh new tubale attribute above and remember to update
|
||||
* Add your fresh new tunable attribute above and remember to update
|
||||
* tunable_strings[] in net/core/ethtool.c
|
||||
*/
|
||||
__ETHTOOL_TUNABLE_COUNT,
|
||||
@@ -870,7 +870,8 @@ struct ethtool_flow_ext {
|
||||
* includes the %FLOW_EXT or %FLOW_MAC_EXT flag
|
||||
* (see &struct ethtool_flow_ext description).
|
||||
* @ring_cookie: RX ring/queue index to deliver to, or %RX_CLS_FLOW_DISC
|
||||
* if packets should be discarded
|
||||
* if packets should be discarded, or %RX_CLS_FLOW_WAKE if the
|
||||
* packets should be used for Wake-on-LAN with %WAKE_FILTER
|
||||
* @location: Location of rule in the table. Locations must be
|
||||
* numbered such that a flow matching multiple rules will be
|
||||
* classified according to the first (lowest numbered) rule.
|
||||
@@ -902,13 +903,13 @@ struct ethtool_rx_flow_spec {
|
||||
static inline uint64_t ethtool_get_flow_spec_ring(uint64_t ring_cookie)
|
||||
{
|
||||
return ETHTOOL_RX_FLOW_SPEC_RING & ring_cookie;
|
||||
};
|
||||
}
|
||||
|
||||
static inline uint64_t ethtool_get_flow_spec_ring_vf(uint64_t ring_cookie)
|
||||
{
|
||||
return (ETHTOOL_RX_FLOW_SPEC_RING_VF & ring_cookie) >>
|
||||
ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
|
||||
};
|
||||
}
|
||||
|
||||
/**
|
||||
* struct ethtool_rxnfc - command to get or set RX flow classification rules
|
||||
@@ -1634,6 +1635,7 @@ static inline int ethtool_validate_duplex(uint8_t duplex)
|
||||
#define WAKE_ARP (1 << 4)
|
||||
#define WAKE_MAGIC (1 << 5)
|
||||
#define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */
|
||||
#define WAKE_FILTER (1 << 7)
|
||||
|
||||
/* L2-L4 network traffic flow types */
|
||||
#define TCP_V4_FLOW 0x01 /* hash or spec (tcp_ip4_spec) */
|
||||
@@ -1671,6 +1673,7 @@ static inline int ethtool_validate_duplex(uint8_t duplex)
|
||||
#define RXH_DISCARD (1 << 31)
|
||||
|
||||
#define RX_CLS_FLOW_DISC 0xffffffffffffffffULL
|
||||
#define RX_CLS_FLOW_WAKE 0xfffffffffffffffeULL
|
||||
|
||||
/* Special RX classification rule insert location values */
|
||||
#define RX_CLS_LOC_SPECIAL 0x80000000 /* flag */
|
||||
|
||||
@@ -636,6 +636,7 @@
|
||||
#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
|
||||
#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
|
||||
#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
|
||||
#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
|
||||
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
|
||||
#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
|
||||
#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
|
||||
@@ -960,8 +961,9 @@
|
||||
#define PCI_REBAR_CTRL 8 /* control register */
|
||||
#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */
|
||||
#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */
|
||||
#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */
|
||||
#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */
|
||||
#define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */
|
||||
#define PCI_REBAR_CTRL_BAR_SHIFT 8 /* shift for BAR size */
|
||||
|
||||
/* Dynamic Power Allocation */
|
||||
#define PCI_DPA_CAP 4 /* capability register */
|
||||
|
||||
@@ -45,11 +45,14 @@
|
||||
/* We've given up on this device. */
|
||||
#define VIRTIO_CONFIG_S_FAILED 0x80
|
||||
|
||||
/* Some virtio feature bits (currently bits 28 through 32) are reserved for the
|
||||
* transport being used (eg. virtio_ring), the rest are per-device feature
|
||||
* bits. */
|
||||
/*
|
||||
* Virtio feature bits VIRTIO_TRANSPORT_F_START through
|
||||
* VIRTIO_TRANSPORT_F_END are reserved for the transport
|
||||
* being used (e.g. virtio_ring, virtio_pci etc.), the
|
||||
* rest are per-device feature bits.
|
||||
*/
|
||||
#define VIRTIO_TRANSPORT_F_START 28
|
||||
#define VIRTIO_TRANSPORT_F_END 34
|
||||
#define VIRTIO_TRANSPORT_F_END 38
|
||||
|
||||
#ifndef VIRTIO_CONFIG_NO_LEGACY
|
||||
/* Do we get callbacks when the ring is completely used, even if we've
|
||||
@@ -71,4 +74,9 @@
|
||||
* this is for compatibility with legacy systems.
|
||||
*/
|
||||
#define VIRTIO_F_IOMMU_PLATFORM 33
|
||||
|
||||
/*
|
||||
* Does the device support Single Root I/O Virtualization?
|
||||
*/
|
||||
#define VIRTIO_F_SR_IOV 37
|
||||
#endif /* _LINUX_VIRTIO_CONFIG_H */
|
||||
|
||||
@@ -734,9 +734,11 @@ __SYSCALL(__NR_pkey_free, sys_pkey_free)
|
||||
__SYSCALL(__NR_statx, sys_statx)
|
||||
#define __NR_io_pgetevents 292
|
||||
__SC_COMP(__NR_io_pgetevents, sys_io_pgetevents, compat_sys_io_pgetevents)
|
||||
#define __NR_rseq 293
|
||||
__SYSCALL(__NR_rseq, sys_rseq)
|
||||
|
||||
#undef __NR_syscalls
|
||||
#define __NR_syscalls 293
|
||||
#define __NR_syscalls 294
|
||||
|
||||
/*
|
||||
* 32 bit systems traditionally used different
|
||||
|
||||
@@ -388,17 +388,19 @@
|
||||
#define __NR_pkey_alloc (__NR_Linux + 364)
|
||||
#define __NR_pkey_free (__NR_Linux + 365)
|
||||
#define __NR_statx (__NR_Linux + 366)
|
||||
#define __NR_rseq (__NR_Linux + 367)
|
||||
#define __NR_io_pgetevents (__NR_Linux + 368)
|
||||
|
||||
|
||||
/*
|
||||
* Offset of the last Linux o32 flavoured syscall
|
||||
*/
|
||||
#define __NR_Linux_syscalls 366
|
||||
#define __NR_Linux_syscalls 368
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
|
||||
|
||||
#define __NR_O32_Linux 4000
|
||||
#define __NR_O32_Linux_syscalls 366
|
||||
#define __NR_O32_Linux_syscalls 368
|
||||
|
||||
#if _MIPS_SIM == _MIPS_SIM_ABI64
|
||||
|
||||
@@ -733,16 +735,18 @@
|
||||
#define __NR_pkey_alloc (__NR_Linux + 324)
|
||||
#define __NR_pkey_free (__NR_Linux + 325)
|
||||
#define __NR_statx (__NR_Linux + 326)
|
||||
#define __NR_rseq (__NR_Linux + 327)
|
||||
#define __NR_io_pgetevents (__NR_Linux + 328)
|
||||
|
||||
/*
|
||||
* Offset of the last Linux 64-bit flavoured syscall
|
||||
*/
|
||||
#define __NR_Linux_syscalls 326
|
||||
#define __NR_Linux_syscalls 328
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
|
||||
|
||||
#define __NR_64_Linux 5000
|
||||
#define __NR_64_Linux_syscalls 326
|
||||
#define __NR_64_Linux_syscalls 328
|
||||
|
||||
#if _MIPS_SIM == _MIPS_SIM_NABI32
|
||||
|
||||
@@ -1081,15 +1085,17 @@
|
||||
#define __NR_pkey_alloc (__NR_Linux + 328)
|
||||
#define __NR_pkey_free (__NR_Linux + 329)
|
||||
#define __NR_statx (__NR_Linux + 330)
|
||||
#define __NR_rseq (__NR_Linux + 331)
|
||||
#define __NR_io_pgetevents (__NR_Linux + 332)
|
||||
|
||||
/*
|
||||
* Offset of the last N32 flavoured syscall
|
||||
*/
|
||||
#define __NR_Linux_syscalls 330
|
||||
#define __NR_Linux_syscalls 332
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
|
||||
|
||||
#define __NR_N32_Linux 6000
|
||||
#define __NR_N32_Linux_syscalls 330
|
||||
#define __NR_N32_Linux_syscalls 332
|
||||
|
||||
#endif /* _ASM_UNISTD_H */
|
||||
|
||||
@@ -633,6 +633,7 @@ struct kvm_ppc_cpu_char {
|
||||
#define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
|
||||
|
||||
#define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe)
|
||||
#define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf)
|
||||
|
||||
/* Transactional Memory checkpointed state:
|
||||
* This is all GPRs, all VSX regs and a subset of SPRs
|
||||
|
||||
@@ -399,5 +399,6 @@
|
||||
#define __NR_pkey_free 385
|
||||
#define __NR_pkey_mprotect 386
|
||||
#define __NR_rseq 387
|
||||
#define __NR_io_pgetevents 388
|
||||
|
||||
#endif /* _ASM_POWERPC_UNISTD_H_ */
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
/*
|
||||
* KVM s390 specific structures and definitions
|
||||
*
|
||||
* Copyright IBM Corp. 2008
|
||||
* Copyright IBM Corp. 2008, 2018
|
||||
*
|
||||
* Author(s): Carsten Otte <cotte@de.ibm.com>
|
||||
* Christian Borntraeger <borntraeger@de.ibm.com>
|
||||
@@ -225,6 +225,7 @@ struct kvm_guest_debug_arch {
|
||||
#define KVM_SYNC_FPRS (1UL << 8)
|
||||
#define KVM_SYNC_GSCB (1UL << 9)
|
||||
#define KVM_SYNC_BPBC (1UL << 10)
|
||||
#define KVM_SYNC_ETOKEN (1UL << 11)
|
||||
/* length and alignment of the sdnx as a power of two */
|
||||
#define SDNXC 8
|
||||
#define SDNXL (1UL << SDNXC)
|
||||
@@ -258,6 +259,8 @@ struct kvm_sync_regs {
|
||||
struct {
|
||||
__u64 reserved1[2];
|
||||
__u64 gscb[4];
|
||||
__u64 etoken;
|
||||
__u64 etoken_extension;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user