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shutdown: Add source information to SHUTDOWN and RESET

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Time to wire up all the call sites that request a shutdown or
reset to use the enum added in the previous patch.

It would have been less churn to keep the common case with no
arguments as meaning guest-triggered, and only modified the
host-triggered code paths, via a wrapper function, but then we'd
still have to audit that I didn't miss any host-triggered spots;
changing the signature forces us to double-check that I correctly
categorized all callers.

Since command line options can change whether a guest reset request
causes an actual reset vs. a shutdown, it's easy to also add the
information to reset requests.

Signed-off-by: Eric Blake <eblake@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au> [ppc parts]
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> [SPARC part]
Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x parts]
Message-Id: <20170515214114.15442-5-eblake@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
This commit is contained in:
Eric Blake
2017-05-23 13:28:17 +02:00
committed by Markus Armbruster
parent 802f045a5f
commit cf83f14005
60 changed files with 98 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/acpi/core.c
+2 -2
View File
@@ -561,7 +561,7 @@ static void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val)
uint16_t sus_typ = (val >> 10) & 7;
switch(sus_typ) {
case 0: /* soft power off */
qemu_system_shutdown_request();
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
break;
case 1:
qemu_system_suspend_request();
@@ -569,7 +569,7 @@ static void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val)
default:
if (sus_typ == ar->pm1.cnt.s4_val) { /* S4 request */
qapi_event_send_suspend_disk(&error_abort);
qemu_system_shutdown_request();
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}
break;
}
hw/arm/highbank.c
+2 -2
View File
@@ -108,9 +108,9 @@ static void hb_regs_write(void *opaque, hwaddr offset,
if (offset == 0xf00) {
if (value == 1 || value == 2) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
} else if (value == 3) {
qemu_system_shutdown_request();
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}
}
hw/arm/integratorcp.c
+1 -1
View File
@@ -158,7 +158,7 @@ static void integratorcm_do_remap(IntegratorCMState *s)
static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
{
if (value & 8) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
if ((s->cm_ctrl ^ value) & 1) {
/* (value & 1) != 0 means the green "MISC LED" is lit.
hw/arm/musicpal.c
+1 -1
View File
@@ -898,7 +898,7 @@ static void mv88w8618_pit_write(void *opaque, hwaddr offset,
case MP_BOARD_RESET:
if (value == MP_BOARD_RESET_MAGIC) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
break;
}
hw/arm/omap1.c
+6 -4
View File
@@ -355,7 +355,7 @@ static void omap_wd_timer_write(void *opaque, hwaddr addr,
/* XXX: on T|E hardware somehow this has no effect,
* on Zire 71 it works as specified. */
s->reset = 1;
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
s->last_wr = value & 0xff;
@@ -1545,8 +1545,10 @@ static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
if (value & (1 << 11)) { /* SETARM_IDLE */
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
}
if (!(value & (1 << 10))) /* WKUP_MODE */
qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
if (!(value & (1 << 10))) { /* WKUP_MODE */
/* XXX: disable wakeup from IRQ */
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}
#define SET_CANIDLE(clock, bit) \
if (diff & (1 << bit)) { \
@@ -1693,7 +1695,7 @@ static void omap_clkm_write(void *opaque, hwaddr addr,
diff = s->clkm.arm_rstct1 ^ value;
s->clkm.arm_rstct1 = value & 0x0007;
if (value & 9) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
s->clkm.cold_start = 0xa;
}
if (diff & ~value & 4) { /* DSP_RST */
hw/arm/omap2.c
+1 -1
View File
@@ -1610,7 +1610,7 @@ static void omap_prcm_write(void *opaque, hwaddr addr,
case 0x450: /* RM_RSTCTRL_WKUP */
/* TODO: reset */
if (value & 2)
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
break;
case 0x454: /* RM_RSTTIME_WKUP */
s->rsttime_wkup = value & 0x1fff;
hw/arm/spitz.c
+1 -1
View File
@@ -848,7 +848,7 @@ static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
static void spitz_reset(void *opaque, int line, int level)
{
if (level) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
hw/arm/stellaris.c
+1 -1
View File
@@ -1197,7 +1197,7 @@ static
void do_sys_reset(void *opaque, int n, int level)
{
if (level) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
hw/arm/tosa.c
+1 -1
View File
@@ -90,7 +90,7 @@ static void tosa_out_switch(void *opaque, int line, int level)
static void tosa_reset(void *opaque, int line, int level)
{
if (level) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
hw/i386/pc.c
+1 -1
View File
@@ -519,7 +519,7 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val,
s->outport = val;
qemu_set_irq(s->a20_out, (val >> 1) & 1);
if ((val & 1) && !(oldval & 1)) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
hw/i386/xen/xen-hvm.c
+1 -1
View File
@@ -1398,7 +1398,7 @@ void xen_shutdown_fatal_error(const char *fmt, ...)
va_end(ap);
fprintf(stderr, "Will destroy the domain.\n");
/* destroy the domain */
qemu_system_shutdown_request();
qemu_system_shutdown_request(SHUTDOWN_CAUSE_HOST_ERROR);
}
void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t length)
hw/input/pckbd.c
+2 -2
View File
@@ -226,7 +226,7 @@ static void outport_write(KBDState *s, uint32_t val)
s->outport = val;
qemu_set_irq(s->a20_out, (val >> 1) & 1);
if (!(val & 1)) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
@@ -301,7 +301,7 @@ static void kbd_write_command(void *opaque, hwaddr addr,
s->outport &= ~KBD_OUT_A20;
break;
case KBD_CCMD_RESET:
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
break;
case KBD_CCMD_NO_OP:
/* ignore that */
hw/ipmi/ipmi.c
+2 -2
View File
@@ -44,14 +44,14 @@ static int ipmi_do_hw_op(IPMIInterface *s, enum ipmi_op op, int checkonly)
if (checkonly) {
return 0;
}
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
return 0;
case IPMI_POWEROFF_CHASSIS:
if (checkonly) {
return 0;
}
qemu_system_shutdown_request();
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
return 0;
case IPMI_SEND_NMI:
hw/isa/lpc_ich9.c
+1 -1
View File
@@ -606,7 +606,7 @@ static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val,
ICH9LPCState *lpc = opaque;
if (val & 4) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
return;
}
lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
hw/mips/boston.c
+1 -1
View File
@@ -232,7 +232,7 @@ static void boston_platreg_write(void *opaque, hwaddr addr,
break;
case PLAT_SOFTRST_CTL:
if (val & PLAT_SOFTRST_CTL_SYSRESET) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
break;
default:
hw/mips/mips_malta.c
+1 -1
View File
@@ -470,7 +470,7 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
/* SOFTRES Register */
case 0x00500:
if (val == 0x42)
qemu_system_reset_request ();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
break;
/* BRKRES Register */
hw/mips/mips_r4k.c
+2 -2
View File
@@ -53,9 +53,9 @@ static void mips_qemu_write (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
if ((addr & 0xffff) == 0 && val == 42)
qemu_system_reset_request ();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
else if ((addr & 0xffff) == 4 && val == 42)
qemu_system_shutdown_request ();
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}
static uint64_t mips_qemu_read (void *opaque, hwaddr addr,
hw/misc/arm_sysctl.c
+4 -4
View File
@@ -351,13 +351,13 @@ static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
break;
case SYS_CFG_SHUTDOWN:
if (site == SYS_CFG_SITE_MB && device == 0) {
qemu_system_shutdown_request();
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
return true;
}
break;
case SYS_CFG_REBOOT:
if (site == SYS_CFG_SITE_MB && device == 0) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
return true;
}
break;
@@ -429,7 +429,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
if (s->lockval == LOCK_VALUE) {
s->resetlevel = val;
if (val & 0x100) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
break;
@@ -438,7 +438,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
if (s->lockval == LOCK_VALUE) {
s->resetlevel = val;
if (val & 0x04) {
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
break;
hw/misc/cbus.c
+1 -1
View File
@@ -356,7 +356,7 @@ static inline void retu_write(CBusRetu *s, int reg, uint16_t val)
case RETU_REG_WATCHDOG:
if (val == 0 && (s->cc[0] & 2))
qemu_system_shutdown_request();
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
break;
case RETU_REG_TXCR:
hw/misc/macio/cuda.c
+2 -2
View File
@@ -612,7 +612,7 @@ static bool cuda_cmd_powerdown(CUDAState *s,
return false;
}
qemu_system_shutdown_request();
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
return true;
}
@@ -624,7 +624,7 @@ static bool cuda_cmd_reset_system(CUDAState *s,
return false;
}
qemu_system_reset_request();
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
return true;
}

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