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Merge tag 'pull-lu-20250828' of https://gitlab.com/rth7680/qemu into staging

Browse Source 
linux-user: do not print IP socket options by default
linux-user: Add strace for rseq
linux-user: Move get_elf_cpu_model to target/elfload.c
linux-user: Move get_elf_hwcap to target/elfload.c
linux-user: Move get_elf_hwcap2 to target/elfload.c
linux-user: Move get_elf_platform to target/elfload.c
linux-user: Move get_elf_base_platform to target/elfload.c
linux-user: Create init_main_thread in target/cpu_loop.c
semihosting: Retrieve stack top from image_info
semihosting: Initialize heap once per process

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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 28 Aug 2025 07:42:07 AM AEST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-lu-20250828' of https://gitlab.com/rth7680/qemu: (46 commits)
  linux-user: do not print IP socket options by default
  linux-user: Add strace for rseq
  linux-user: Remove do_init_main_thread
  linux-user/hexagon: Create init_main_thread
  linux-user/xtensa: Create init_main_thread
  linux-user/hppa: Create init_main_thread
  linux-user/riscv: Create init_main_thread
  linux-user/s390x: Create init_main_thread
  linux-user/alpha: Create init_main_thread
  linux-user/m68k: Create init_main_thread
  linux-user/sh4: Create init_main_thread
  linux-user/openrisc: Create init_main_thread
  linux-user/microblaze: Create init_main_thread
  linux-user/mips: Create init_main_thread
  linux-user/loongarch64: Create init_main_thread
  linux-user/ppc: Create init_main_thread
  linux-user/sparc: Create init_main_thread
  linux-user/aarch64: Create init_main_thread
  linux-user/arm: Remove a.out startup remenents
  linux-user/arm: Create init_main_thread
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2025-08-28 09:24:36 +10:00
parent d35b9e4eae a5fbf1c617
commit ca18b336e1
69 changed files with 1528 additions and 1629 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/core/loader.c
-4
View File
@@ -295,10 +295,6 @@ static void *load_at(int fd, off_t offset, size_t size)
return ptr;
}
#ifdef ELF_CLASS
#undef ELF_CLASS
#endif
#define ELF_CLASS ELFCLASS32
#include "elf.h"
include/qemu/osdep.h
+8
View File
@@ -133,6 +133,14 @@ QEMU_EXTERN_C int daemon(int, int);
#include <setjmp.h>
#include <signal.h>
/*
* Avoid conflict with linux/arch/powerpc/include/uapi/asm/elf.h, included
* from <asm/sigcontext.h>, but we might as well do this unconditionally.
*/
#undef ELF_CLASS
#undef ELF_DATA
#undef ELF_ARCH
#ifdef CONFIG_IOVEC
#include <sys/uio.h>
#endif
include/user/cpu_loop.h
-4
View File
@@ -81,8 +81,4 @@ void target_exception_dump(CPUArchState *env, const char *fmt, int code);
#define EXCP_DUMP(env, fmt, code) \
target_exception_dump(env, fmt, code)
typedef struct target_pt_regs target_pt_regs;
void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs);
#endif
linux-user/aarch64/cpu_loop.c
+6 -16
View File
@@ -137,13 +137,10 @@ void cpu_loop(CPUARMState *env)
}
}
void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs)
void init_main_thread(CPUState *cs, struct image_info *info)
{
CPUARMState *env = cpu_env(cs);
ARMCPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
TaskState *ts = get_task_state(cs);
struct image_info *info = ts->info;
int i;
if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
fprintf(stderr,
@@ -151,14 +148,12 @@ void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs)
exit(EXIT_FAILURE);
}
for (i = 0; i < 31; i++) {
env->xregs[i] = regs->regs[i];
}
env->pc = regs->pc;
env->xregs[31] = regs->sp;
env->pc = info->entry & ~0x3ULL;
env->xregs[31] = info->start_stack;
#if TARGET_BIG_ENDIAN
env->cp15.sctlr_el[1] |= SCTLR_E0E;
for (i = 1; i < 4; ++i) {
for (int i = 1; i < 4; ++i) {
env->cp15.sctlr_el[i] |= SCTLR_EE;
}
arm_rebuild_hflags(env);
@@ -167,9 +162,4 @@ void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs)
if (cpu_isar_feature(aa64_pauth, cpu)) {
qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys));
}
ts->stack_base = info->start_stack;
ts->heap_base = info->brk;
/* This will be filled in on the first SYS_HEAPINFO call. */
ts->heap_limit = 0;
}
linux-user/aarch64/elfload.c
+349
View File
@@ -0,0 +1,349 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include "qemu/osdep.h"
#include "qemu.h"
#include "loader.h"
#include "target/arm/cpu-features.h"
const char *get_elf_cpu_model(uint32_t eflags)
{
return "any";
}
enum {
ARM_HWCAP_A64_FP = 1 << 0,
ARM_HWCAP_A64_ASIMD = 1 << 1,
ARM_HWCAP_A64_EVTSTRM = 1 << 2,
ARM_HWCAP_A64_AES = 1 << 3,
ARM_HWCAP_A64_PMULL = 1 << 4,
ARM_HWCAP_A64_SHA1 = 1 << 5,
ARM_HWCAP_A64_SHA2 = 1 << 6,
ARM_HWCAP_A64_CRC32 = 1 << 7,
ARM_HWCAP_A64_ATOMICS = 1 << 8,
ARM_HWCAP_A64_FPHP = 1 << 9,
ARM_HWCAP_A64_ASIMDHP = 1 << 10,
ARM_HWCAP_A64_CPUID = 1 << 11,
ARM_HWCAP_A64_ASIMDRDM = 1 << 12,
ARM_HWCAP_A64_JSCVT = 1 << 13,
ARM_HWCAP_A64_FCMA = 1 << 14,
ARM_HWCAP_A64_LRCPC = 1 << 15,
ARM_HWCAP_A64_DCPOP = 1 << 16,
ARM_HWCAP_A64_SHA3 = 1 << 17,
ARM_HWCAP_A64_SM3 = 1 << 18,
ARM_HWCAP_A64_SM4 = 1 << 19,
ARM_HWCAP_A64_ASIMDDP = 1 << 20,
ARM_HWCAP_A64_SHA512 = 1 << 21,
ARM_HWCAP_A64_SVE = 1 << 22,
ARM_HWCAP_A64_ASIMDFHM = 1 << 23,
ARM_HWCAP_A64_DIT = 1 << 24,
ARM_HWCAP_A64_USCAT = 1 << 25,
ARM_HWCAP_A64_ILRCPC = 1 << 26,
ARM_HWCAP_A64_FLAGM = 1 << 27,
ARM_HWCAP_A64_SSBS = 1 << 28,
ARM_HWCAP_A64_SB = 1 << 29,
ARM_HWCAP_A64_PACA = 1 << 30,
ARM_HWCAP_A64_PACG = 1ULL << 31,
ARM_HWCAP_A64_GCS = 1ULL << 32,
ARM_HWCAP_A64_CMPBR = 1ULL << 33,
ARM_HWCAP_A64_FPRCVT = 1ULL << 34,
ARM_HWCAP_A64_F8MM8 = 1ULL << 35,
ARM_HWCAP_A64_F8MM4 = 1ULL << 36,
ARM_HWCAP_A64_SVE_F16MM = 1ULL << 37,
ARM_HWCAP_A64_SVE_ELTPERM = 1ULL << 38,
ARM_HWCAP_A64_SVE_AES2 = 1ULL << 39,
ARM_HWCAP_A64_SVE_BFSCALE = 1ULL << 40,
ARM_HWCAP_A64_SVE2P2 = 1ULL << 41,
ARM_HWCAP_A64_SME2P2 = 1ULL << 42,
ARM_HWCAP_A64_SME_SBITPERM = 1ULL << 43,
ARM_HWCAP_A64_SME_AES = 1ULL << 44,
ARM_HWCAP_A64_SME_SFEXPA = 1ULL << 45,
ARM_HWCAP_A64_SME_STMOP = 1ULL << 46,
ARM_HWCAP_A64_SME_SMOP4 = 1ULL << 47,
ARM_HWCAP2_A64_DCPODP = 1 << 0,
ARM_HWCAP2_A64_SVE2 = 1 << 1,
ARM_HWCAP2_A64_SVEAES = 1 << 2,
ARM_HWCAP2_A64_SVEPMULL = 1 << 3,
ARM_HWCAP2_A64_SVEBITPERM = 1 << 4,
ARM_HWCAP2_A64_SVESHA3 = 1 << 5,
ARM_HWCAP2_A64_SVESM4 = 1 << 6,
ARM_HWCAP2_A64_FLAGM2 = 1 << 7,
ARM_HWCAP2_A64_FRINT = 1 << 8,
ARM_HWCAP2_A64_SVEI8MM = 1 << 9,
ARM_HWCAP2_A64_SVEF32MM = 1 << 10,
ARM_HWCAP2_A64_SVEF64MM = 1 << 11,
ARM_HWCAP2_A64_SVEBF16 = 1 << 12,
ARM_HWCAP2_A64_I8MM = 1 << 13,
ARM_HWCAP2_A64_BF16 = 1 << 14,
ARM_HWCAP2_A64_DGH = 1 << 15,
ARM_HWCAP2_A64_RNG = 1 << 16,
ARM_HWCAP2_A64_BTI = 1 << 17,
ARM_HWCAP2_A64_MTE = 1 << 18,
ARM_HWCAP2_A64_ECV = 1 << 19,
ARM_HWCAP2_A64_AFP = 1 << 20,
ARM_HWCAP2_A64_RPRES = 1 << 21,
ARM_HWCAP2_A64_MTE3 = 1 << 22,
ARM_HWCAP2_A64_SME = 1 << 23,
ARM_HWCAP2_A64_SME_I16I64 = 1 << 24,
ARM_HWCAP2_A64_SME_F64F64 = 1 << 25,
ARM_HWCAP2_A64_SME_I8I32 = 1 << 26,
ARM_HWCAP2_A64_SME_F16F32 = 1 << 27,
ARM_HWCAP2_A64_SME_B16F32 = 1 << 28,
ARM_HWCAP2_A64_SME_F32F32 = 1 << 29,
ARM_HWCAP2_A64_SME_FA64 = 1 << 30,
ARM_HWCAP2_A64_WFXT = 1ULL << 31,
ARM_HWCAP2_A64_EBF16 = 1ULL << 32,
ARM_HWCAP2_A64_SVE_EBF16 = 1ULL << 33,
ARM_HWCAP2_A64_CSSC = 1ULL << 34,
ARM_HWCAP2_A64_RPRFM = 1ULL << 35,
ARM_HWCAP2_A64_SVE2P1 = 1ULL << 36,
ARM_HWCAP2_A64_SME2 = 1ULL << 37,
ARM_HWCAP2_A64_SME2P1 = 1ULL << 38,
ARM_HWCAP2_A64_SME_I16I32 = 1ULL << 39,
ARM_HWCAP2_A64_SME_BI32I32 = 1ULL << 40,
ARM_HWCAP2_A64_SME_B16B16 = 1ULL << 41,
ARM_HWCAP2_A64_SME_F16F16 = 1ULL << 42,
ARM_HWCAP2_A64_MOPS = 1ULL << 43,
ARM_HWCAP2_A64_HBC = 1ULL << 44,
ARM_HWCAP2_A64_SVE_B16B16 = 1ULL << 45,
ARM_HWCAP2_A64_LRCPC3 = 1ULL << 46,
ARM_HWCAP2_A64_LSE128 = 1ULL << 47,
ARM_HWCAP2_A64_FPMR = 1ULL << 48,
ARM_HWCAP2_A64_LUT = 1ULL << 49,
ARM_HWCAP2_A64_FAMINMAX = 1ULL << 50,
ARM_HWCAP2_A64_F8CVT = 1ULL << 51,
ARM_HWCAP2_A64_F8FMA = 1ULL << 52,
ARM_HWCAP2_A64_F8DP4 = 1ULL << 53,
ARM_HWCAP2_A64_F8DP2 = 1ULL << 54,
ARM_HWCAP2_A64_F8E4M3 = 1ULL << 55,
ARM_HWCAP2_A64_F8E5M2 = 1ULL << 56,
ARM_HWCAP2_A64_SME_LUTV2 = 1ULL << 57,
ARM_HWCAP2_A64_SME_F8F16 = 1ULL << 58,
ARM_HWCAP2_A64_SME_F8F32 = 1ULL << 59,
ARM_HWCAP2_A64_SME_SF8FMA = 1ULL << 60,
ARM_HWCAP2_A64_SME_SF8DP4 = 1ULL << 61,
ARM_HWCAP2_A64_SME_SF8DP2 = 1ULL << 62,
ARM_HWCAP2_A64_POE = 1ULL << 63,
};
#define GET_FEATURE_ID(feat, hwcap) \
do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
abi_ulong get_elf_hwcap(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
abi_ulong hwcaps = 0;
hwcaps |= ARM_HWCAP_A64_FP;
hwcaps |= ARM_HWCAP_A64_ASIMD;
hwcaps |= ARM_HWCAP_A64_CPUID;
/* probe for the extra features */
GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES);
GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL);
GET_FEATURE_ID(aa64_sha1, ARM_HWCAP_A64_SHA1);
GET_FEATURE_ID(aa64_sha256, ARM_HWCAP_A64_SHA2);
GET_FEATURE_ID(aa64_sha512, ARM_HWCAP_A64_SHA512);
GET_FEATURE_ID(aa64_crc32, ARM_HWCAP_A64_CRC32);
GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3);
GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3);
GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4);
GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
GET_FEATURE_ID(aa64_atomics, ARM_HWCAP_A64_ATOMICS);
GET_FEATURE_ID(aa64_lse2, ARM_HWCAP_A64_USCAT);
GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM);
GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP);
GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
GET_FEATURE_ID(aa64_dit, ARM_HWCAP_A64_DIT);
GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP);
GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC);
GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC);
return hwcaps;
}
abi_ulong get_elf_hwcap2(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
abi_ulong hwcaps = 0;
GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP);
GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2);
GET_FEATURE_ID(aa64_sve2_aes, ARM_HWCAP2_A64_SVEAES);
GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL);
GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM);
GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3);
GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4);
GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2);
GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT);
GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM);
GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM);
GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM);
GET_FEATURE_ID(aa64_sve_bf16, ARM_HWCAP2_A64_SVEBF16);
GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM);
GET_FEATURE_ID(aa64_bf16, ARM_HWCAP2_A64_BF16);
GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG);
GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI);
GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE);
GET_FEATURE_ID(aa64_mte3, ARM_HWCAP2_A64_MTE3);
GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME |
ARM_HWCAP2_A64_SME_F32F32 |
ARM_HWCAP2_A64_SME_B16F32 |
ARM_HWCAP2_A64_SME_F16F32 |
ARM_HWCAP2_A64_SME_I8I32));
GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64);
GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64);
GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64);
GET_FEATURE_ID(aa64_hbc, ARM_HWCAP2_A64_HBC);
GET_FEATURE_ID(aa64_mops, ARM_HWCAP2_A64_MOPS);
GET_FEATURE_ID(aa64_sve2p1, ARM_HWCAP2_A64_SVE2P1);
GET_FEATURE_ID(aa64_sme2, (ARM_HWCAP2_A64_SME2 |
ARM_HWCAP2_A64_SME_I16I32 |
ARM_HWCAP2_A64_SME_BI32I32));
GET_FEATURE_ID(aa64_sme2p1, ARM_HWCAP2_A64_SME2P1);
GET_FEATURE_ID(aa64_sme_b16b16, ARM_HWCAP2_A64_SME_B16B16);
GET_FEATURE_ID(aa64_sme_f16f16, ARM_HWCAP2_A64_SME_F16F16);
GET_FEATURE_ID(aa64_sve_b16b16, ARM_HWCAP2_A64_SVE_B16B16);
return hwcaps;
}
const char *elf_hwcap_str(uint32_t bit)
{
static const char * const hwcap_str[] = {
[__builtin_ctz(ARM_HWCAP_A64_FP )] = "fp",
[__builtin_ctz(ARM_HWCAP_A64_ASIMD )] = "asimd",
[__builtin_ctz(ARM_HWCAP_A64_EVTSTRM )] = "evtstrm",
[__builtin_ctz(ARM_HWCAP_A64_AES )] = "aes",
[__builtin_ctz(ARM_HWCAP_A64_PMULL )] = "pmull",
[__builtin_ctz(ARM_HWCAP_A64_SHA1 )] = "sha1",
[__builtin_ctz(ARM_HWCAP_A64_SHA2 )] = "sha2",
[__builtin_ctz(ARM_HWCAP_A64_CRC32 )] = "crc32",
[__builtin_ctz(ARM_HWCAP_A64_ATOMICS )] = "atomics",
[__builtin_ctz(ARM_HWCAP_A64_FPHP )] = "fphp",
[__builtin_ctz(ARM_HWCAP_A64_ASIMDHP )] = "asimdhp",
[__builtin_ctz(ARM_HWCAP_A64_CPUID )] = "cpuid",
[__builtin_ctz(ARM_HWCAP_A64_ASIMDRDM)] = "asimdrdm",
[__builtin_ctz(ARM_HWCAP_A64_JSCVT )] = "jscvt",
[__builtin_ctz(ARM_HWCAP_A64_FCMA )] = "fcma",
[__builtin_ctz(ARM_HWCAP_A64_LRCPC )] = "lrcpc",
[__builtin_ctz(ARM_HWCAP_A64_DCPOP )] = "dcpop",
[__builtin_ctz(ARM_HWCAP_A64_SHA3 )] = "sha3",
[__builtin_ctz(ARM_HWCAP_A64_SM3 )] = "sm3",
[__builtin_ctz(ARM_HWCAP_A64_SM4 )] = "sm4",
[__builtin_ctz(ARM_HWCAP_A64_ASIMDDP )] = "asimddp",
[__builtin_ctz(ARM_HWCAP_A64_SHA512 )] = "sha512",
[__builtin_ctz(ARM_HWCAP_A64_SVE )] = "sve",
[__builtin_ctz(ARM_HWCAP_A64_ASIMDFHM)] = "asimdfhm",
[__builtin_ctz(ARM_HWCAP_A64_DIT )] = "dit",
[__builtin_ctz(ARM_HWCAP_A64_USCAT )] = "uscat",
[__builtin_ctz(ARM_HWCAP_A64_ILRCPC )] = "ilrcpc",
[__builtin_ctz(ARM_HWCAP_A64_FLAGM )] = "flagm",
[__builtin_ctz(ARM_HWCAP_A64_SSBS )] = "ssbs",
[__builtin_ctz(ARM_HWCAP_A64_SB )] = "sb",
[__builtin_ctz(ARM_HWCAP_A64_PACA )] = "paca",
[__builtin_ctz(ARM_HWCAP_A64_PACG )] = "pacg",
[__builtin_ctzll(ARM_HWCAP_A64_GCS )] = "gcs",
[__builtin_ctzll(ARM_HWCAP_A64_CMPBR )] = "cmpbr",
[__builtin_ctzll(ARM_HWCAP_A64_FPRCVT)] = "fprcvt",
[__builtin_ctzll(ARM_HWCAP_A64_F8MM8 )] = "f8mm8",
[__builtin_ctzll(ARM_HWCAP_A64_F8MM4 )] = "f8mm4",
[__builtin_ctzll(ARM_HWCAP_A64_SVE_F16MM)] = "svef16mm",
[__builtin_ctzll(ARM_HWCAP_A64_SVE_ELTPERM)] = "sveeltperm",
[__builtin_ctzll(ARM_HWCAP_A64_SVE_AES2)] = "sveaes2",
[__builtin_ctzll(ARM_HWCAP_A64_SVE_BFSCALE)] = "svebfscale",
[__builtin_ctzll(ARM_HWCAP_A64_SVE2P2)] = "sve2p2",
[__builtin_ctzll(ARM_HWCAP_A64_SME2P2)] = "sme2p2",
[__builtin_ctzll(ARM_HWCAP_A64_SME_SBITPERM)] = "smesbitperm",
[__builtin_ctzll(ARM_HWCAP_A64_SME_AES)] = "smeaes",
[__builtin_ctzll(ARM_HWCAP_A64_SME_SFEXPA)] = "smesfexpa",
[__builtin_ctzll(ARM_HWCAP_A64_SME_STMOP)] = "smestmop",
[__builtin_ctzll(ARM_HWCAP_A64_SME_SMOP4)] = "smesmop4",
};
return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
}
const char *elf_hwcap2_str(uint32_t bit)
{
static const char * const hwcap_str[] = {
[__builtin_ctz(ARM_HWCAP2_A64_DCPODP )] = "dcpodp",
[__builtin_ctz(ARM_HWCAP2_A64_SVE2 )] = "sve2",
[__builtin_ctz(ARM_HWCAP2_A64_SVEAES )] = "sveaes",
[__builtin_ctz(ARM_HWCAP2_A64_SVEPMULL )] = "svepmull",
[__builtin_ctz(ARM_HWCAP2_A64_SVEBITPERM )] = "svebitperm",
[__builtin_ctz(ARM_HWCAP2_A64_SVESHA3 )] = "svesha3",
[__builtin_ctz(ARM_HWCAP2_A64_SVESM4 )] = "svesm4",
[__builtin_ctz(ARM_HWCAP2_A64_FLAGM2 )] = "flagm2",
[__builtin_ctz(ARM_HWCAP2_A64_FRINT )] = "frint",
[__builtin_ctz(ARM_HWCAP2_A64_SVEI8MM )] = "svei8mm",
[__builtin_ctz(ARM_HWCAP2_A64_SVEF32MM )] = "svef32mm",
[__builtin_ctz(ARM_HWCAP2_A64_SVEF64MM )] = "svef64mm",
[__builtin_ctz(ARM_HWCAP2_A64_SVEBF16 )] = "svebf16",
[__builtin_ctz(ARM_HWCAP2_A64_I8MM )] = "i8mm",
[__builtin_ctz(ARM_HWCAP2_A64_BF16 )] = "bf16",
[__builtin_ctz(ARM_HWCAP2_A64_DGH )] = "dgh",
[__builtin_ctz(ARM_HWCAP2_A64_RNG )] = "rng",
[__builtin_ctz(ARM_HWCAP2_A64_BTI )] = "bti",
[__builtin_ctz(ARM_HWCAP2_A64_MTE )] = "mte",
[__builtin_ctz(ARM_HWCAP2_A64_ECV )] = "ecv",
[__builtin_ctz(ARM_HWCAP2_A64_AFP )] = "afp",
[__builtin_ctz(ARM_HWCAP2_A64_RPRES )] = "rpres",
[__builtin_ctz(ARM_HWCAP2_A64_MTE3 )] = "mte3",
[__builtin_ctz(ARM_HWCAP2_A64_SME )] = "sme",
[__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64 )] = "smei16i64",
[__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64 )] = "smef64f64",
[__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32 )] = "smei8i32",
[__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32 )] = "smef16f32",
[__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] = "smeb16f32",
[__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] = "smef32f32",
[__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] = "smefa64",
[__builtin_ctz(ARM_HWCAP2_A64_WFXT )] = "wfxt",
[__builtin_ctzll(ARM_HWCAP2_A64_EBF16 )] = "ebf16",
[__builtin_ctzll(ARM_HWCAP2_A64_SVE_EBF16 )] = "sveebf16",
[__builtin_ctzll(ARM_HWCAP2_A64_CSSC )] = "cssc",
[__builtin_ctzll(ARM_HWCAP2_A64_RPRFM )] = "rprfm",
[__builtin_ctzll(ARM_HWCAP2_A64_SVE2P1 )] = "sve2p1",
[__builtin_ctzll(ARM_HWCAP2_A64_SME2 )] = "sme2",
[__builtin_ctzll(ARM_HWCAP2_A64_SME2P1 )] = "sme2p1",
[__builtin_ctzll(ARM_HWCAP2_A64_SME_I16I32 )] = "smei16i32",
[__builtin_ctzll(ARM_HWCAP2_A64_SME_BI32I32)] = "smebi32i32",
[__builtin_ctzll(ARM_HWCAP2_A64_SME_B16B16 )] = "smeb16b16",
[__builtin_ctzll(ARM_HWCAP2_A64_SME_F16F16 )] = "smef16f16",
[__builtin_ctzll(ARM_HWCAP2_A64_MOPS )] = "mops",
[__builtin_ctzll(ARM_HWCAP2_A64_HBC )] = "hbc",
[__builtin_ctzll(ARM_HWCAP2_A64_SVE_B16B16 )] = "sveb16b16",
[__builtin_ctzll(ARM_HWCAP2_A64_LRCPC3 )] = "lrcpc3",
[__builtin_ctzll(ARM_HWCAP2_A64_LSE128 )] = "lse128",
[__builtin_ctzll(ARM_HWCAP2_A64_FPMR )] = "fpmr",
[__builtin_ctzll(ARM_HWCAP2_A64_LUT )] = "lut",
[__builtin_ctzll(ARM_HWCAP2_A64_FAMINMAX )] = "faminmax",
[__builtin_ctzll(ARM_HWCAP2_A64_F8CVT )] = "f8cvt",
[__builtin_ctzll(ARM_HWCAP2_A64_F8FMA )] = "f8fma",
[__builtin_ctzll(ARM_HWCAP2_A64_F8DP4 )] = "f8dp4",
[__builtin_ctzll(ARM_HWCAP2_A64_F8DP2 )] = "f8dp2",
[__builtin_ctzll(ARM_HWCAP2_A64_F8E4M3 )] = "f8e4m3",
[__builtin_ctzll(ARM_HWCAP2_A64_F8E5M2 )] = "f8e5m2",
[__builtin_ctzll(ARM_HWCAP2_A64_SME_LUTV2 )] = "smelutv2",
[__builtin_ctzll(ARM_HWCAP2_A64_SME_F8F16 )] = "smef8f16",
[__builtin_ctzll(ARM_HWCAP2_A64_SME_F8F32 )] = "smef8f32",
[__builtin_ctzll(ARM_HWCAP2_A64_SME_SF8DP4 )] = "smesf8dp4",
[__builtin_ctzll(ARM_HWCAP2_A64_SME_SF8DP2 )] = "smesf8dp2",
[__builtin_ctzll(ARM_HWCAP2_A64_POE )] = "poe",
};
return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
}
const char *get_elf_platform(CPUState *cs)
{
return TARGET_BIG_ENDIAN ? "aarch64_be" : "aarch64";
}
linux-user/aarch64/target_elf.h
+5 -4
View File
@@ -7,8 +7,9 @@
#ifndef AARCH64_TARGET_ELF_H
#define AARCH64_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
return "any";
}
#define HAVE_ELF_HWCAP 1
#define HAVE_ELF_HWCAP2 1
#define HAVE_ELF_PLATFORM 1
#endif
linux-user/alpha/cpu_loop.c
+4 -7
View File
@@ -173,13 +173,10 @@ void cpu_loop(CPUAlphaState *env)
}
}
void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs)
void init_main_thread(CPUState *cs, struct image_info *info)
{
int i;
CPUArchState *env = cpu_env(cs);
for(i = 0; i < 28; i++) {
env->ir[i] = ((abi_ulong *)regs)[i];
}
env->ir[IR_SP] = regs->usp;
env->pc = regs->pc;
env->pc = info->entry;
env->ir[IR_SP] = info->start_stack;
}
linux-user/alpha/elfload.c
+11
View File
@@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include "qemu/osdep.h"
#include "qemu.h"
#include "loader.h"
const char *get_elf_cpu_model(uint32_t eflags)
{
return "ev67";
}
linux-user/alpha/target_elf.h
+1 -4
View File
@@ -7,8 +7,5 @@
#ifndef ALPHA_TARGET_ELF_H
#define ALPHA_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
return "ev67";
}
#endif
linux-user/arm/cpu_loop.c
+50 -25
View File
@@ -480,32 +480,57 @@ void cpu_loop(CPUARMState *env)
}
}
void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs)
void init_main_thread(CPUState *cs, struct image_info *info)
{
CPUState *cpu = env_cpu(env);
TaskState *ts = get_task_state(cpu);
struct image_info *info = ts->info;
int i;
CPUARMState *env = cpu_env(cs);
abi_ptr stack = info->start_stack;
abi_ptr entry = info->entry;
cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
CPSRWriteByInstr);
for(i = 0; i < 16; i++) {
env->regs[i] = regs->uregs[i];
}
#if TARGET_BIG_ENDIAN
/* Enable BE8. */
if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
&& (info->elf_flags & EF_ARM_BE8)) {
env->uncached_cpsr |= CPSR_E;
env->cp15.sctlr_el[1] |= SCTLR_E0E;
} else {
env->cp15.sctlr_el[1] |= SCTLR_B;
}
arm_rebuild_hflags(env);
#endif
cpsr_write(env, ARM_CPU_MODE_USR | (entry & 1 ? CPSR_T : 0),
CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
ts->stack_base = info->start_stack;
ts->heap_base = info->brk;
/* This will be filled in on the first SYS_HEAPINFO call. */
ts->heap_limit = 0;
env->regs[15] = entry & 0xfffffffe;
env->regs[13] = stack;
/*
* Per the SVR4 ABI, r0 contains a pointer to a function to be
* registered with atexit. A value of 0 means we have no such handler.
*/
env->regs[0] = 0;
/* For uClinux PIC binaries. */
/* XXX: Linux does this only on ARM with no MMU (do we care?) */
env->regs[10] = info->start_data;
/* Support ARM FDPIC. */
if (info_is_fdpic(info)) {
/*
* As described in the ABI document, r7 points to the loadmap info
* prepared by the kernel. If an interpreter is needed, r8 points
* to the interpreter loadmap and r9 points to the interpreter
* PT_DYNAMIC info. If no interpreter is needed, r8 is zero, and
* r9 points to the main program PT_DYNAMIC info.
*/
env->regs[7] = info->loadmap_addr;
if (info->interpreter_loadmap_addr) {
/* Executable is dynamically loaded. */
env->regs[8] = info->interpreter_loadmap_addr;
env->regs[9] = info->interpreter_pt_dynamic_addr;
} else {
env->regs[8] = 0;
env->regs[9] = info->pt_dynamic_addr;
}
}
if (TARGET_BIG_ENDIAN) {
/* Enable BE8. */
if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
&& (info->elf_flags & EF_ARM_BE8)) {
env->uncached_cpsr |= CPSR_E;
env->cp15.sctlr_el[1] |= SCTLR_E0E;
} else {
env->cp15.sctlr_el[1] |= SCTLR_B;
}
arm_rebuild_hflags(env);
}
}
linux-user/arm/elfload.c
+201
View File
@@ -0,0 +1,201 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include "qemu/osdep.h"
#include "qemu.h"
#include "loader.h"
#include "target/arm/cpu-features.h"
const char *get_elf_cpu_model(uint32_t eflags)
{
return "any";
}
enum
{
ARM_HWCAP_ARM_SWP = 1 << 0,
ARM_HWCAP_ARM_HALF = 1 << 1,
ARM_HWCAP_ARM_THUMB = 1 << 2,
ARM_HWCAP_ARM_26BIT = 1 << 3,
ARM_HWCAP_ARM_FAST_MULT = 1 << 4,
ARM_HWCAP_ARM_FPA = 1 << 5,
ARM_HWCAP_ARM_VFP = 1 << 6,
ARM_HWCAP_ARM_EDSP = 1 << 7,
ARM_HWCAP_ARM_JAVA = 1 << 8,
ARM_HWCAP_ARM_IWMMXT = 1 << 9,
ARM_HWCAP_ARM_CRUNCH = 1 << 10,
ARM_HWCAP_ARM_THUMBEE = 1 << 11,
ARM_HWCAP_ARM_NEON = 1 << 12,
ARM_HWCAP_ARM_VFPv3 = 1 << 13,
ARM_HWCAP_ARM_VFPv3D16 = 1 << 14,
ARM_HWCAP_ARM_TLS = 1 << 15,
ARM_HWCAP_ARM_VFPv4 = 1 << 16,
ARM_HWCAP_ARM_IDIVA = 1 << 17,
ARM_HWCAP_ARM_IDIVT = 1 << 18,
ARM_HWCAP_ARM_VFPD32 = 1 << 19,
ARM_HWCAP_ARM_LPAE = 1 << 20,
ARM_HWCAP_ARM_EVTSTRM = 1 << 21,
ARM_HWCAP_ARM_FPHP = 1 << 22,
ARM_HWCAP_ARM_ASIMDHP = 1 << 23,
ARM_HWCAP_ARM_ASIMDDP = 1 << 24,
ARM_HWCAP_ARM_ASIMDFHM = 1 << 25,
ARM_HWCAP_ARM_ASIMDBF16 = 1 << 26,
ARM_HWCAP_ARM_I8MM = 1 << 27,
};
enum {
ARM_HWCAP2_ARM_AES = 1 << 0,
ARM_HWCAP2_ARM_PMULL = 1 << 1,
ARM_HWCAP2_ARM_SHA1 = 1 << 2,
ARM_HWCAP2_ARM_SHA2 = 1 << 3,
ARM_HWCAP2_ARM_CRC32 = 1 << 4,
ARM_HWCAP2_ARM_SB = 1 << 5,
ARM_HWCAP2_ARM_SSBS = 1 << 6,
};
abi_ulong get_elf_hwcap(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
abi_ulong hwcaps = 0;
hwcaps |= ARM_HWCAP_ARM_SWP;
hwcaps |= ARM_HWCAP_ARM_HALF;
hwcaps |= ARM_HWCAP_ARM_THUMB;
hwcaps |= ARM_HWCAP_ARM_FAST_MULT;
/* probe for the extra features */
#define GET_FEATURE(feat, hwcap) \
do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
#define GET_FEATURE_ID(feat, hwcap) \
do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
/* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */
GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA);
GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT);
GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP);
if (cpu_isar_feature(aa32_fpsp_v3, cpu) ||
cpu_isar_feature(aa32_fpdp_v3, cpu)) {
hwcaps |= ARM_HWCAP_ARM_VFPv3;
if (cpu_isar_feature(aa32_simd_r32, cpu)) {
hwcaps |= ARM_HWCAP_ARM_VFPD32;
} else {
hwcaps |= ARM_HWCAP_ARM_VFPv3D16;
}
}
GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);
/*
* MVFR1.FPHP and .SIMDHP must be in sync, and QEMU uses the same
* isar_feature function for both. The kernel reports them as two hwcaps.
*/
GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_FPHP);
GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_ASIMDHP);
GET_FEATURE_ID(aa32_dp, ARM_HWCAP_ARM_ASIMDDP);
GET_FEATURE_ID(aa32_fhm, ARM_HWCAP_ARM_ASIMDFHM);
GET_FEATURE_ID(aa32_bf16, ARM_HWCAP_ARM_ASIMDBF16);
GET_FEATURE_ID(aa32_i8mm, ARM_HWCAP_ARM_I8MM);
return hwcaps;
}
abi_ulong get_elf_hwcap2(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
abi_ulong hwcaps = 0;
GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES);
GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL);
GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1);
GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2);
GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32);
GET_FEATURE_ID(aa32_sb, ARM_HWCAP2_ARM_SB);
GET_FEATURE_ID(aa32_ssbs, ARM_HWCAP2_ARM_SSBS);
return hwcaps;
}
const char *elf_hwcap_str(uint32_t bit)
{
static const char *hwcap_str[] = {
[__builtin_ctz(ARM_HWCAP_ARM_SWP )] = "swp",
[__builtin_ctz(ARM_HWCAP_ARM_HALF )] = "half",
[__builtin_ctz(ARM_HWCAP_ARM_THUMB )] = "thumb",
[__builtin_ctz(ARM_HWCAP_ARM_26BIT )] = "26bit",
[__builtin_ctz(ARM_HWCAP_ARM_FAST_MULT)] = "fast_mult",
[__builtin_ctz(ARM_HWCAP_ARM_FPA )] = "fpa",
[__builtin_ctz(ARM_HWCAP_ARM_VFP )] = "vfp",
[__builtin_ctz(ARM_HWCAP_ARM_EDSP )] = "edsp",
[__builtin_ctz(ARM_HWCAP_ARM_JAVA )] = "java",
[__builtin_ctz(ARM_HWCAP_ARM_IWMMXT )] = "iwmmxt",
[__builtin_ctz(ARM_HWCAP_ARM_CRUNCH )] = "crunch",
[__builtin_ctz(ARM_HWCAP_ARM_THUMBEE )] = "thumbee",
[__builtin_ctz(ARM_HWCAP_ARM_NEON )] = "neon",
[__builtin_ctz(ARM_HWCAP_ARM_VFPv3 )] = "vfpv3",
[__builtin_ctz(ARM_HWCAP_ARM_VFPv3D16 )] = "vfpv3d16",
[__builtin_ctz(ARM_HWCAP_ARM_TLS )] = "tls",
[__builtin_ctz(ARM_HWCAP_ARM_VFPv4 )] = "vfpv4",
[__builtin_ctz(ARM_HWCAP_ARM_IDIVA )] = "idiva",
[__builtin_ctz(ARM_HWCAP_ARM_IDIVT )] = "idivt",
[__builtin_ctz(ARM_HWCAP_ARM_VFPD32 )] = "vfpd32",
[__builtin_ctz(ARM_HWCAP_ARM_LPAE )] = "lpae",
[__builtin_ctz(ARM_HWCAP_ARM_EVTSTRM )] = "evtstrm",
[__builtin_ctz(ARM_HWCAP_ARM_FPHP )] = "fphp",
[__builtin_ctz(ARM_HWCAP_ARM_ASIMDHP )] = "asimdhp",
[__builtin_ctz(ARM_HWCAP_ARM_ASIMDDP )] = "asimddp",
[__builtin_ctz(ARM_HWCAP_ARM_ASIMDFHM )] = "asimdfhm",
[__builtin_ctz(ARM_HWCAP_ARM_ASIMDBF16)] = "asimdbf16",
[__builtin_ctz(ARM_HWCAP_ARM_I8MM )] = "i8mm",
};
return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
}
const char *elf_hwcap2_str(uint32_t bit)
{
static const char *hwcap_str[] = {
[__builtin_ctz(ARM_HWCAP2_ARM_AES )] = "aes",
[__builtin_ctz(ARM_HWCAP2_ARM_PMULL)] = "pmull",
[__builtin_ctz(ARM_HWCAP2_ARM_SHA1 )] = "sha1",
[__builtin_ctz(ARM_HWCAP2_ARM_SHA2 )] = "sha2",
[__builtin_ctz(ARM_HWCAP2_ARM_CRC32)] = "crc32",
[__builtin_ctz(ARM_HWCAP2_ARM_SB )] = "sb",
[__builtin_ctz(ARM_HWCAP2_ARM_SSBS )] = "ssbs",
};
return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL;
}
const char *get_elf_platform(CPUState *cs)
{
CPUARMState *env = cpu_env(cs);
#if TARGET_BIG_ENDIAN
# define END "b"
#else
# define END "l"
#endif
if (arm_feature(env, ARM_FEATURE_V8)) {
return "v8" END;
} else if (arm_feature(env, ARM_FEATURE_V7)) {
if (arm_feature(env, ARM_FEATURE_M)) {
return "v7m" END;
} else {
return "v7" END;
}
} else if (arm_feature(env, ARM_FEATURE_V6)) {
return "v6" END;
} else if (arm_feature(env, ARM_FEATURE_V5)) {
return "v5" END;
} else {
return "v4" END;
}
#undef END
}
linux-user/arm/target_elf.h
+5 -4
View File
@@ -7,8 +7,9 @@
#ifndef ARM_TARGET_ELF_H
#define ARM_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
return "any";
}
#define HAVE_ELF_HWCAP 1
#define HAVE_ELF_HWCAP2 1
#define HAVE_ELF_PLATFORM 1
#endif
linux-user/arm/target_proc.h
+2 -2
View File
@@ -10,8 +10,8 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
{
ARMCPU *cpu = env_archcpu(cpu_env);
int arch, midr_rev, midr_part, midr_var, midr_impl;
target_ulong elf_hwcap = get_elf_hwcap();
target_ulong elf_hwcap2 = get_elf_hwcap2();
target_ulong elf_hwcap = get_elf_hwcap(env_cpu(cpu_env));
target_ulong elf_hwcap2 = get_elf_hwcap2(env_cpu(cpu_env));
const char *elf_name;
int num_cpus, len_part, len_var;
linux-user/elfload.c
+29 -1200
View File
File diff suppressed because it is too large Load Diff
linux-user/hexagon/cpu_loop.c
+5 -3
View File
@@ -79,9 +79,11 @@ void cpu_loop(CPUHexagonState *env)
}
}
void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs)
void init_main_thread(CPUState *cs, struct image_info *info)
{
env->gpr[HEX_REG_PC] = regs->sepc;
env->gpr[HEX_REG_SP] = regs->sp;
CPUArchState *env = cpu_env(cs);
env->gpr[HEX_REG_PC] = info->entry;
env->gpr[HEX_REG_SP] = info->start_stack;
env->gpr[HEX_REG_USR] = 0x56000;
}
linux-user/hexagon/elfload.c
+35
View File
@@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include "qemu/osdep.h"
#include "qemu.h"
#include "loader.h"
const char *get_elf_cpu_model(uint32_t eflags)
{
static char buf[32];
int err;
/* For now, treat anything newer than v5 as a v73 */
/* FIXME - Disable instructions that are newer than the specified arch */
if (eflags == 0x04 || /* v5 */
eflags == 0x05 || /* v55 */
eflags == 0x60 || /* v60 */
eflags == 0x61 || /* v61 */
eflags == 0x62 || /* v62 */
eflags == 0x65 || /* v65 */
eflags == 0x66 || /* v66 */
eflags == 0x67 || /* v67 */
eflags == 0x8067 || /* v67t */
eflags == 0x68 || /* v68 */
eflags == 0x69 || /* v69 */
eflags == 0x71 || /* v71 */
eflags == 0x8071 || /* v71t */
eflags == 0x73 /* v73 */
) {
return "v73";
}
err = snprintf(buf, sizeof(buf), "unknown (0x%x)", eflags);
return err >= 0 && err < sizeof(buf) ? buf : "unknown";
}
linux-user/hexagon/target_elf.h
-29
View File
@@ -18,33 +18,4 @@
#ifndef HEXAGON_TARGET_ELF_H
#define HEXAGON_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
static char buf[32];
int err;
/* For now, treat anything newer than v5 as a v73 */
/* FIXME - Disable instructions that are newer than the specified arch */
if (eflags == 0x04 || /* v5 */
eflags == 0x05 || /* v55 */
eflags == 0x60 || /* v60 */
eflags == 0x61 || /* v61 */
eflags == 0x62 || /* v62 */
eflags == 0x65 || /* v65 */
eflags == 0x66 || /* v66 */
eflags == 0x67 || /* v67 */
eflags == 0x8067 || /* v67t */
eflags == 0x68 || /* v68 */
eflags == 0x69 || /* v69 */
eflags == 0x71 || /* v71 */
eflags == 0x8071 || /* v71t */
eflags == 0x73 /* v73 */
) {
return "v73";
}
err = snprintf(buf, sizeof(buf), "unknown (0x%x)", eflags);
return err >= 0 && err < sizeof(buf) ? buf : "unknown";
}
#endif
linux-user/hppa/cpu_loop.c
+11 -7
View File
@@ -196,12 +196,16 @@ void cpu_loop(CPUHPPAState *env)
}
}
void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs)
void init_main_thread(CPUState *cs, struct image_info *info)
{
int i;
for (i = 1; i < 32; i++) {
env->gr[i] = regs->gr[i];
}
env->iaoq_f = regs->iaoq[0];
env->iaoq_b = regs->iaoq[1];
CPUArchState *env = cpu_env(cs);
env->iaoq_f = info->entry | PRIV_USER;
env->iaoq_b = env->iaoq_f + 4;
env->gr[23] = 0;
env->gr[24] = info->argv;
env->gr[25] = info->argc;
/* The top-of-stack contains a linkage buffer. */
env->gr[30] = info->start_stack + 64;
env->gr[31] = info->entry;
}
linux-user/hppa/elfload.c
+16
View File
@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include "qemu/osdep.h"
#include "qemu.h"
#include "loader.h"
const char *get_elf_cpu_model(uint32_t eflags)
{
return "hppa";
}
const char *get_elf_platform(CPUState *cs)
{
return "PARISC";
}
linux-user/hppa/target_elf.h
+3 -4
View File
@@ -7,8 +7,7 @@
#ifndef HPPA_TARGET_ELF_H
#define HPPA_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
return "hppa";
}
#define HAVE_ELF_PLATFORM 1
#endif

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