izzy/xemu
0
0
Fork 0
mirror of https://github.com/izzy2lost/xemu.git synced 2026-07-06 00:20:22 -07:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'pull-hex-20251017' of https://github.com/quic/qemu into staging

Browse Source 
Fixes for linux-user sigcontext save/restore, etc.

misc: avoid inconsistencies w/indent on macOS
fix hexagon linux-user sigcontext discrepancy, found by Alex @ Zig

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCgAdFiEEPWaq5HRZSCTIjOD4GlSvuOVkbDIFAmjyq24ACgkQGlSvuOVk
# bDIF9g/9FEllcwJFFOmyb+fsS0NkLFGRccCvowgjYCw5SaxC0+JBq58tWVkukCcK
# s+8eQ6TUfrgbxJziCoMWbP8UddMhNz9haUFGZ4wA8yq6Cxxmib092vdLj9YdfBdL
# TpMoXB1goWbPQ3EW2EyXr+Hsrlr/sb/hIrtSCvs2Xy1kRjc4xoAbHprgCz3C6oz4
# aiLJJy2uxWVDVEggWg7kSb2ZVmu/NrfReyv49kjEsuXiyHeQDBEDNYdRN5B6A9/F
# iznCSgTFBcDaV4UPaem6yEDuXCLucovmfLyvR+P6K/JtpOfX8nzWvk88j0WFeEmU
# kRZIpfR9un2GrndVeuxuoMGAZcha/LpajMr20OTfrKhJDPKp/kL5S3VqmBmZMsQx
# PjoBYFzBvg2FiMCQS1wQR4LGQ28/awz4ZnyeML02FRzDjmcFbZ0z5y4q1A9NnQEJ
# CZNnTjpUCdAVxymTnXCXVf/aS1T5v/iPWCu0BiebIlGP6/Eya364u60c0n/ABd1W
# bY3K1d2LZTYyi9dlT151pIOZ04S0k4E4g3jAyL578PfEpoJ7bXOmF8PL5DAAz1b8
# JRZjZLNXQlvNmcxTRs7wUzJlZ8AaudEZv5c+EnUcgLPcrBSMwvYdoXV7nyj+PKL1
# 3SwpRsgQimz7XtXAEUGmsSKUEIefF/yk/4laXHaGth3rMUDDi5U=
# =+ULY
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 17 Oct 2025 01:47:42 PM PDT
# gpg:                using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# gpg:                 aka "Brian Cain <bcain@kernel.org>" [unknown]
# gpg:                 aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown]
# gpg:                 aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown]
# gpg:                 aka "bcain" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF  49E0 175C 464E 541B 6D47
#      Subkey fingerprint: 3D66 AAE4 7459 4824 C88C  E0F8 1A54 AFB8 E564 6C32

* tag 'pull-hex-20251017' of https://github.com/quic/qemu:
  target/hexagon: Only indent on linux
  target/hexagon: Replace `prepare` script with meson target
  target/hexagon: s/pkt_has_store/pkt_has_scalar_store
  target/hexagon: handle .new values
  tests/tcg/hexagon: Add cs{0,1} coverage
  linux-user/hexagon: Use an array for GPRs
  linux-user/hexagon: use abi_ulong
  linux-user/hexagon: Fix sigcontext

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2025-10-17 14:04:47 -07:00
parent 18f6f30b00 f97700e075
commit c85ba2d7a4
14 changed files with 133 additions and 165 deletions
Download Patch File Download Diff File Expand all files Collapse all files
linux-user/hexagon/signal.c
+72 -112
View File
@@ -23,30 +23,32 @@
#include "signal-common.h"
#include "linux-user/trace.h"
struct target_sigcontext {
target_ulong r0, r1, r2, r3;
target_ulong r4, r5, r6, r7;
target_ulong r8, r9, r10, r11;
target_ulong r12, r13, r14, r15;
target_ulong r16, r17, r18, r19;
target_ulong r20, r21, r22, r23;
target_ulong r24, r25, r26, r27;
target_ulong r28, r29, r30, r31;
target_ulong sa0;
target_ulong lc0;
target_ulong sa1;
target_ulong lc1;
target_ulong m0;
target_ulong m1;
target_ulong usr;
target_ulong gp;
target_ulong ugp;
target_ulong pc;
target_ulong cause;
target_ulong badva;
target_ulong pred[NUM_PREGS];
struct target_user_regs_struct {
abi_ulong gpr[32];
abi_ulong sa0;
abi_ulong lc0;
abi_ulong sa1;
abi_ulong lc1;
abi_ulong m0;
abi_ulong m1;
abi_ulong usr;
abi_ulong p3_0;
abi_ulong gp;
abi_ulong ugp;
abi_ulong pc;
abi_ulong cause;
abi_ulong badva;
abi_ulong cs0;
abi_ulong cs1;
abi_ulong pad1; /* pad to 48 words */
};
QEMU_BUILD_BUG_ON(sizeof(struct target_user_regs_struct) != 48 * 4);
struct target_sigcontext {
struct target_user_regs_struct sc_regs;
} QEMU_ALIGNED(8);
struct target_ucontext {
unsigned long uc_flags;
target_ulong uc_link; /* target pointer */
@@ -76,53 +78,34 @@ static abi_ulong get_sigframe(struct target_sigaction *ka,
static void setup_sigcontext(struct target_sigcontext *sc, CPUHexagonState *env)
{
__put_user(env->gpr[HEX_REG_R00], &sc->r0);
__put_user(env->gpr[HEX_REG_R01], &sc->r1);
__put_user(env->gpr[HEX_REG_R02], &sc->r2);
__put_user(env->gpr[HEX_REG_R03], &sc->r3);
__put_user(env->gpr[HEX_REG_R04], &sc->r4);
__put_user(env->gpr[HEX_REG_R05], &sc->r5);
__put_user(env->gpr[HEX_REG_R06], &sc->r6);
__put_user(env->gpr[HEX_REG_R07], &sc->r7);
__put_user(env->gpr[HEX_REG_R08], &sc->r8);
__put_user(env->gpr[HEX_REG_R09], &sc->r9);
__put_user(env->gpr[HEX_REG_R10], &sc->r10);
__put_user(env->gpr[HEX_REG_R11], &sc->r11);
__put_user(env->gpr[HEX_REG_R12], &sc->r12);
__put_user(env->gpr[HEX_REG_R13], &sc->r13);
__put_user(env->gpr[HEX_REG_R14], &sc->r14);
__put_user(env->gpr[HEX_REG_R15], &sc->r15);
__put_user(env->gpr[HEX_REG_R16], &sc->r16);
__put_user(env->gpr[HEX_REG_R17], &sc->r17);
__put_user(env->gpr[HEX_REG_R18], &sc->r18);
__put_user(env->gpr[HEX_REG_R19], &sc->r19);
__put_user(env->gpr[HEX_REG_R20], &sc->r20);
__put_user(env->gpr[HEX_REG_R21], &sc->r21);
__put_user(env->gpr[HEX_REG_R22], &sc->r22);
__put_user(env->gpr[HEX_REG_R23], &sc->r23);
__put_user(env->gpr[HEX_REG_R24], &sc->r24);
__put_user(env->gpr[HEX_REG_R25], &sc->r25);
__put_user(env->gpr[HEX_REG_R26], &sc->r26);
__put_user(env->gpr[HEX_REG_R27], &sc->r27);
__put_user(env->gpr[HEX_REG_R28], &sc->r28);
__put_user(env->gpr[HEX_REG_R29], &sc->r29);
__put_user(env->gpr[HEX_REG_R30], &sc->r30);
__put_user(env->gpr[HEX_REG_R31], &sc->r31);
__put_user(env->gpr[HEX_REG_SA0], &sc->sa0);
__put_user(env->gpr[HEX_REG_LC0], &sc->lc0);
__put_user(env->gpr[HEX_REG_SA1], &sc->sa1);
__put_user(env->gpr[HEX_REG_LC1], &sc->lc1);
__put_user(env->gpr[HEX_REG_M0], &sc->m0);
__put_user(env->gpr[HEX_REG_M1], &sc->m1);
__put_user(env->gpr[HEX_REG_USR], &sc->usr);
__put_user(env->gpr[HEX_REG_GP], &sc->gp);
__put_user(env->gpr[HEX_REG_UGP], &sc->ugp);
__put_user(env->gpr[HEX_REG_PC], &sc->pc);
abi_ulong preds = 0;
int i;
for (i = 0; i < NUM_PREGS; i++) {
__put_user(env->pred[i], &(sc->pred[i]));
for (int i = 0; i < 32; i++) {
__put_user(env->gpr[HEX_REG_R00 + i], &sc->sc_regs.gpr[i]);
}
__put_user(env->gpr[HEX_REG_SA0], &sc->sc_regs.sa0);
__put_user(env->gpr[HEX_REG_LC0], &sc->sc_regs.lc0);
__put_user(env->gpr[HEX_REG_SA1], &sc->sc_regs.sa1);
__put_user(env->gpr[HEX_REG_LC1], &sc->sc_regs.lc1);
__put_user(env->gpr[HEX_REG_M0], &sc->sc_regs.m0);
__put_user(env->gpr[HEX_REG_M1], &sc->sc_regs.m1);
__put_user(env->gpr[HEX_REG_USR], &sc->sc_regs.usr);
__put_user(env->gpr[HEX_REG_GP], &sc->sc_regs.gp);
__put_user(env->gpr[HEX_REG_UGP], &sc->sc_regs.ugp);
__put_user(env->gpr[HEX_REG_PC], &sc->sc_regs.pc);
/* Consolidate predicates into p3_0 */
for (int i = 0; i < NUM_PREGS; i++) {
preds |= (env->pred[i] & 0xff) << (i * 8);
}
__put_user(preds, &sc->sc_regs.p3_0);
/* Set cause and badva to 0 - these are set by kernel on exceptions */
__put_user(0, &sc->sc_regs.cause);
__put_user(0, &sc->sc_regs.badva);
__put_user(env->gpr[HEX_REG_CS0], &sc->sc_regs.cs0);
__put_user(env->gpr[HEX_REG_CS1], &sc->sc_regs.cs1);
}
static void setup_ucontext(struct target_ucontext *uc,
@@ -192,53 +175,30 @@ badframe:
static void restore_sigcontext(CPUHexagonState *env,
struct target_sigcontext *sc)
{
__get_user(env->gpr[HEX_REG_R00], &sc->r0);
__get_user(env->gpr[HEX_REG_R01], &sc->r1);
__get_user(env->gpr[HEX_REG_R02], &sc->r2);
__get_user(env->gpr[HEX_REG_R03], &sc->r3);
__get_user(env->gpr[HEX_REG_R04], &sc->r4);
__get_user(env->gpr[HEX_REG_R05], &sc->r5);
__get_user(env->gpr[HEX_REG_R06], &sc->r6);
__get_user(env->gpr[HEX_REG_R07], &sc->r7);
__get_user(env->gpr[HEX_REG_R08], &sc->r8);
__get_user(env->gpr[HEX_REG_R09], &sc->r9);
__get_user(env->gpr[HEX_REG_R10], &sc->r10);
__get_user(env->gpr[HEX_REG_R11], &sc->r11);
__get_user(env->gpr[HEX_REG_R12], &sc->r12);
__get_user(env->gpr[HEX_REG_R13], &sc->r13);
__get_user(env->gpr[HEX_REG_R14], &sc->r14);
__get_user(env->gpr[HEX_REG_R15], &sc->r15);
__get_user(env->gpr[HEX_REG_R16], &sc->r16);
__get_user(env->gpr[HEX_REG_R17], &sc->r17);
__get_user(env->gpr[HEX_REG_R18], &sc->r18);
__get_user(env->gpr[HEX_REG_R19], &sc->r19);
__get_user(env->gpr[HEX_REG_R20], &sc->r20);
__get_user(env->gpr[HEX_REG_R21], &sc->r21);
__get_user(env->gpr[HEX_REG_R22], &sc->r22);
__get_user(env->gpr[HEX_REG_R23], &sc->r23);
__get_user(env->gpr[HEX_REG_R24], &sc->r24);
__get_user(env->gpr[HEX_REG_R25], &sc->r25);
__get_user(env->gpr[HEX_REG_R26], &sc->r26);
__get_user(env->gpr[HEX_REG_R27], &sc->r27);
__get_user(env->gpr[HEX_REG_R28], &sc->r28);
__get_user(env->gpr[HEX_REG_R29], &sc->r29);
__get_user(env->gpr[HEX_REG_R30], &sc->r30);
__get_user(env->gpr[HEX_REG_R31], &sc->r31);
__get_user(env->gpr[HEX_REG_SA0], &sc->sa0);
__get_user(env->gpr[HEX_REG_LC0], &sc->lc0);
__get_user(env->gpr[HEX_REG_SA1], &sc->sa1);
__get_user(env->gpr[HEX_REG_LC1], &sc->lc1);
__get_user(env->gpr[HEX_REG_M0], &sc->m0);
__get_user(env->gpr[HEX_REG_M1], &sc->m1);
__get_user(env->gpr[HEX_REG_USR], &sc->usr);
__get_user(env->gpr[HEX_REG_GP], &sc->gp);
__get_user(env->gpr[HEX_REG_UGP], &sc->ugp);
__get_user(env->gpr[HEX_REG_PC], &sc->pc);
abi_ulong preds;
int i;
for (i = 0; i < NUM_PREGS; i++) {
__get_user(env->pred[i], &(sc->pred[i]));
for (int i = 0; i < 32; i++) {
__get_user(env->gpr[HEX_REG_R00 + i], &sc->sc_regs.gpr[i]);
}
__get_user(env->gpr[HEX_REG_SA0], &sc->sc_regs.sa0);
__get_user(env->gpr[HEX_REG_LC0], &sc->sc_regs.lc0);
__get_user(env->gpr[HEX_REG_SA1], &sc->sc_regs.sa1);
__get_user(env->gpr[HEX_REG_LC1], &sc->sc_regs.lc1);
__get_user(env->gpr[HEX_REG_M0], &sc->sc_regs.m0);
__get_user(env->gpr[HEX_REG_M1], &sc->sc_regs.m1);
__get_user(env->gpr[HEX_REG_USR], &sc->sc_regs.usr);
__get_user(env->gpr[HEX_REG_GP], &sc->sc_regs.gp);
__get_user(env->gpr[HEX_REG_UGP], &sc->sc_regs.ugp);
__get_user(env->gpr[HEX_REG_PC], &sc->sc_regs.pc);
/* Restore predicates from p3_0 */
__get_user(preds, &sc->sc_regs.p3_0);
for (int i = 0; i < NUM_PREGS; i++) {
env->pred[i] = (preds >> (i * 8)) & 0xff;
}
__get_user(env->gpr[HEX_REG_CS0], &sc->sc_regs.cs0);
__get_user(env->gpr[HEX_REG_CS1], &sc->sc_regs.cs1);
}
static void restore_ucontext(CPUHexagonState *env, struct target_ucontext *uc)
target/hexagon/decode.c
+2 -2
View File
@@ -236,9 +236,9 @@ static void decode_set_insn_attr_fields(Packet *pkt)
if (GET_ATTRIB(opcode, A_SCALAR_STORE) &&
!GET_ATTRIB(opcode, A_MEMSIZE_0B)) {
if (pkt->insn[i].slot == 0) {
pkt->pkt_has_store_s0 = true;
pkt->pkt_has_scalar_store_s0 = true;
} else {
pkt->pkt_has_store_s1 = true;
pkt->pkt_has_scalar_store_s1 = true;
}
}
}
target/hexagon/gen_helper_funcs.py
+1 -1
View File
@@ -69,7 +69,7 @@ def gen_helper_function(f, tag, tagregs, tagimms):
if hex_common.need_slot(tag):
if "A_LOAD" in hex_common.attribdict[tag]:
f.write(hex_common.code_fmt(f"""\
bool pkt_has_store_s1 = slotval & 0x1;
bool pkt_has_scalar_store_s1 = slotval & 0x1;
"""))
f.write(hex_common.code_fmt(f"""\
uint32_t slot = slotval >> 1;
target/hexagon/genptr.c
+2 -1
View File
@@ -395,7 +395,8 @@ static inline void gen_store_conditional8(DisasContext *ctx,
#ifndef CONFIG_HEXAGON_IDEF_PARSER
static TCGv gen_slotval(DisasContext *ctx)
{
int slotval = (ctx->pkt->pkt_has_store_s1 & 1) | (ctx->insn->slot << 1);
int slotval =
(ctx->pkt->pkt_has_scalar_store_s1 & 1) | (ctx->insn->slot << 1);
return tcg_constant_tl(slotval);
}
#endif
target/hexagon/hex_common.py
+17 -5
View File
@@ -350,6 +350,7 @@ class Register:
f"{self.helper_arg_type()} {self.helper_arg_name()}"
)
#
# Every register is either Single or Pair or Hvx
#
@@ -1070,11 +1071,22 @@ def init_registers():
for reg in new_regs:
new_registers[f"{reg.regtype}{reg.regid}"] = reg
def get_register(tag, regtype, regid):
if f"{regtype}{regid}V" in semdict[tag]:
return registers[f"{regtype}{regid}"]
else:
return new_registers[f"{regtype}{regid}"]
def is_new_reg(tag, regid):
if regid[0] in "NO":
return True
return regid[0] == "P" and \
f"{regid}N" in semdict[tag] and \
f"{regid}V" not in semdict[tag]
def get_register(tag, regtype, regid, subtype=""):
regid = f"{regtype}{regid}"
is_new = is_new_reg(tag, regid)
try:
reg = new_registers[regid] if is_new else registers[regid]
except KeyError:
raise Exception(f"Unknown {'new ' if is_new else ''}register {regid}" +\
f"from '{tag}' with syntax '{semdict[tag]}'") from None
return reg
def helper_ret_type(tag, regs):
## If there is a scalar result, it is the return type
target/hexagon/idef-parser/README.rst
+1 -1
View File
@@ -637,7 +637,7 @@ tinycode for the Hexagon ``add`` instruction
::
---- 00021094
mov_i32 pkt_has_store_s1,$0x0
mov_i32 pkt_has_scalar_store_s1,$0x0
add_i32 tmp0,r2,r2
mov_i32 loc2,tmp0
mov_i32 new_r1,loc2
target/hexagon/idef-parser/parser-helpers.c
+2 -2
View File
@@ -1725,7 +1725,7 @@ void gen_cancel(Context *c, YYLTYPE *locp)
void gen_load_cancel(Context *c, YYLTYPE *locp)
{
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_scalar_store_s1) {\n");
OUT(c, locp, "ctx->s1_store_processed = false;\n");
OUT(c, locp, "process_store(ctx, 1);\n");
OUT(c, locp, "}\n");
@@ -1750,7 +1750,7 @@ void gen_load(Context *c, YYLTYPE *locp, HexValue *width,
/* Lookup the effective address EA */
find_variable(c, locp, ea, ea);
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_scalar_store_s1) {\n");
OUT(c, locp, "probe_noshuf_load(", ea, ", ", width, ", ctx->mem_idx);\n");
OUT(c, locp, "process_store(ctx, 1);\n");
OUT(c, locp, "}\n");
target/hexagon/idef-parser/prepare
-24
View File
@@ -1,24 +0,0 @@
#!/usr/bin/env bash
#
# Copyright(c) 2019-2021 rev.ng Labs Srl. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, see <http://www.gnu.org/licenses/>.
#
set -e
set -o pipefail
# Run the preprocessor and drop comments
cpp "$@"
target/hexagon/insn.h
+2 -2
View File
@@ -66,8 +66,8 @@ struct Packet {
bool pkt_has_dczeroa;
bool pkt_has_store_s0;
bool pkt_has_store_s1;
bool pkt_has_scalar_store_s0;
bool pkt_has_scalar_store_s1;
bool pkt_has_hvx;
Insn *vhist_insn;
target/hexagon/macros.h
+4 -4
View File
@@ -83,7 +83,7 @@
*/
#define CHECK_NOSHUF(VA, SIZE) \
do { \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
process_store(ctx, 1); \
} \
@@ -94,11 +94,11 @@
TCGLabel *noshuf_label = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \
GET_EA; \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
} \
gen_set_label(noshuf_label); \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
process_store(ctx, 1); \
} \
} while (0)
@@ -525,7 +525,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
do { \
check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \
check_noshuf(env, pkt_has_scalar_store_s1, slot, EA, SIZE, GETPC()); \
DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \
} while (0)
#endif
target/hexagon/meson.build
+3 -2
View File
@@ -280,12 +280,13 @@ if idef_parser_enabled and 'hexagon-linux-user' in target_dirs
command: [python, files('gen_idef_parser_funcs.py'), semantics_generated, '@OUTPUT@'],
)
compiler = meson.get_compiler('c').get_id()
preprocessed_idef_parser_input_generated = custom_target(
'idef_parser_input.preprocessed.h.inc',
output: 'idef_parser_input.preprocessed.h.inc',
input: idef_parser_input_generated,
depend_files: [idef_parser_dir / 'macros.h.inc'],
command: [idef_parser_dir / 'prepare', '@INPUT@', '-I' + idef_parser_dir, '-o', '@OUTPUT@'],
command: [compiler, '-x', 'c', '-E', '-I', idef_parser_dir, '-o', '@OUTPUT@', '@INPUT@'],
)
flex = generator(
@@ -323,7 +324,7 @@ if idef_parser_enabled and 'hexagon-linux-user' in target_dirs
)
indent = find_program('indent', required: false)
if indent.found()
if indent.found() and host_os == 'linux'
idef_generated_tcg_c = custom_target(
'indent',
input: idef_generated_tcg[0],
target/hexagon/op_helper.c
+2 -2
View File
@@ -463,11 +463,11 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
* If the load is in slot 0 and there is a store in slot1 (that
* wasn't cancelled), we have to do the store first.
*/
static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1,
static void check_noshuf(CPUHexagonState *env, bool pkt_has_scalar_store_s1,
uint32_t slot, target_ulong vaddr, int size,
uintptr_t ra)
{
if (slot == 0 && pkt_has_store_s1 &&
if (slot == 0 && pkt_has_scalar_store_s1 &&
((env->slot_cancelled & (1 << 1)) == 0)) {
probe_read(env, vaddr, size, MMU_USER_IDX, ra);
commit_store(env, 1, ra);
target/hexagon/translate.c
+5 -4
View File
@@ -693,11 +693,11 @@ static void process_store_log(DisasContext *ctx)
* the memory accesses overlap.
*/
Packet *pkt = ctx->pkt;
if (pkt->pkt_has_store_s1) {
if (pkt->pkt_has_scalar_store_s1) {
g_assert(!pkt->pkt_has_dczeroa);
process_store(ctx, 1);
}
if (pkt->pkt_has_store_s0) {
if (pkt->pkt_has_scalar_store_s0) {
g_assert(!pkt->pkt_has_dczeroa);
process_store(ctx, 0);
}
@@ -822,8 +822,9 @@ static void gen_commit_packet(DisasContext *ctx)
* involved in committing the packet.
*/
Packet *pkt = ctx->pkt;
bool has_store_s0 = pkt->pkt_has_store_s0;
bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed);
bool has_store_s0 = pkt->pkt_has_scalar_store_s0;
bool has_store_s1 =
(pkt->pkt_has_scalar_store_s1 && !ctx->s1_store_processed);
bool has_hvx_store = pkt_has_hvx_store(pkt);
if (pkt->pkt_has_dczeroa) {
/*
tests/tcg/hexagon/signal_context.c
+20 -3
View File
@@ -26,7 +26,11 @@ void sig_user(int sig, siginfo_t *info, void *puc)
"p1 = r7\n\t"
"p2 = r7\n\t"
"p3 = r7\n\t"
: : : "r7", "p0", "p1", "p2", "p3");
"r6 = #0x12345678\n\t"
"cs0 = r6\n\t"
"r6 = #0x87654321\n\t"
"cs1 = r6\n\t"
: : : "r6", "r7", "p0", "p1", "p2", "p3", "cs0", "cs1");
}
int main()
@@ -53,7 +57,11 @@ int main()
timer_settime(tid, 0, &it, NULL);
asm("loop0(1f, %1)\n\t"
"1: r8 = #0xff\n\t"
"1: r9 = #0xdeadbeef\n\t"
" cs0 = r9\n\t"
" r9 = #0xbadc0fee\n\t"
" cs1 = r9\n\t"
" r8 = #0xff\n\t"
" p0 = r8\n\t"
" p1 = r8\n\t"
" p2 = r8\n\t"
@@ -74,10 +82,19 @@ int main()
" r8 = p3\n\t"
" p0 = cmp.eq(r8, #0xff)\n\t"
" if (!p0) jump 2b\n\t"
" r8 = cs0\n\t"
" r9 = #0xdeadbeef\n\t"
" p0 = cmp.eq(r8, r9)\n\t"
" if (!p0) jump 2b\n\t"
" r8 = cs1\n\t"
" r9 = #0xbadc0fee\n\t"
" p0 = cmp.eq(r8, r9)\n\t"
" if (!p0) jump 2b\n\t"
"4: {}: endloop0\n\t"
:
: "r"(&err), "r"(i)
: "memory", "r8", "p0", "p1", "p2", "p3");
: "memory", "r8", "r9", "p0", "p1", "p2", "p3", "cs0", "cs1", "lc0",
"sa0");
puts(err ? "FAIL" : "PASS");
return err;