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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging

Browse Source 
pc,virtio,pci: fixes and updates

Most notably, this includes the TCO support for ICH: the last feature for 2.4
as we are entering the hard freeze.

Bugfixes only from now on.

virtio pci also gained cfg access capability - arguably a bugfix
since virtio spec makes it mandatory, but it's a big patch.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Wed Jul  8 10:40:07 2015 BST using RSA key ID D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"

* remotes/mst/tags/for_upstream:
  tco-test: fix up config accesses and re-enable
  virtio fix cfg endian-ness for BE targets
  virtio-pci: implement cfg capability
  virtio: define virtio_pci_cfg_cap in header.
  pcie: Set the "link active" in the link status register
  pci_regs.h: import from linux
  virtio_net: reuse constants from linux
  hw/i386/pc: don't carry FDC from pc_basic_device_init() to pc_cmos_init()
  hw/i386/pc: reflect any FDC @ ioport 0x3f0 in the CMOS
  hw/i386/pc: factor out pc_cmos_init_floppy()
  ich9: implement strap SPKR pin logic
  tests: add testcase for TCO watchdog emulation
  ich9: add TCO interface emulation
  acpi: split out ICH ACPI support
  Revert "dataplane: allow virtio-1 devices"
  dataplane: fix cross-endian issues

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2015-07-08 13:36:19 +01:00
parent 62a3864eb0 c4fc82bf1a
commit c8232b39bb
26 changed files with 1943 additions and 811 deletions
Download Patch File Download Diff File Expand all files Collapse all files
default-configs/i386-softmmu.mak
+1
View File
@@ -16,6 +16,7 @@ CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
CONFIG_ACPI_X86=y
CONFIG_ACPI_X86_ICH=y
CONFIG_ACPI_MEMORY_HOTPLUG=y
CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
default-configs/x86_64-softmmu.mak
+1
View File
@@ -17,6 +17,7 @@ CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
CONFIG_ACPI_X86=y
CONFIG_ACPI_X86_ICH=y
CONFIG_ACPI_MEMORY_HOTPLUG=y
CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
hw/acpi/Makefile.objs
+2 -1
View File
@@ -1,4 +1,5 @@
common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o ich9.o pcihp.o
common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o pcihp.o
common-obj-$(CONFIG_ACPI_X86_ICH) += ich9.o tco.o
common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
common-obj-$(CONFIG_ACPI) += acpi_interface.o
hw/acpi/ich9.c
+56 -1
View File
@@ -30,6 +30,7 @@
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/tco.h"
#include "sysemu/kvm.h"
#include "exec/address-spaces.h"
@@ -92,8 +93,16 @@ static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
unsigned width)
{
ICH9LPCPMRegs *pm = opaque;
TCOIORegs *tr = &pm->tco_regs;
uint64_t tco_en;
switch (addr) {
case 0:
tco_en = pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN;
/* once TCO_LOCK bit is set, TCO_EN bit cannot be overwritten */
if (tr->tco.cnt1 & TCO_LOCK) {
val = (val & ~ICH9_PMIO_SMI_EN_TCO_EN) | tco_en;
}
pm->smi_en &= ~pm->smi_en_wmask;
pm->smi_en |= (val & pm->smi_en_wmask);
break;
@@ -159,6 +168,25 @@ static const VMStateDescription vmstate_memhp_state = {
}
};
static bool vmstate_test_use_tco(void *opaque)
{
ICH9LPCPMRegs *s = opaque;
return s->enable_tco;
}
static const VMStateDescription vmstate_tco_io_state = {
.name = "ich9_pm/tco",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.needed = vmstate_test_use_tco,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts,
TCOIORegs),
VMSTATE_END_OF_LIST()
}
};
const VMStateDescription vmstate_ich9_pm = {
.name = "ich9_pm",
.version_id = 1,
@@ -179,6 +207,10 @@ const VMStateDescription vmstate_ich9_pm = {
.subsections = (const VMStateDescription*[]) {
&vmstate_memhp_state,
NULL
},
.subsections = (const VMStateDescription*[]) {
&vmstate_tco_io_state,
NULL
}
};
@@ -209,7 +241,8 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
acpi_pm1_evt_power_down(&pm->acpi_regs);
}
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, bool smm_enabled,
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
bool smm_enabled, bool enable_tco,
qemu_irq sci_irq)
{
memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
@@ -232,6 +265,12 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, bool smm_enabled,
memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
pm->smm_enabled = smm_enabled;
pm->enable_tco = enable_tco;
if (pm->enable_tco) {
acpi_pm_tco_init(&pm->tco_regs, &pm->io);
}
pm->irq = sci_irq;
qemu_register_reset(pm_reset, pm);
pm->powerdown_notifier.notify = pm_powerdown_req;
@@ -352,6 +391,18 @@ out:
error_propagate(errp, local_err);
}
static bool ich9_pm_get_enable_tco(Object *obj, Error **errp)
{
ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
return s->pm.enable_tco;
}
static void ich9_pm_set_enable_tco(Object *obj, bool value, Error **errp)
{
ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
s->pm.enable_tco = value;
}
void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
{
static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
@@ -383,6 +434,10 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
ich9_pm_get_s4_val,
ich9_pm_set_s4_val,
NULL, pm, NULL);
object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,
ich9_pm_get_enable_tco,
ich9_pm_set_enable_tco,
NULL);
}
void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, Error **errp)
hw/acpi/tco.c
+264
View File
@@ -0,0 +1,264 @@
/*
* QEMU ICH9 TCO emulation
*
* Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu-common.h"
#include "sysemu/watchdog.h"
#include "hw/i386/ich9.h"
#include "hw/acpi/tco.h"
//#define DEBUG
#ifdef DEBUG
#define TCO_DEBUG(fmt, ...) \
do { \
fprintf(stderr, "%s "fmt, __func__, ## __VA_ARGS__); \
} while (0)
#else
#define TCO_DEBUG(fmt, ...) do { } while (0)
#endif
enum {
TCO_RLD_DEFAULT = 0x0000,
TCO_DAT_IN_DEFAULT = 0x00,
TCO_DAT_OUT_DEFAULT = 0x00,
TCO1_STS_DEFAULT = 0x0000,
TCO2_STS_DEFAULT = 0x0000,
TCO1_CNT_DEFAULT = 0x0000,
TCO2_CNT_DEFAULT = 0x0008,
TCO_MESSAGE1_DEFAULT = 0x00,
TCO_MESSAGE2_DEFAULT = 0x00,
TCO_WDCNT_DEFAULT = 0x00,
TCO_TMR_DEFAULT = 0x0004,
SW_IRQ_GEN_DEFAULT = 0x03,
};
static inline void tco_timer_reload(TCOIORegs *tr)
{
tr->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
((int64_t)(tr->tco.tmr & TCO_TMR_MASK) * TCO_TICK_NSEC);
timer_mod(tr->tco_timer, tr->expire_time);
}
static inline void tco_timer_stop(TCOIORegs *tr)
{
tr->expire_time = -1;
}
static void tco_timer_expired(void *opaque)
{
TCOIORegs *tr = opaque;
ICH9LPCPMRegs *pm = container_of(tr, ICH9LPCPMRegs, tco_regs);
ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm);
uint32_t gcs = pci_get_long(lpc->chip_config + ICH9_CC_GCS);
tr->tco.rld = 0;
tr->tco.sts1 |= TCO_TIMEOUT;
if (++tr->timeouts_no == 2) {
tr->tco.sts2 |= TCO_SECOND_TO_STS;
tr->tco.sts2 |= TCO_BOOT_STS;
tr->timeouts_no = 0;
if (!lpc->pin_strap.spkr_hi && !(gcs & ICH9_CC_GCS_NO_REBOOT)) {
watchdog_perform_action();
tco_timer_stop(tr);
return;
}
}
if (pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN) {
ich9_generate_smi();
} else {
ich9_generate_nmi();
}
tr->tco.rld = tr->tco.tmr;
tco_timer_reload(tr);
}
/* NOTE: values of 0 or 1 will be ignored by ICH */
static inline int can_start_tco_timer(TCOIORegs *tr)
{
return !(tr->tco.cnt1 & TCO_TMR_HLT) && tr->tco.tmr > 1;
}
static uint32_t tco_ioport_readw(TCOIORegs *tr, uint32_t addr)
{
uint16_t rld;
switch (addr) {
case TCO_RLD:
if (tr->expire_time != -1) {
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int64_t elapsed = (tr->expire_time - now) / TCO_TICK_NSEC;
rld = (uint16_t)elapsed | (tr->tco.rld & ~TCO_RLD_MASK);
} else {
rld = tr->tco.rld;
}
return rld;
case TCO_DAT_IN:
return tr->tco.din;
case TCO_DAT_OUT:
return tr->tco.dout;
case TCO1_STS:
return tr->tco.sts1;
case TCO2_STS:
return tr->tco.sts2;
case TCO1_CNT:
return tr->tco.cnt1;
case TCO2_CNT:
return tr->tco.cnt2;
case TCO_MESSAGE1:
return tr->tco.msg1;
case TCO_MESSAGE2:
return tr->tco.msg2;
case TCO_WDCNT:
return tr->tco.wdcnt;
case TCO_TMR:
return tr->tco.tmr;
case SW_IRQ_GEN:
return tr->sw_irq_gen;
}
return 0;
}
static void tco_ioport_writew(TCOIORegs *tr, uint32_t addr, uint32_t val)
{
switch (addr) {
case TCO_RLD:
tr->timeouts_no = 0;
if (can_start_tco_timer(tr)) {
tr->tco.rld = tr->tco.tmr;
tco_timer_reload(tr);
} else {
tr->tco.rld = val;
}
break;
case TCO_DAT_IN:
tr->tco.din = val;
tr->tco.sts1 |= SW_TCO_SMI;
ich9_generate_smi();
break;
case TCO_DAT_OUT:
tr->tco.dout = val;
tr->tco.sts1 |= TCO_INT_STS;
/* TODO: cause an interrupt, as selected by the TCO_INT_SEL bits */
break;
case TCO1_STS:
tr->tco.sts1 = val & TCO1_STS_MASK;
break;
case TCO2_STS:
tr->tco.sts2 = val & TCO2_STS_MASK;
break;
case TCO1_CNT:
val &= TCO1_CNT_MASK;
/*
* once TCO_LOCK bit is set, it can not be cleared by software. a reset
* is required to change this bit from 1 to 0 -- it defaults to 0.
*/
tr->tco.cnt1 = val | (tr->tco.cnt1 & TCO_LOCK);
if (can_start_tco_timer(tr)) {
tr->tco.rld = tr->tco.tmr;
tco_timer_reload(tr);
} else {
tco_timer_stop(tr);
}
break;
case TCO2_CNT:
tr->tco.cnt2 = val;
break;
case TCO_MESSAGE1:
tr->tco.msg1 = val;
break;
case TCO_MESSAGE2:
tr->tco.msg2 = val;
break;
case TCO_WDCNT:
tr->tco.wdcnt = val;
break;
case TCO_TMR:
tr->tco.tmr = val;
break;
case SW_IRQ_GEN:
tr->sw_irq_gen = val;
break;
}
}
static uint64_t tco_io_readw(void *opaque, hwaddr addr, unsigned width)
{
TCOIORegs *tr = opaque;
return tco_ioport_readw(tr, addr);
}
static void tco_io_writew(void *opaque, hwaddr addr, uint64_t val,
unsigned width)
{
TCOIORegs *tr = opaque;
tco_ioport_writew(tr, addr, val);
}
static const MemoryRegionOps tco_io_ops = {
.read = tco_io_readw,
.write = tco_io_writew,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.impl.min_access_size = 1,
.impl.max_access_size = 2,
.endianness = DEVICE_LITTLE_ENDIAN,
};
void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent)
{
*tr = (TCOIORegs) {
.tco = {
.rld = TCO_RLD_DEFAULT,
.din = TCO_DAT_IN_DEFAULT,
.dout = TCO_DAT_OUT_DEFAULT,
.sts1 = TCO1_STS_DEFAULT,
.sts2 = TCO2_STS_DEFAULT,
.cnt1 = TCO1_CNT_DEFAULT,
.cnt2 = TCO2_CNT_DEFAULT,
.msg1 = TCO_MESSAGE1_DEFAULT,
.msg2 = TCO_MESSAGE2_DEFAULT,
.wdcnt = TCO_WDCNT_DEFAULT,
.tmr = TCO_TMR_DEFAULT,
},
.sw_irq_gen = SW_IRQ_GEN_DEFAULT,
.tco_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tco_timer_expired, tr),
.expire_time = -1,
.timeouts_no = 0,
};
memory_region_init_io(&tr->io, memory_region_owner(parent),
&tco_io_ops, tr, "sm-tco", ICH9_PMIO_TCO_LEN);
memory_region_add_subregion(parent, ICH9_PMIO_TCO_RLD, &tr->io);
}
const VMStateDescription vmstate_tco_io_sts = {
.name = "tco io device status",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT16(tco.rld, TCOIORegs),
VMSTATE_UINT8(tco.din, TCOIORegs),
VMSTATE_UINT8(tco.dout, TCOIORegs),
VMSTATE_UINT16(tco.sts1, TCOIORegs),
VMSTATE_UINT16(tco.sts2, TCOIORegs),
VMSTATE_UINT16(tco.cnt1, TCOIORegs),
VMSTATE_UINT16(tco.cnt2, TCOIORegs),
VMSTATE_UINT8(tco.msg1, TCOIORegs),
VMSTATE_UINT8(tco.msg2, TCOIORegs),
VMSTATE_UINT8(tco.wdcnt, TCOIORegs),
VMSTATE_UINT16(tco.tmr, TCOIORegs),
VMSTATE_UINT8(sw_irq_gen, TCOIORegs),
VMSTATE_TIMER_PTR(tco_timer, TCOIORegs),
VMSTATE_INT64(expire_time, TCOIORegs),
VMSTATE_UINT8(timeouts_no, TCOIORegs),
VMSTATE_END_OF_LIST()
}
};
hw/i386/pc.c
+96 -33
View File
@@ -293,11 +293,82 @@ static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
set_boot_dev(opaque, boot_device, errp);
}
static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
{
int val, nb, i;
FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
/* floppy type */
if (floppy) {
for (i = 0; i < 2; i++) {
fd_type[i] = isa_fdc_get_drive_type(floppy, i);
}
}
val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
cmos_get_fd_drive_type(fd_type[1]);
rtc_set_memory(rtc_state, 0x10, val);
val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
nb = 0;
if (fd_type[0] < FDRIVE_DRV_NONE) {
nb++;
}
if (fd_type[1] < FDRIVE_DRV_NONE) {
nb++;
}
switch (nb) {
case 0:
break;
case 1:
val |= 0x01; /* 1 drive, ready for boot */
break;
case 2:
val |= 0x41; /* 2 drives, ready for boot */
break;
}
rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
}
typedef struct pc_cmos_init_late_arg {
ISADevice *rtc_state;
BusState *idebus[2];
} pc_cmos_init_late_arg;
typedef struct check_fdc_state {
ISADevice *floppy;
bool multiple;
} CheckFdcState;
static int check_fdc(Object *obj, void *opaque)
{
CheckFdcState *state = opaque;
Object *fdc;
uint32_t iobase;
Error *local_err = NULL;
fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
if (!fdc) {
return 0;
}
iobase = object_property_get_int(obj, "iobase", &local_err);
if (local_err || iobase != 0x3f0) {
error_free(local_err);
return 0;
}
if (state->floppy) {
state->multiple = true;
} else {
state->floppy = ISA_DEVICE(obj);
}
return 0;
}
static const char * const fdc_container_path[] = {
"/unattached", "/peripheral", "/peripheral-anon"
};
static void pc_cmos_init_late(void *opaque)
{
pc_cmos_init_late_arg *arg = opaque;
@@ -306,6 +377,8 @@ static void pc_cmos_init_late(void *opaque)
int8_t heads, sectors;
int val;
int i, trans;
Object *container;
CheckFdcState state = { 0 };
val = 0;
if (ide_get_geometry(arg->idebus[0], 0,
@@ -335,16 +408,32 @@ static void pc_cmos_init_late(void *opaque)
}
rtc_set_memory(s, 0x39, val);
/*
* Locate the FDC at IO address 0x3f0, and configure the CMOS registers
* accordingly.
*/
for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
container = container_get(qdev_get_machine(), fdc_container_path[i]);
object_child_foreach(container, check_fdc, &state);
}
if (state.multiple) {
error_report("warning: multiple floppy disk controllers with "
"iobase=0x3f0 have been found;\n"
"the one being picked for CMOS setup might not reflect "
"your intent");
}
pc_cmos_init_floppy(s, state.floppy);
qemu_unregister_reset(pc_cmos_init_late, opaque);
}
void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
const char *boot_device, MachineState *machine,
ISADevice *floppy, BusState *idebus0, BusState *idebus1,
BusState *idebus0, BusState *idebus1,
ISADevice *s)
{
int val, nb, i;
FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
int val;
static pc_cmos_init_late_arg arg;
PCMachineState *pc_machine = PC_MACHINE(machine);
Error *local_err = NULL;
@@ -401,39 +490,12 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
exit(1);
}
/* floppy type */
if (floppy) {
for (i = 0; i < 2; i++) {
fd_type[i] = isa_fdc_get_drive_type(floppy, i);
}
}
val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
cmos_get_fd_drive_type(fd_type[1]);
rtc_set_memory(s, 0x10, val);
val = 0;
nb = 0;
if (fd_type[0] < FDRIVE_DRV_NONE) {
nb++;
}
if (fd_type[1] < FDRIVE_DRV_NONE) {
nb++;
}
switch (nb) {
case 0:
break;
case 1:
val |= 0x01; /* 1 drive, ready for boot */
break;
case 2:
val |= 0x41; /* 2 drives, ready for boot */
break;
}
val |= 0x02; /* FPU is there */
val |= 0x04; /* PS/2 mouse installed */
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
/* hard drives */
/* hard drives and FDC */
arg.rtc_state = s;
arg.idebus[0] = idebus0;
arg.idebus[1] = idebus1;
@@ -1401,7 +1463,6 @@ static const MemoryRegionOps ioportF0_io_ops = {
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
ISADevice **rtc_state,
bool create_fdctrl,
ISADevice **floppy,
bool no_vmport,
uint32 hpet_irqs)
{
@@ -1497,7 +1558,9 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
fd[i] = drive_get(IF_FLOPPY, 0, i);
create_fdctrl |= !!fd[i];
}
*floppy = create_fdctrl ? fdctrl_init_isa(isa_bus, fd) : NULL;
if (create_fdctrl) {
fdctrl_init_isa(isa_bus, fd);
}
}
void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
hw/i386/pc_piix.c
+2 -3
View File
@@ -94,7 +94,6 @@ static void pc_init1(MachineState *machine)
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
ISADevice *floppy;
MemoryRegion *ram_memory;
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
@@ -241,7 +240,7 @@ static void pc_init1(MachineState *machine)
}
/* init basic PC hardware */
pc_basic_device_init(isa_bus, gsi, &rtc_state, true, &floppy,
pc_basic_device_init(isa_bus, gsi, &rtc_state, true,
(pc_machine->vmport != ON_OFF_AUTO_ON), 0x4);
pc_nic_init(isa_bus, pci_bus);
@@ -273,7 +272,7 @@ static void pc_init1(MachineState *machine)
}
pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order,
machine, floppy, idebus[0], idebus[1], rtc_state);
machine, idebus[0], idebus[1], rtc_state);
if (pci_enabled && usb_enabled()) {
pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci");
hw/i386/pc_q35.c
+5 -4
View File
@@ -73,7 +73,6 @@ static void pc_q35_init(MachineState *machine)
PCIDevice *lpc;
BusState *idebus[MAX_SATA_PORTS];
ISADevice *rtc_state;
ISADevice *floppy;
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
MemoryRegion *ram_memory;
@@ -249,11 +248,11 @@ static void pc_q35_init(MachineState *machine)
}
/* init basic PC hardware */
pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy, &floppy,
pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy,
(pc_machine->vmport != ON_OFF_AUTO_ON), 0xff0104);
/* connect pm stuff to lpc */
ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pc_machine));
ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pc_machine), !mc->no_tco);
/* ahci and SATA device, for q35 1 ahci controller is built-in */
ahci = pci_create_simple_multifunction(host_bus,
@@ -278,7 +277,7 @@ static void pc_q35_init(MachineState *machine)
8, NULL, 0);
pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order,
machine, floppy, idebus[0], idebus[1], rtc_state);
machine, idebus[0], idebus[1], rtc_state);
/* the rest devices to which pci devfn is automatically assigned */
pc_vga_init(isa_bus, host_bus);
@@ -399,6 +398,7 @@ static void pc_q35_2_4_machine_options(MachineClass *m)
m->default_machine_opts = "firmware=bios-256k.bin";
m->default_display = "std";
m->no_floppy = 1;
m->no_tco = 0;
m->alias = "q35";
}
@@ -410,6 +410,7 @@ static void pc_q35_2_3_machine_options(MachineClass *m)
{
pc_q35_2_4_machine_options(m);
m->no_floppy = 0;
m->no_tco = 1;
m->alias = NULL;
SET_MACHINE_COMPAT(m, PC_COMPAT_2_3);
}
hw/isa/lpc_ich9.c
+19 -2
View File
@@ -138,6 +138,7 @@ static void ich9_cc_reset(ICH9LPCState *lpc)
pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
ich9_cc_update(lpc);
}
@@ -313,6 +314,16 @@ PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
return route;
}
void ich9_generate_smi(void)
{
cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
}
void ich9_generate_nmi(void)
{
cpu_interrupt(first_cpu, CPU_INTERRUPT_NMI);
}
static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
{
switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
@@ -357,13 +368,13 @@ static void ich9_set_sci(void *opaque, int irq_num, int level)
}
}
void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled, bool enable_tco)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
qemu_irq sci_irq;
sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, enable_tco, sci_irq);
ich9_lpc_reset(&lpc->d.qdev);
}
@@ -681,6 +692,11 @@ static const VMStateDescription vmstate_ich9_lpc = {
}
};
static Property ich9_lpc_properties[] = {
DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true),
DEFINE_PROP_END_OF_LIST(),
};
static void ich9_lpc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -692,6 +708,7 @@ static void ich9_lpc_class_init(ObjectClass *klass, void *data)
dc->reset = ich9_lpc_reset;
k->init = ich9_lpc_init;
dc->vmsd = &vmstate_ich9_lpc;
dc->props = ich9_lpc_properties;
k->config_write = ich9_lpc_config_write;
dc->desc = "ICH9 LPC bridge";
k->vendor_id = PCI_VENDOR_ID_INTEL;
hw/pci/pcie.c
+1 -1
View File
@@ -78,7 +78,7 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
PCI_EXP_LNK_LS_25);
pci_set_word(exp_cap + PCI_EXP_LNKSTA,
PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25 |PCI_EXP_LNKSTA_DLLLA);
pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
hw/virtio/dataplane/vring.c
+25 -28
View File
@@ -153,22 +153,20 @@ bool vring_should_notify(VirtIODevice *vdev, Vring *vring)
return true;
}
return vring_need_event(vring_used_event(&vring->vr), new, old);
return vring_need_event(virtio_tswap16(vdev, vring_used_event(&vring->vr)),
new, old);
}
static int get_desc(VirtIODevice *vdev, Vring *vring, VirtQueueElement *elem,
static int get_desc(Vring *vring, VirtQueueElement *elem,
struct vring_desc *desc)
{
unsigned *num;
struct iovec *iov;
hwaddr *addr;
MemoryRegion *mr;
int is_write = virtio_tswap16(vdev, desc->flags) & VRING_DESC_F_WRITE;
uint32_t len = virtio_tswap32(vdev, desc->len);
uint64_t desc_addr = virtio_tswap64(vdev, desc->addr);
if (is_write) {
if (desc->flags & VRING_DESC_F_WRITE) {
num = &elem->in_num;
iov = &elem->in_sg[*num];
addr = &elem->in_addr[*num];
@@ -192,17 +190,18 @@ static int get_desc(VirtIODevice *vdev, Vring *vring, VirtQueueElement *elem,
}
/* TODO handle non-contiguous memory across region boundaries */
iov->iov_base = vring_map(&mr, desc_addr, len, is_write);
iov->iov_base = vring_map(&mr, desc->addr, desc->len,
desc->flags & VRING_DESC_F_WRITE);
if (!iov->iov_base) {
error_report("Failed to map descriptor addr %#" PRIx64 " len %u",
(uint64_t)desc_addr, len);
(uint64_t)desc->addr, desc->len);
return -EFAULT;
}
/* The MemoryRegion is looked up again and unref'ed later, leave the
* ref in place. */
iov->iov_len = len;
*addr = desc_addr;
iov->iov_len = desc->len;
*addr = desc->addr;
*num += 1;
return 0;
}
@@ -224,23 +223,21 @@ static int get_indirect(VirtIODevice *vdev, Vring *vring,
struct vring_desc desc;
unsigned int i = 0, count, found = 0;
int ret;
uint32_t len = virtio_tswap32(vdev, indirect->len);
uint64_t addr = virtio_tswap64(vdev, indirect->addr);
/* Sanity check */
if (unlikely(len % sizeof(desc))) {
if (unlikely(indirect->len % sizeof(desc))) {
error_report("Invalid length in indirect descriptor: "
"len %#x not multiple of %#zx",
len, sizeof(desc));
indirect->len, sizeof(desc));
vring->broken = true;
return -EFAULT;
}
count = len / sizeof(desc);
count = indirect->len / sizeof(desc);
/* Buffers are chained via a 16 bit next field, so
* we can have at most 2^16 of these. */
if (unlikely(count > USHRT_MAX + 1)) {
error_report("Indirect buffer length too big: %d", len);
error_report("Indirect buffer length too big: %d", indirect->len);
vring->broken = true;
return -EFAULT;
}
@@ -251,12 +248,12 @@ static int get_indirect(VirtIODevice *vdev, Vring *vring,
/* Translate indirect descriptor */
desc_ptr = vring_map(&mr,
addr + found * sizeof(desc),
indirect->addr + found * sizeof(desc),
sizeof(desc), false);
if (!desc_ptr) {
error_report("Failed to map indirect descriptor "
"addr %#" PRIx64 " len %zu",
(uint64_t)addr + found * sizeof(desc),
(uint64_t)indirect->addr + found * sizeof(desc),
sizeof(desc));
vring->broken = true;
return -EFAULT;
@@ -274,20 +271,19 @@ static int get_indirect(VirtIODevice *vdev, Vring *vring,
return -EFAULT;
}
if (unlikely(virtio_tswap16(vdev, desc.flags)
& VRING_DESC_F_INDIRECT)) {
if (unlikely(desc.flags & VRING_DESC_F_INDIRECT)) {
error_report("Nested indirect descriptor");
vring->broken = true;
return -EFAULT;
}
ret = get_desc(vdev, vring, elem, &desc);
ret = get_desc(vring, elem, &desc);
if (ret < 0) {
vring->broken |= (ret == -EFAULT);
return ret;
}
i = virtio_tswap16(vdev, desc.next);
} while (virtio_tswap16(vdev, desc.flags) & VRING_DESC_F_NEXT);
i = desc.next;
} while (desc.flags & VRING_DESC_F_NEXT);
return 0;
}
@@ -388,7 +384,7 @@ int vring_pop(VirtIODevice *vdev, Vring *vring,
/* Ensure descriptor is loaded before accessing fields */
barrier();
if (virtio_tswap16(vdev, desc.flags) & VRING_DESC_F_INDIRECT) {
if (desc.flags & VRING_DESC_F_INDIRECT) {
ret = get_indirect(vdev, vring, elem, &desc);
if (ret < 0) {
goto out;
@@ -396,18 +392,19 @@ int vring_pop(VirtIODevice *vdev, Vring *vring,
continue;
}
ret = get_desc(vdev, vring, elem, &desc);
ret = get_desc(vring, elem, &desc);
if (ret < 0) {
goto out;
}
i = virtio_tswap16(vdev, desc.next);
} while (virtio_tswap16(vdev, desc.flags) & VRING_DESC_F_NEXT);
i = desc.next;
} while (desc.flags & VRING_DESC_F_NEXT);
/* On success, increment avail index. */
vring->last_avail_idx++;
if (virtio_has_feature(vdev, VIRTIO_RING_F_EVENT_IDX)) {
vring_avail_event(&vring->vr) = vring->last_avail_idx;
vring_avail_event(&vring->vr) =
virtio_tswap16(vdev, vring->last_avail_idx);
}
return head;
hw/virtio/virtio-pci.c
+150 -1
View File
@@ -443,11 +443,89 @@ static const MemoryRegionOps virtio_pci_config_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
/* Below are generic functions to do memcpy from/to an address space,
* without byteswaps, with input validation.
*
* As regular address_space_* APIs all do some kind of byteswap at least for
* some host/target combinations, we are forced to explicitly convert to a
* known-endianness integer value.
* It doesn't really matter which endian format to go through, so the code
* below selects the endian that causes the least amount of work on the given
* host.
*
* Note: host pointer must be aligned.
*/
static
void virtio_address_space_write(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
uint32_t val;
/* address_space_* APIs assume an aligned address.
* As address is under guest control, handle illegal values.
*/
addr &= ~(len - 1);
/* Make sure caller aligned buf properly */
assert(!(((uintptr_t)buf) & (len - 1)));
switch (len) {
case 1:
val = pci_get_byte(buf);
address_space_stb(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
break;
case 2:
val = pci_get_word(buf);
address_space_stw_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
break;
case 4:
val = pci_get_long(buf);
address_space_stl_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
break;
default:
/* As length is under guest control, handle illegal values. */
break;
}
}
static void
virtio_address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
{
uint32_t val;
/* address_space_* APIs assume an aligned address.
* As address is under guest control, handle illegal values.
*/
addr &= ~(len - 1);
/* Make sure caller aligned buf properly */
assert(!(((uintptr_t)buf) & (len - 1)));
switch (len) {
case 1:
val = address_space_ldub(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
pci_set_byte(buf, val);
break;
case 2:
val = address_space_lduw_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
pci_set_word(buf, val);
break;
case 4:
val = address_space_ldl_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
pci_set_long(buf, val);
break;
default:
/* As length is under guest control, handle illegal values. */
break;
}
}
static void virtio_write_config(PCIDevice *pci_dev, uint32_t address,
uint32_t val, int len)
{
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
struct virtio_pci_cfg_cap *cfg;
pci_default_write_config(pci_dev, address, val, len);
@@ -456,6 +534,49 @@ static void virtio_write_config(PCIDevice *pci_dev, uint32_t address,
virtio_pci_stop_ioeventfd(proxy);
virtio_set_status(vdev, vdev->status & ~VIRTIO_CONFIG_S_DRIVER_OK);
}
if (proxy->config_cap &&
ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
pci_cfg_data),
sizeof cfg->pci_cfg_data)) {
uint32_t off;
uint32_t len;
cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
off = le32_to_cpu(cfg->cap.offset);
len = le32_to_cpu(cfg->cap.length);
if (len <= sizeof cfg->pci_cfg_data) {
virtio_address_space_write(&proxy->modern_as, off,
cfg->pci_cfg_data, len);
}
}
}
static uint32_t virtio_read_config(PCIDevice *pci_dev,
uint32_t address, int len)
{
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
struct virtio_pci_cfg_cap *cfg;
if (proxy->config_cap &&
ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
pci_cfg_data),
sizeof cfg->pci_cfg_data)) {
uint32_t off;
uint32_t len;
cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
off = le32_to_cpu(cfg->cap.offset);
len = le32_to_cpu(cfg->cap.length);
if (len <= sizeof cfg->pci_cfg_data) {
virtio_address_space_read(&proxy->modern_as, off,
cfg->pci_cfg_data, len);
}
}
return pci_default_read_config(pci_dev, address, len);
}
static int kvm_virtio_pci_vq_vector_use(VirtIOPCIProxy *proxy,
@@ -942,7 +1063,7 @@ static int virtio_pci_query_nvectors(DeviceState *d)
return proxy->nvectors;
}
static void virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy,
static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy,
struct virtio_pci_cap *cap)
{
PCIDevice *dev = &proxy->pci_dev;
@@ -954,6 +1075,8 @@ static void virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy,
assert(cap->cap_len >= sizeof *cap);
memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len,
cap->cap_len - PCI_CAP_FLAGS);
return offset;
}
static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr,
@@ -1329,6 +1452,11 @@ static void virtio_pci_device_plugged(DeviceState *d, Error **errp)
.notify_off_multiplier =
cpu_to_le32(QEMU_VIRTIO_PCI_QUEUE_MEM_MULT),
};
struct virtio_pci_cfg_cap cfg = {
.cap.cap_len = sizeof cfg,
.cap.cfg_type = VIRTIO_PCI_CAP_PCI_CFG,
};
struct virtio_pci_cfg_cap *cfg_mask;
/* TODO: add io access for speed */
@@ -1338,11 +1466,19 @@ static void virtio_pci_device_plugged(DeviceState *d, Error **errp)
virtio_pci_modern_region_map(proxy, &proxy->isr, &cap);
virtio_pci_modern_region_map(proxy, &proxy->device, &cap);
virtio_pci_modern_region_map(proxy, &proxy->notify, &notify.cap);
pci_register_bar(&proxy->pci_dev, proxy->modern_mem_bar,
PCI_BASE_ADDRESS_SPACE_MEMORY |
PCI_BASE_ADDRESS_MEM_PREFETCH |
PCI_BASE_ADDRESS_MEM_TYPE_64,
&proxy->modern_bar);
proxy->config_cap = virtio_pci_add_mem_cap(proxy, &cfg.cap);
cfg_mask = (void *)(proxy->pci_dev.wmask + proxy->config_cap);
pci_set_byte(&cfg_mask->cap.bar, ~0x0);
pci_set_long((uint8_t *)&cfg_mask->cap.offset, ~0x0);
pci_set_long((uint8_t *)&cfg_mask->cap.length, ~0x0);
pci_set_long(cfg_mask->pci_cfg_data, ~0x0);
}
if (proxy->nvectors &&
@@ -1354,6 +1490,7 @@ static void virtio_pci_device_plugged(DeviceState *d, Error **errp)
}
proxy->pci_dev.config_write = virtio_write_config;
proxy->pci_dev.config_read = virtio_read_config;
if (legacy) {
size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev)
@@ -1424,6 +1561,15 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
2 * QEMU_VIRTIO_PCI_QUEUE_MEM_MULT *
VIRTIO_QUEUE_MAX);
memory_region_init_alias(&proxy->modern_cfg,
OBJECT(proxy),
"virtio-pci-cfg",
&proxy->modern_bar,
0,
memory_region_size(&proxy->modern_bar));
address_space_init(&proxy->modern_as, &proxy->modern_cfg, "virtio-pci-cfg-as");
virtio_pci_bus_new(&proxy->bus, sizeof(proxy->bus), proxy);
if (k->realize) {
k->realize(proxy, errp);
@@ -1432,7 +1578,10 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
static void virtio_pci_exit(PCIDevice *pci_dev)
{
VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
msix_uninit_exclusive_bar(pci_dev);
address_space_destroy(&proxy->modern_as);
}
static void virtio_pci_reset(DeviceState *qdev)
hw/virtio/virtio-pci.h
+3
View File
@@ -112,9 +112,12 @@ struct VirtIOPCIProxy {
VirtIOPCIRegion device;
VirtIOPCIRegion notify;
MemoryRegion modern_bar;
MemoryRegion modern_cfg;
AddressSpace modern_as;
uint32_t legacy_io_bar;
uint32_t msix_bar;
uint32_t modern_mem_bar;
int config_cap;
uint32_t flags;
uint32_t class_code;
uint32_t nvectors;
include/hw/acpi/ich9.h
+7 -1
View File
@@ -25,6 +25,7 @@
#include "hw/acpi/cpu_hotplug.h"
#include "hw/acpi/memory_hotplug.h"
#include "hw/acpi/acpi_dev_interface.h"
#include "hw/acpi/tco.h"
typedef struct ICH9LPCPMRegs {
/*
@@ -55,10 +56,15 @@ typedef struct ICH9LPCPMRegs {
uint8_t disable_s4;
uint8_t s4_val;
uint8_t smm_enabled;
bool enable_tco;
TCOIORegs tco_regs;
} ICH9LPCPMRegs;
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
bool smm_enabled, qemu_irq sci_irq);
bool smm_enabled,
bool enable_tco,
qemu_irq sci_irq);
void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
extern const VMStateDescription vmstate_ich9_pm;
include/hw/acpi/tco.h
+82
View File
@@ -0,0 +1,82 @@
/*
* QEMU ICH9 TCO emulation
*
* Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef HW_ACPI_TCO_H
#define HW_ACPI_TCO_H
#include "qemu/typedefs.h"
#include "qemu-common.h"
/* As per ICH9 spec, the internal timer has an error of ~0.6s on every tick */
#define TCO_TICK_NSEC 600000000LL
/* TCO I/O register offsets */
enum {
TCO_RLD = 0x00,
TCO_DAT_IN = 0x02,
TCO_DAT_OUT = 0x03,
TCO1_STS = 0x04,
TCO2_STS = 0x06,
TCO1_CNT = 0x08,
TCO2_CNT = 0x0a,
TCO_MESSAGE1 = 0x0c,
TCO_MESSAGE2 = 0x0d,
TCO_WDCNT = 0x0e,
SW_IRQ_GEN = 0x10,
TCO_TMR = 0x12,
};
/* TCO I/O register control/status bits */
enum {
SW_TCO_SMI = 1 << 1,
TCO_INT_STS = 1 << 2,
TCO_LOCK = 1 << 12,
TCO_TMR_HLT = 1 << 11,
TCO_TIMEOUT = 1 << 3,
TCO_SECOND_TO_STS = 1 << 1,
TCO_BOOT_STS = 1 << 2,
};
/* TCO I/O registers mask bits */
enum {
TCO_RLD_MASK = 0x3ff,
TCO1_STS_MASK = 0xe870,
TCO2_STS_MASK = 0xfff8,
TCO1_CNT_MASK = 0xfeff,
TCO_TMR_MASK = 0x3ff,
};
typedef struct TCOIORegs {
struct {
uint16_t rld;
uint8_t din;
uint8_t dout;
uint16_t sts1;
uint16_t sts2;
uint16_t cnt1;
uint16_t cnt2;
uint8_t msg1;
uint8_t msg2;
uint8_t wdcnt;
uint16_t tmr;
} tco;
uint8_t sw_irq_gen;
QEMUTimer *tco_timer;
int64_t expire_time;
uint8_t timeouts_no;
MemoryRegion io;
} TCOIORegs;
/* tco.c */
void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent);
extern const VMStateDescription vmstate_tco_io_sts;
#endif /* HW_ACPI_TCO_H */
include/hw/boards.h
+2 -1
View File
@@ -99,7 +99,8 @@ struct MachineClass {
no_floppy:1,
no_cdrom:1,
no_sdcard:1,
has_dynamic_sysbus:1;
has_dynamic_sysbus:1,
no_tco:1;
int is_default;
const char *default_machine_opts;
const char *default_boot_order;
include/hw/i386/ich9.h
+15 -1
View File
@@ -17,9 +17,12 @@
void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled, bool enable_tco);
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
void ich9_generate_smi(void);
void ich9_generate_nmi(void);
#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
@@ -43,6 +46,11 @@ typedef struct ICH9LPCState {
ICH9LPCPMRegs pm;
uint32_t sci_level; /* track sci level */
/* 2.24 Pin Straps */
struct {
bool spkr_hi;
} pin_strap;
/* 10.1 Chipset Configuration registers(Memory Space)
which is pointed by RCBA */
uint8_t chip_config[ICH9_CC_SIZE];
@@ -90,6 +98,9 @@ Object *ich9_lpc_find(void);
#define ICH9_CC_DIR_MASK 0x7
#define ICH9_CC_OIC 0x31FF
#define ICH9_CC_OIC_AEN 0x1
#define ICH9_CC_GCS 0x3410
#define ICH9_CC_GCS_DEFAULT 0x00000020
#define ICH9_CC_GCS_NO_REBOOT (1 << 5)
/* D28:F[0-5] */
#define ICH9_PCIE_DEV 28
@@ -186,7 +197,10 @@ Object *ich9_lpc_find(void);
#define ICH9_PMIO_GPE0_LEN 16
#define ICH9_PMIO_SMI_EN 0x30
#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
#define ICH9_PMIO_SMI_STS 0x34
#define ICH9_PMIO_TCO_RLD 0x60
#define ICH9_PMIO_TCO_LEN 32
/* FADT ACPI_ENABLE/ACPI_DISABLE */
#define ICH9_APM_ACPI_ENABLE 0x2
include/hw/i386/pc.h
+2 -2
View File
@@ -88,6 +88,7 @@ typedef struct PcPciInfo {
#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
#define ACPI_PM_PROP_TCO_ENABLED "enable_tco"
struct PcGuestInfo {
bool isapc_ram_fw;
@@ -198,13 +199,12 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
ISADevice **rtc_state,
bool create_fdctrl,
ISADevice **floppy,
bool no_vmport,
uint32 hpet_irqs);
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
const char *boot_device, MachineState *machine,
ISADevice *floppy, BusState *ide0, BusState *ide1,
BusState *ide0, BusState *ide1,
ISADevice *s);
void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_pci_device_init(PCIBus *pci_bus);
include/hw/pci/pci_regs.h
+1 -719
View File
File diff suppressed because it is too large Load Diff
include/hw/virtio/virtio-net.h
-12
View File
@@ -21,9 +21,6 @@
#define VIRTIO_NET(obj) \
OBJECT_CHECK(VirtIONet, (obj), TYPE_VIRTIO_NET)
#define VIRTIO_NET_F_CTRL_GUEST_OFFLOADS 2 /* Control channel offload
* configuration support */
#define TX_TIMER_INTERVAL 150000 /* 150 us */
/* Limit the number of packets that can be sent via a single flush
@@ -100,15 +97,6 @@ typedef struct VirtIONet {
int announce_counter;
} VirtIONet;
/*
* Control network offloads
*
* Dynamic offloads are available with the
* VIRTIO_NET_F_CTRL_GUEST_OFFLOADS feature bit.
*/
#define VIRTIO_NET_CTRL_GUEST_OFFLOADS 5
#define VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET 0
void virtio_net_set_netclient_name(VirtIONet *n, const char *name,
const char *type);

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