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Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging

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Convert target/sparc to decodetree.

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# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
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# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
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* tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu: (94 commits)
  target/sparc: Remove disas_sparc_legacy
  target/sparc: Convert FZERO, FONE to decodetree
  target/sparc: Move FPACK16, FPACKFIX to decodetree
  target/sparc: Move FPCMP* to decodetree
  target/sparc: Convert FCMP, FCMPE to decodetree
  target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
  target/sparc: Move FMOVq, FNEGq, FABSq to decodetree
  target/sparc: Move FdTOq, FxTOq to decodetree
  target/sparc: Move FiTOq, FsTOq to decodetree
  target/sparc: Move FqTOd, FqTOx to decodetree
  target/sparc: Move FqTOs, FqTOi to decodetree
  target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree
  target/sparc: Move gen_fop_FD insns to decodetree
  target/sparc: Move FDMULQ to decodetree
  target/sparc: Move FSMULD to decodetree
  target/sparc: Move gen_fop_QQQ insns to decodetree
  target/sparc: Move gen_fop_DDD insns to decodetree
  target/sparc: Move gen_fop_FFF insns to decodetree
  target/sparc: Move FSQRTq to decodetree
  target/sparc: Move gen_fop_DD insns to decodetree
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
2023-10-27 09:43:53 +09:00
parent 3c95fd4ed8 ba9c09b40b
commit c60be6e3e3
14 changed files with 4028 additions and 3780 deletions
Download Patch File Download Diff File Expand all files Collapse all files
configs/targets/sparc-softmmu.mak
+1
View File
@@ -1,2 +1,3 @@
TARGET_ARCH=sparc
TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y
configs/targets/sparc64-softmmu.mak
+1
View File
@@ -1,3 +1,4 @@
TARGET_ARCH=sparc64
TARGET_BASE_ARCH=sparc
TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y
linux-user/sparc/target_syscall.h
+1 -5
View File
@@ -50,11 +50,7 @@ static inline abi_ulong target_shmlba(CPUSPARCState *env)
#ifdef TARGET_SPARC64
return MAX(TARGET_PAGE_SIZE, 16 * 1024);
#else
if (!(env->def.features & CPU_FEATURE_FLUSH)) {
return 64 * 1024;
} else {
return 256 * 1024;
}
return 256 * 1024;
#endif
}
target/sparc/cpu-feature.h.inc
+14
View File
@@ -0,0 +1,14 @@
FEATURE(FLOAT128)
FEATURE(MUL)
FEATURE(DIV)
FEATURE(VIS1)
FEATURE(VIS2)
FEATURE(FSMULD)
FEATURE(HYPV)
FEATURE(CMT)
FEATURE(GL)
FEATURE(TA0_SHUTDOWN) /* Shutdown on "ta 0x0" */
FEATURE(ASR17)
FEATURE(CACHE_CTRL)
FEATURE(POWERDOWN)
FEATURE(CASA)
target/sparc/cpu.c
+38 -34
View File
@@ -403,9 +403,7 @@ static const sparc_def_t sparc_defs[] = {
.mmu_sfsr_mask = 0x00016fff,
.mmu_trcr_mask = 0x0000003f,
.nwindows = 7,
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
CPU_FEATURE_FMUL,
.features = CPU_FEATURE_MUL | CPU_FEATURE_DIV,
},
{
.name = "TI MicroSparc II",
@@ -545,21 +543,20 @@ static const sparc_def_t sparc_defs[] = {
#endif
};
/* This must match sparc_cpu_properties[]. */
static const char * const feature_name[] = {
"float",
"float128",
"swap",
"mul",
"div",
"flush",
"fsqrt",
"fmul",
"vis1",
"vis2",
"fsmuld",
"hypv",
"cmt",
"gl",
[CPU_FEATURE_BIT_FLOAT128] = "float128",
#ifdef TARGET_SPARC64
[CPU_FEATURE_BIT_CMT] = "cmt",
[CPU_FEATURE_BIT_GL] = "gl",
[CPU_FEATURE_BIT_HYPV] = "hypv",
[CPU_FEATURE_BIT_VIS1] = "vis1",
[CPU_FEATURE_BIT_VIS2] = "vis2",
#else
[CPU_FEATURE_BIT_MUL] = "mul",
[CPU_FEATURE_BIT_DIV] = "div",
[CPU_FEATURE_BIT_FSMULD] = "fsmuld",
#endif
};
static void print_features(uint32_t features, const char *prefix)
@@ -757,9 +754,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
CPUSPARCState *env = &cpu->env;
#if defined(CONFIG_USER_ONLY)
if ((env->def.features & CPU_FEATURE_FLOAT)) {
env->def.features |= CPU_FEATURE_FLOAT128;
}
/* We are emulating the kernel, which will trap and emulate float128. */
env->def.features |= CPU_FEATURE_FLOAT128;
#endif
env->version = env->def.iu_version;
@@ -835,21 +831,29 @@ static PropertyInfo qdev_prop_nwindows = {
.set = sparc_set_nwindows,
};
/* This must match feature_name[]. */
static Property sparc_cpu_properties[] = {
DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, 0, false),
DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 1, false),
DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, 2, false),
DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 3, false),
DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 4, false),
DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, 5, false),
DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, 6, false),
DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, 7, false),
DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 8, false),
DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 9, false),
DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 10, false),
DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 11, false),
DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 12, false),
DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 13, false),
DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FLOAT128, false),
#ifdef TARGET_SPARC64
DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_CMT, false),
DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_GL, false),
DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_HYPV, false),
DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_VIS1, false),
DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_VIS2, false),
#else
DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_MUL, false),
DEFINE_PROP_BIT("div", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_DIV, false),
DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FSMULD, false),
#endif
DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
qdev_prop_uint64, target_ulong),
DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
target/sparc/cpu.h
+43 -33
View File
@@ -6,6 +6,29 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
/*
* From Oracle SPARC Architecture 2015:
*
* Compatibility notes: The PSO memory model described in SPARC V8 and
* SPARC V9 compatibility architecture specifications was never implemented
* in a SPARC V9 implementation and is not included in the Oracle SPARC
* Architecture specification.
*
* The RMO memory model described in the SPARC V9 specification was
* implemented in some non-Sun SPARC V9 implementations, but is not
* directly supported in Oracle SPARC Architecture 2015 implementations.
*
* Therefore always use TSO in QEMU.
*
* D.5 Specification of Partial Store Order (PSO)
* ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
*
* D.6 Specification of Total Store Order (TSO)
* ... PSO with the additional requirement that all [stores] are followed
* by an implied MEMBAR #StoreStore.
*/
#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
#else
@@ -268,38 +291,27 @@ struct sparc_def_t {
uint32_t maxtl;
};
#define CPU_FEATURE_FLOAT (1 << 0)
#define CPU_FEATURE_FLOAT128 (1 << 1)
#define CPU_FEATURE_SWAP (1 << 2)
#define CPU_FEATURE_MUL (1 << 3)
#define CPU_FEATURE_DIV (1 << 4)
#define CPU_FEATURE_FLUSH (1 << 5)
#define CPU_FEATURE_FSQRT (1 << 6)
#define CPU_FEATURE_FMUL (1 << 7)
#define CPU_FEATURE_VIS1 (1 << 8)
#define CPU_FEATURE_VIS2 (1 << 9)
#define CPU_FEATURE_FSMULD (1 << 10)
#define CPU_FEATURE_HYPV (1 << 11)
#define CPU_FEATURE_CMT (1 << 12)
#define CPU_FEATURE_GL (1 << 13)
#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
#define CPU_FEATURE_ASR17 (1 << 15)
#define CPU_FEATURE_CACHE_CTRL (1 << 16)
#define CPU_FEATURE_POWERDOWN (1 << 17)
#define CPU_FEATURE_CASA (1 << 18)
#define FEATURE(X) CPU_FEATURE_BIT_##X,
enum {
#include "cpu-feature.h.inc"
};
#undef FEATURE
#define FEATURE(X) CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X,
enum {
#include "cpu-feature.h.inc"
};
#undef FEATURE
#ifndef TARGET_SPARC64
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FSMULD)
#else
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
CPU_FEATURE_CASA)
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \
CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2)
enum {
mmu_us_12, // Ultrasparc < III (64 entry TLB)
mmu_us_3, // Ultrasparc III (512 entry TLB)
@@ -782,14 +794,12 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
if (env->pstate & PS_AM) {
flags |= TB_FLAG_AM_ENABLED;
}
if ((env->def.features & CPU_FEATURE_FLOAT)
&& (env->pstate & PS_PEF)
&& (env->fprs & FPRS_FEF)) {
if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
flags |= TB_FLAG_FPU_ENABLED;
}
flags |= env->asi << TB_FLAG_ASI_SHIFT;
#else
if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
if (env->psref) {
flags |= TB_FLAG_FPU_ENABLED;
}
#endif
target/sparc/fop_helper.c
+2 -15
View File
@@ -382,20 +382,7 @@ static void set_fsr(CPUSPARCState *env, target_ulong fsr)
set_float_rounding_mode(rnd_mode, &env->fp_status);
}
target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr,
uint32_t new_fsr)
void helper_set_fsr(CPUSPARCState *env, target_ulong fsr)
{
old_fsr = (new_fsr & FSR_LDFSR_MASK) | (old_fsr & FSR_LDFSR_OLDMASK);
set_fsr(env, old_fsr);
return old_fsr;
set_fsr(env, fsr);
}
#ifdef TARGET_SPARC64
target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr,
uint64_t new_fsr)
{
old_fsr = (new_fsr & FSR_LDXFSR_MASK) | (old_fsr & FSR_LDXFSR_OLDMASK);
set_fsr(env, old_fsr);
return old_fsr;
}
#endif
target/sparc/helper.c
-8
View File
@@ -102,9 +102,7 @@ static target_ulong do_udiv(CPUSPARCState *env, target_ulong a,
}
if (cc) {
env->cc_dst = x0;
env->cc_src2 = overflow;
env->cc_op = CC_OP_DIV;
}
return x0;
}
@@ -143,9 +141,7 @@ static target_ulong do_sdiv(CPUSPARCState *env, target_ulong a,
}
if (cc) {
env->cc_dst = x0;
env->cc_src2 = overflow;
env->cc_op = CC_OP_DIV;
}
return x0;
}
@@ -202,10 +198,8 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1,
}
/* Only modify the CC after any exceptions have been generated. */
env->cc_op = CC_OP_TADDTV;
env->cc_src = src1;
env->cc_src2 = src2;
env->cc_dst = dst;
return dst;
tag_overflow:
@@ -230,10 +224,8 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1,
}
/* Only modify the CC after any exceptions have been generated. */
env->cc_op = CC_OP_TSUBTV;
env->cc_src = src1;
env->cc_src2 = src2;
env->cc_dst = dst;
return dst;
tag_overflow:
target/sparc/helper.h
+1 -15
View File
@@ -24,7 +24,6 @@ DEF_HELPER_FLAGS_2(tick_set_count, TCG_CALL_NO_RWG, void, ptr, i64)
DEF_HELPER_FLAGS_3(tick_get_count, TCG_CALL_NO_WG, i64, env, ptr, int)
DEF_HELPER_FLAGS_2(tick_set_limit, TCG_CALL_NO_RWG, void, ptr, i64)
#endif
DEF_HELPER_FLAGS_3(check_align, TCG_CALL_NO_WG, void, env, tl, i32)
DEF_HELPER_1(debug, void, env)
DEF_HELPER_1(save, void, env)
DEF_HELPER_1(restore, void, env)
@@ -43,7 +42,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32)
DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32)
#endif
DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_3(ldfsr, TCG_CALL_NO_RWG, tl, env, tl, i32)
DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32)
DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64)
@@ -55,7 +54,6 @@ DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env)
#ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_3(ldxfsr, TCG_CALL_NO_RWG, tl, env, tl, i64)
DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32)
@@ -139,18 +137,6 @@ DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
#define VIS_HELPER(name) \
DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \
DEF_HELPER_FLAGS_2(f ## name ## 16s, TCG_CALL_NO_RWG_SE, \
i32, i32, i32) \
DEF_HELPER_FLAGS_2(f ## name ## 32, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \
DEF_HELPER_FLAGS_2(f ## name ## 32s, TCG_CALL_NO_RWG_SE, \
i32, i32, i32)
VIS_HELPER(padd)
VIS_HELPER(psub)
#define VIS_CMPHELPER(name) \
DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \
target/sparc/insns.decode
+547
View File
File diff suppressed because it is too large Load Diff
target/sparc/ldst_helper.c
+8 -9
View File
@@ -360,6 +360,7 @@ static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra)
#endif /* !CONFIG_USER_ONLY */
#endif
#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)
static void do_check_align(CPUSPARCState *env, target_ulong addr,
uint32_t align, uintptr_t ra)
{
@@ -367,11 +368,7 @@ static void do_check_align(CPUSPARCState *env, target_ulong addr,
cpu_raise_exception_ra(env, TT_UNALIGNED, ra);
}
}
void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
{
do_check_align(env, addr, align, GETPC());
}
#endif
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
defined(DEBUG_MXCC)
@@ -1653,7 +1650,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
env->dmmu.sun4v_tsb_pointers[idx] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
goto illegal_insn;
}
break;
case 0x33:
@@ -1665,7 +1662,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
*/
env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
goto illegal_insn;
}
break;
case 0x35:
@@ -1682,7 +1679,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
env->immu.sun4v_tsb_pointers[idx] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
goto illegal_insn;
}
break;
case 0x37:
@@ -1694,7 +1691,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
*/
env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
goto illegal_insn;
}
break;
case ASI_UPA_CONFIG: /* UPA config */
@@ -1923,6 +1920,8 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
default:
sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
return;
illegal_insn:
cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC());
}
}
#endif /* CONFIG_USER_ONLY */
target/sparc/meson.build
+3
View File
@@ -1,4 +1,7 @@
gen = decodetree.process('insns.decode')
sparc_ss = ss.source_set()
sparc_ss.add(gen)
sparc_ss.add(files(
'cc_helper.c',
'cpu.c',
target/sparc/translate.c
+3369 -3602
View File
File diff suppressed because it is too large Load Diff
target/sparc/vis_helper.c
-59
View File
@@ -275,65 +275,6 @@ uint64_t helper_fexpand(uint64_t src1, uint64_t src2)
return d.ll;
}
#define VIS_HELPER(name, F) \
uint64_t name##16(uint64_t src1, uint64_t src2) \
{ \
VIS64 s, d; \
\
s.ll = src1; \
d.ll = src2; \
\
d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
\
return d.ll; \
} \
\
uint32_t name##16s(uint32_t src1, uint32_t src2) \
{ \
VIS32 s, d; \
\
s.l = src1; \
d.l = src2; \
\
d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
\
return d.l; \
} \
\
uint64_t name##32(uint64_t src1, uint64_t src2) \
{ \
VIS64 s, d; \
\
s.ll = src1; \
d.ll = src2; \
\
d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
\
return d.ll; \
} \
\
uint32_t name##32s(uint32_t src1, uint32_t src2) \
{ \
VIS32 s, d; \
\
s.l = src1; \
d.l = src2; \
\
d.l = F(d.l, s.l); \
\
return d.l; \
}
#define FADD(a, b) ((a) + (b))
#define FSUB(a, b) ((a) - (b))
VIS_HELPER(helper_fpadd, FADD)
VIS_HELPER(helper_fpsub, FSUB)
#define VIS_CMPHELPER(name, F) \
uint64_t name##16(uint64_t src1, uint64_t src2) \
{ \