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Basic OMAP310 support. Basic Palm Tungsten|E machine emulation.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3091 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
2007-07-29 17:57:26 +00:00
parent a5236105db
commit c3d2689d88
12 changed files with 5143 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Makefile.target
+1
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@@ -463,6 +463,7 @@ VL_OBJS+= arm-semi.o
VL_OBJS+= pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
VL_OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o max111x.o max7310.o
VL_OBJS+= spitz.o ads7846.o ide.o serial.o nand.o $(AUDIODRV) wm8750.o
VL_OBJS+= omap.o omap_lcdc.o omap1_clk.o palm.o
CPPFLAGS += -DHAS_AUDIO
endif
ifeq ($(TARGET_BASE_ARCH), sh4)
cpu-all.h
+2 -1
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@@ -702,7 +702,8 @@ void cpu_dump_statistics (CPUState *env, FILE *f,
int flags);
void cpu_abort(CPUState *env, const char *fmt, ...)
__attribute__ ((__format__ (__printf__, 2, 3)));
__attribute__ ((__format__ (__printf__, 2, 3)))
__attribute__ ((__noreturn__));
extern CPUState *first_cpu;
extern CPUState *cpu_single_env;
extern int code_copy_enabled;
hw/omap.c
+2914
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File diff suppressed because it is too large Load Diff
hw/omap.h
+581
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File diff suppressed because it is too large Load Diff
hw/omap1_clk.c
+745
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File diff suppressed because it is too large Load Diff
hw/omap_lcd_template.h
+172
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@@ -0,0 +1,172 @@
/*
* QEMU OMAP LCD Emulator templates
*
* Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if DEPTH == 8
# define BPP 1
# define PIXEL_TYPE uint8_t
#elif DEPTH == 15 || DEPTH == 16
# define BPP 2
# define PIXEL_TYPE uint16_t
#elif DEPTH == 32
# define BPP 4
# define PIXEL_TYPE uint32_t
#else
# error unsupport depth
#endif
/*
* 2-bit colour
*/
static void glue(draw_line2_, DEPTH)(
uint8_t *d, const uint8_t *s, int width, const uint16_t *pal)
{
uint8_t v, r, g, b;
do {
v = ldub_raw((void *) s);
r = (pal[v & 3] >> 4) & 0xf0;
g = pal[v & 3] & 0xf0;
b = (pal[v & 3] << 4) & 0xf0;
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
d += BPP;
v >>= 2;
r = (pal[v & 3] >> 4) & 0xf0;
g = pal[v & 3] & 0xf0;
b = (pal[v & 3] << 4) & 0xf0;
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
d += BPP;
v >>= 2;
r = (pal[v & 3] >> 4) & 0xf0;
g = pal[v & 3] & 0xf0;
b = (pal[v & 3] << 4) & 0xf0;
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
d += BPP;
v >>= 2;
r = (pal[v & 3] >> 4) & 0xf0;
g = pal[v & 3] & 0xf0;
b = (pal[v & 3] << 4) & 0xf0;
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
d += BPP;
s ++;
width -= 4;
} while (width > 0);
}
/*
* 4-bit colour
*/
static void glue(draw_line4_, DEPTH)(
uint8_t *d, const uint8_t *s, int width, const uint16_t *pal)
{
uint8_t v, r, g, b;
do {
v = ldub_raw((void *) s);
r = (pal[v & 0xf] >> 4) & 0xf0;
g = pal[v & 0xf] & 0xf0;
b = (pal[v & 0xf] << 4) & 0xf0;
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
d += BPP;
v >>= 4;
r = (pal[v & 0xf] >> 4) & 0xf0;
g = pal[v & 0xf] & 0xf0;
b = (pal[v & 0xf] << 4) & 0xf0;
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
d += BPP;
s ++;
width -= 2;
} while (width > 0);
}
/*
* 8-bit colour
*/
static void glue(draw_line8_, DEPTH)(
uint8_t *d, const uint8_t *s, int width, const uint16_t *pal)
{
uint8_t v, r, g, b;
do {
v = ldub_raw((void *) s);
r = (pal[v] >> 4) & 0xf0;
g = pal[v] & 0xf0;
b = (pal[v] << 4) & 0xf0;
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
s ++;
d += BPP;
} while (-- width != 0);
}
/*
* 12-bit colour
*/
static void glue(draw_line12_, DEPTH)(
uint8_t *d, const uint8_t *s, int width, const uint16_t *pal)
{
uint16_t v;
uint8_t r, g, b;
do {
v = lduw_raw((void *) s);
r = (v >> 4) & 0xf0;
g = v & 0xf0;
b = (v << 4) & 0xf0;
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
s += 2;
d += BPP;
} while (-- width != 0);
}
/*
* 16-bit colour
*/
static void glue(draw_line16_, DEPTH)(
uint8_t *d, const uint8_t *s, int width, const uint16_t *pal)
{
#if DEPTH == 16 && defined(WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
memcpy(d, s, width * 2);
#else
uint16_t v;
uint8_t r, g, b;
do {
v = lduw_raw((void *) s);
r = (v >> 8) & 0xf8;
g = (v >> 3) & 0xfc;
b = (v << 3) & 0xf8;
((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
s += 2;
d += BPP;
} while (-- width != 0);
#endif
}
#undef DEPTH
#undef BPP
#undef PIXEL_TYPE
hw/omap_lcdc.c
+499
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@@ -0,0 +1,499 @@
/*
* OMAP LCD controller.
*
* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "vl.h"
struct omap_lcd_panel_s {
target_phys_addr_t base;
qemu_irq irq;
DisplayState *state;
ram_addr_t imif_base;
ram_addr_t emiff_base;
int plm;
int tft;
int mono;
int enable;
int width;
int height;
int interrupts;
uint32_t timing[3];
uint32_t subpanel;
uint32_t ctrl;
struct omap_dma_lcd_channel_s *dma;
uint16_t palette[256];
int palette_done;
int frame_done;
int invalidate;
int sync_error;
};
static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
{
if (s->frame_done && (s->interrupts & 1)) {
qemu_irq_raise(s->irq);
return;
}
if (s->palette_done && (s->interrupts & 2)) {
qemu_irq_raise(s->irq);
return;
}
if (s->sync_error) {
qemu_irq_raise(s->irq);
return;
}
qemu_irq_lower(s->irq);
}
#include "pixel_ops.h"
typedef void draw_line_func(
uint8_t *d, const uint8_t *s, int width, const uint16_t *pal);
#define DEPTH 8
#include "omap_lcd_template.h"
#define DEPTH 15
#include "omap_lcd_template.h"
#define DEPTH 16
#include "omap_lcd_template.h"
#define DEPTH 32
#include "omap_lcd_template.h"
static draw_line_func *draw_line_table2[33] = {
[0 ... 32] = 0,
[8] = draw_line2_8,
[15] = draw_line2_15,
[16] = draw_line2_16,
[32] = draw_line2_32,
}, *draw_line_table4[33] = {
[0 ... 32] = 0,
[8] = draw_line4_8,
[15] = draw_line4_15,
[16] = draw_line4_16,
[32] = draw_line4_32,
}, *draw_line_table8[33] = {
[0 ... 32] = 0,
[8] = draw_line8_8,
[15] = draw_line8_15,
[16] = draw_line8_16,
[32] = draw_line8_32,
}, *draw_line_table12[33] = {
[0 ... 32] = 0,
[8] = draw_line12_8,
[15] = draw_line12_15,
[16] = draw_line12_16,
[32] = draw_line12_32,
}, *draw_line_table16[33] = {
[0 ... 32] = 0,
[8] = draw_line16_8,
[15] = draw_line16_15,
[16] = draw_line16_16,
[32] = draw_line16_32,
};
void omap_update_display(void *opaque)
{
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
draw_line_func *draw_line;
int size, dirty[2], minline, maxline, height;
int line, width, linesize, step, bpp, frame_offset;
ram_addr_t frame_base, scanline, newline, x;
uint8_t *s, *d;
if (!omap_lcd || omap_lcd->plm == 1 ||
!omap_lcd->enable || !omap_lcd->state->depth)
return;
frame_offset = 0;
if (omap_lcd->plm != 2) {
memcpy(omap_lcd->palette, phys_ram_base +
omap_lcd->dma->phys_framebuffer[
omap_lcd->dma->current_frame], 0x200);
switch (omap_lcd->palette[0] >> 12 & 7) {
case 3 ... 7:
frame_offset += 0x200;
break;
default:
frame_offset += 0x20;
}
}
/* Colour depth */
switch ((omap_lcd->palette[0] >> 12) & 7) {
case 1:
draw_line = draw_line_table2[omap_lcd->state->depth];
bpp = 2;
break;
case 2:
draw_line = draw_line_table4[omap_lcd->state->depth];
bpp = 4;
break;
case 3:
draw_line = draw_line_table8[omap_lcd->state->depth];
bpp = 8;
break;
case 4 ... 7:
if (!omap_lcd->tft)
draw_line = draw_line_table12[omap_lcd->state->depth];
else
draw_line = draw_line_table16[omap_lcd->state->depth];
bpp = 16;
break;
default:
/* Unsupported at the moment. */
return;
}
/* Resolution */
width = omap_lcd->width;
if (width != omap_lcd->state->width ||
omap_lcd->height != omap_lcd->state->height) {
dpy_resize(omap_lcd->state,
omap_lcd->width, omap_lcd->height);
omap_lcd->invalidate = 1;
}
if (omap_lcd->dma->current_frame == 0)
size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top;
else
size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top;
if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) {
omap_lcd->sync_error = 1;
omap_lcd_interrupts(omap_lcd);
omap_lcd->enable = 0;
return;
}
/* Content */
frame_base = omap_lcd->dma->phys_framebuffer[
omap_lcd->dma->current_frame] + frame_offset;
omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame;
if (omap_lcd->dma->interrupts & 1)
qemu_irq_raise(omap_lcd->dma->irq);
if (omap_lcd->dma->dual)
omap_lcd->dma->current_frame ^= 1;
if (!omap_lcd->state->depth)
return;
line = 0;
height = omap_lcd->height;
if (omap_lcd->subpanel & (1 << 31)) {
if (omap_lcd->subpanel & (1 << 29))
line = (omap_lcd->subpanel >> 16) & 0x3ff;
else
height = (omap_lcd->subpanel >> 16) & 0x3ff;
/* TODO: fill the rest of the panel with DPD */
}
step = width * bpp >> 3;
scanline = frame_base + step * line;
s = (uint8_t *) (phys_ram_base + scanline);
d = omap_lcd->state->data;
linesize = omap_lcd->state->linesize;
dirty[0] = dirty[1] =
cpu_physical_memory_get_dirty(scanline, VGA_DIRTY_FLAG);
minline = height;
maxline = line;
for (; line < height; line ++) {
newline = scanline + step;
for (x = scanline + TARGET_PAGE_SIZE; x < newline;
x += TARGET_PAGE_SIZE) {
dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
dirty[0] |= dirty[1];
}
if (dirty[0] || omap_lcd->invalidate) {
draw_line(d, s, width, omap_lcd->palette);
if (line < minline)
minline = line;
maxline = line + 1;
}
scanline = newline;
dirty[0] = dirty[1];
s += step;
d += linesize;
}
if (maxline >= minline) {
dpy_update(omap_lcd->state, 0, minline, width, maxline);
cpu_physical_memory_reset_dirty(frame_base + step * minline,
frame_base + step * maxline, VGA_DIRTY_FLAG);
}
}
static int ppm_save(const char *filename, uint8_t *data,
int w, int h, int linesize)
{
FILE *f;
uint8_t *d, *d1;
unsigned int v;
int y, x, bpp;
f = fopen(filename, "wb");
if (!f)
return -1;
fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
d1 = data;
bpp = linesize / w;
for (y = 0; y < h; y ++) {
d = d1;
for (x = 0; x < w; x ++) {
v = *(uint32_t *) d;
switch (bpp) {
case 2:
fputc((v >> 8) & 0xf8, f);
fputc((v >> 3) & 0xfc, f);
fputc((v << 3) & 0xf8, f);
break;
case 3:
case 4:
default:
fputc((v >> 16) & 0xff, f);
fputc((v >> 8) & 0xff, f);
fputc((v) & 0xff, f);
break;
}
d += bpp;
}
d1 += linesize;
}
fclose(f);
return 0;
}
void omap_screen_dump(void *opaque, const char *filename) {
struct omap_lcd_panel_s *omap_lcd = opaque;
omap_update_display(opaque);
if (omap_lcd && omap_lcd->state->data)
ppm_save(filename, omap_lcd->state->data,
omap_lcd->width, omap_lcd->height,
omap_lcd->state->linesize);
}
void omap_invalidate_display(void *opaque) {
struct omap_lcd_panel_s *omap_lcd = opaque;
omap_lcd->invalidate = 1;
}
void omap_lcd_update(struct omap_lcd_panel_s *s) {
if (!s->enable) {
s->dma->current_frame = -1;
s->sync_error = 0;
if (s->plm != 1)
s->frame_done = 1;
omap_lcd_interrupts(s);
return;
}
if (s->dma->current_frame == -1) {
s->frame_done = 0;
s->palette_done = 0;
s->dma->current_frame = 0;
}
if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu,
s->dma->src_f1_top) ||
!s->dma->mpu->port[
s->dma->src].addr_valid(s->dma->mpu,
s->dma->src_f1_bottom) ||
(s->dma->dual &&
(!s->dma->mpu->port[
s->dma->src].addr_valid(s->dma->mpu,
s->dma->src_f2_top) ||
!s->dma->mpu->port[
s->dma->src].addr_valid(s->dma->mpu,
s->dma->src_f2_bottom)))) {
s->dma->condition |= 1 << 2;
if (s->dma->interrupts & (1 << 1))
qemu_irq_raise(s->dma->irq);
s->enable = 0;
return;
}
if (s->dma->src == imif) {
/* Framebuffers are in SRAM */
s->dma->phys_framebuffer[0] = s->imif_base +
s->dma->src_f1_top - OMAP_IMIF_BASE;
s->dma->phys_framebuffer[1] = s->imif_base +
s->dma->src_f2_top - OMAP_IMIF_BASE;
} else {
/* Framebuffers are in RAM */
s->dma->phys_framebuffer[0] = s->emiff_base +
s->dma->src_f1_top - OMAP_EMIFF_BASE;
s->dma->phys_framebuffer[1] = s->emiff_base +
s->dma->src_f2_top - OMAP_EMIFF_BASE;
}
if (s->plm != 2 && !s->palette_done) {
memcpy(s->palette, phys_ram_base +
s->dma->phys_framebuffer[s->dma->current_frame], 0x200);
s->palette_done = 1;
omap_lcd_interrupts(s);
}
}
static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
int offset = addr - s->base;
switch (offset) {
case 0x00: /* LCD_CONTROL */
return (s->tft << 23) | (s->plm << 20) |
(s->tft << 7) | (s->interrupts << 3) |
(s->mono << 1) | s->enable | s->ctrl | 0xfe000c34;
case 0x04: /* LCD_TIMING0 */
return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f;
case 0x08: /* LCD_TIMING1 */
return (s->timing[1] << 10) | (s->height - 1);
case 0x0c: /* LCD_TIMING2 */
return s->timing[2] | 0xfc000000;
case 0x10: /* LCD_STATUS */
return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done;
case 0x14: /* LCD_SUBPANEL */
return s->subpanel;
default:
break;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
int offset = addr - s->base;
switch (offset) {
case 0x00: /* LCD_CONTROL */
s->plm = (value >> 20) & 3;
s->tft = (value >> 7) & 1;
s->interrupts = (value >> 3) & 3;
s->mono = (value >> 1) & 1;
s->ctrl = value & 0x01cff300;
if (s->enable != (value & 1)) {
s->enable = value & 1;
omap_lcd_update(s);
}
break;
case 0x04: /* LCD_TIMING0 */
s->timing[0] = value >> 10;
s->width = (value & 0x3ff) + 1;
break;
case 0x08: /* LCD_TIMING1 */
s->timing[1] = value >> 10;
s->height = (value & 0x3ff) + 1;
break;
case 0x0c: /* LCD_TIMING2 */
s->timing[2] = value;
break;
case 0x10: /* LCD_STATUS */
break;
case 0x14: /* LCD_SUBPANEL */
s->subpanel = value & 0xa1ffffff;
break;
default:
OMAP_BAD_REG(addr);
}
}
static CPUReadMemoryFunc *omap_lcdc_readfn[] = {
omap_lcdc_read,
omap_lcdc_read,
omap_lcdc_read,
};
static CPUWriteMemoryFunc *omap_lcdc_writefn[] = {
omap_lcdc_write,
omap_lcdc_write,
omap_lcdc_write,
};
void omap_lcdc_reset(struct omap_lcd_panel_s *s)
{
s->dma->current_frame = -1;
s->plm = 0;
s->tft = 0;
s->mono = 0;
s->enable = 0;
s->width = 0;
s->height = 0;
s->interrupts = 0;
s->timing[0] = 0;
s->timing[1] = 0;
s->timing[2] = 0;
s->subpanel = 0;
s->palette_done = 0;
s->frame_done = 0;
s->sync_error = 0;
s->invalidate = 1;
s->subpanel = 0;
s->ctrl = 0;
}
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
{
int iomemtype;
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
qemu_mallocz(sizeof(struct omap_lcd_panel_s));
s->irq = irq;
s->dma = dma;
s->base = base;
s->state = ds;
s->imif_base = imif_base;
s->emiff_base = emiff_base;
omap_lcdc_reset(s);
iomemtype = cpu_register_io_memory(0, omap_lcdc_readfn,
omap_lcdc_writefn, s);
cpu_register_physical_memory(s->base, 0x100, iomemtype);
graphic_console_init(ds, omap_update_display,
omap_invalidate_display, omap_screen_dump, s);
return s;
}
hw/palm.c
+140
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@@ -0,0 +1,140 @@
/*
* PalmOne's (TM) PDAs.
*
* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "vl.h"
static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 3) << 3);
}
static uint32_t static_readh(void *opaque, target_phys_addr_t offset) {
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 1) << 3);
}
static uint32_t static_readw(void *opaque, target_phys_addr_t offset) {
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 0) << 3);
}
static void static_write(void *opaque, target_phys_addr_t offset,
uint32_t value) {
#ifdef SPY
printf("%s: value %08lx written at " PA_FMT "\n",
__FUNCTION__, value, offset);
#endif
}
static CPUReadMemoryFunc *static_readfn[] = {
static_readb,
static_readh,
static_readw,
};
static CPUWriteMemoryFunc *static_writefn[] = {
static_write,
static_write,
static_write,
};
/* Palm Tunsgten|E support */
static void palmte_microwire_setup(struct omap_mpu_state_s *cpu)
{
}
static void palmte_init(int ram_size, int vga_ram_size, int boot_device,
DisplayState *ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
struct omap_mpu_state_s *cpu;
int flash_size = 0x00800000;
int sdram_size = 0x02000000;
int io;
static uint32_t cs0val = 0xffffffff;
static uint32_t cs1val = 0x0000e1a0;
static uint32_t cs2val = 0x0000e1a0;
static uint32_t cs3val = 0xe1a0e1a0;
ram_addr_t phys_flash;
int rom_size, rom_loaded = 0;
if (ram_size < flash_size + sdram_size + OMAP15XX_SRAM_SIZE) {
fprintf(stderr, "This architecture uses %i bytes of memory\n",
flash_size + sdram_size + OMAP15XX_SRAM_SIZE);
exit(1);
}
cpu = omap310_mpu_init(sdram_size, ds, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
(phys_flash = qemu_ram_alloc(flash_size)) | IO_MEM_ROM);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs0val);
cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
OMAP_CS0_SIZE - flash_size, io);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val);
cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs2val);
cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs3val);
cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
palmte_microwire_setup(cpu);
/* Setup initial (reset) machine state */
if (nb_option_roms) {
rom_size = get_image_size(option_rom[0]);
if (rom_size > flash_size)
fprintf(stderr, "%s: ROM image too big (%x > %x)\n",
__FUNCTION__, rom_size, flash_size);
else if (rom_size > 0 && load_image(option_rom[0],
phys_ram_base + phys_flash) > 0) {
rom_loaded = 1;
cpu->env->regs[15] = 0x00000000;
} else
fprintf(stderr, "%s: error loading '%s'\n",
__FUNCTION__, option_rom[0]);
}
if (!rom_loaded && !kernel_filename) {
fprintf(stderr, "Kernel or ROM image must be specified\n");
exit(1);
}
/* Load the kernel. */
if (kernel_filename) {
/* Start at bootloader. */
cpu->env->regs[15] = OMAP_EMIFF_BASE;
arm_load_kernel(cpu->env, sdram_size, kernel_filename, kernel_cmdline,
initrd_filename, 0x331, OMAP_EMIFF_BASE);
}
dpy_resize(ds, 320, 320);
}
QEMUMachine palmte_machine = {
"cheetah",
"Palm Tungsten|E aka. Cheetah PDA (OMAP310)",
palmte_init,
};
target-arm/cpu.h
+8 -1
View File
@@ -99,6 +99,10 @@ typedef struct CPUARMState {
uint32_t c13_fcse; /* FCSE PID. */
uint32_t c13_context; /* Context ID. */
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
uint32_t c15_ticonfig; /* TI925T configuration byte. */
uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
uint32_t c15_threadid; /* TI debugger thread-ID. */
} cp15;
/* Coprocessor IO used by peripherals */
@@ -247,7 +251,8 @@ enum arm_features {
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
ARM_FEATURE_MPU /* Only has Memory Protection Unit, not full MMU. */
ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
ARM_FEATURE_OMAPCP /* OMAP specific CP15 ops handling. */
};
static inline int arm_feature(CPUARMState *env, int feature)
@@ -265,6 +270,8 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM1026 0x4106a262
#define ARM_CPUID_ARM926 0x41069265
#define ARM_CPUID_ARM946 0x41059461
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
#define ARM_CPUID_PXA250 0x69052100
#define ARM_CPUID_PXA255 0x69052d00
#define ARM_CPUID_PXA260 0x69052903
target-arm/helper.c
+75 -1
View File
@@ -32,6 +32,15 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
set_feature(env, ARM_FEATURE_OMAPCP);
env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
break;
case ARM_CPUID_PXA250:
case ARM_CPUID_PXA255:
case ARM_CPUID_PXA260:
@@ -101,6 +110,7 @@ static const struct arm_cpu_t arm_cpu_names[] = {
{ ARM_CPUID_ARM926, "arm926"},
{ ARM_CPUID_ARM946, "arm946"},
{ ARM_CPUID_ARM1026, "arm1026"},
{ ARM_CPUID_TI925T, "ti925t" },
{ ARM_CPUID_PXA250, "pxa250" },
{ ARM_CPUID_PXA255, "pxa255" },
{ ARM_CPUID_PXA260, "pxa260" },
@@ -644,8 +654,12 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
case 0: /* ID codes. */
if (arm_feature(env, ARM_FEATURE_XSCALE))
break;
if (arm_feature(env, ARM_FEATURE_OMAPCP))
break;
goto bad_reg;
case 1: /* System configuration. */
if (arm_feature(env, ARM_FEATURE_OMAPCP))
op2 = 0;
switch (op2) {
case 0:
if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
@@ -693,6 +707,8 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
case 4: /* Reserved. */
goto bad_reg;
case 5: /* MMU Fault status / MPU access permission. */
if (arm_feature(env, ARM_FEATURE_OMAPCP))
op2 = 0;
switch (op2) {
case 0:
if (arm_feature(env, ARM_FEATURE_MPU))
@@ -724,6 +740,8 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
goto bad_reg;
env->cp15.c6_region[crm] = val;
} else {
if (arm_feature(env, ARM_FEATURE_OMAPCP))
op2 = 0;
switch (op2) {
case 0:
env->cp15.c6_data = val;
@@ -737,6 +755,8 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
}
break;
case 7: /* Cache control. */
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
/* No cache, so nothing to do. */
break;
case 8: /* MMU TLB control. */
@@ -763,6 +783,8 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
}
break;
case 9:
if (arm_feature(env, ARM_FEATURE_OMAPCP))
break;
switch (crm) {
case 0: /* Cache lockdown. */
switch (op2) {
@@ -823,6 +845,31 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
}
goto bad_reg;
}
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
switch (crm) {
case 0:
break;
case 1: /* Set TI925T configuration. */
env->cp15.c15_ticonfig = val & 0xe7;
env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
ARM_CPUID_TI915T : ARM_CPUID_TI925T;
break;
case 2: /* Set I_max. */
env->cp15.c15_i_max = val;
break;
case 3: /* Set I_min. */
env->cp15.c15_i_min = val;
break;
case 4: /* Set thread-ID. */
env->cp15.c15_threadid = val & 0xffff;
break;
case 8: /* Wait-for-interrupt (deprecated). */
cpu_interrupt(env, CPU_INTERRUPT_HALT);
break;
default:
goto bad_reg;
}
}
break;
}
return;
@@ -834,8 +881,10 @@ bad_reg:
uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
{
uint32_t op2;
uint32_t crm;
op2 = (insn >> 5) & 7;
crm = insn & 0xf;
switch ((insn >> 16) & 0xf) {
case 0: /* ID codes. */
switch (op2) {
@@ -849,6 +898,8 @@ uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
return 0;
}
case 1: /* System configuration. */
if (arm_feature(env, ARM_FEATURE_OMAPCP))
op2 = 0;
switch (op2) {
case 0: /* Control register. */
return env->cp15.c1_sys;
@@ -885,6 +936,8 @@ uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
case 4: /* Reserved. */
goto bad_reg;
case 5: /* MMU Fault status / MPU access permission. */
if (arm_feature(env, ARM_FEATURE_OMAPCP))
op2 = 0;
switch (op2) {
case 0:
if (arm_feature(env, ARM_FEATURE_MPU))
@@ -913,6 +966,8 @@ uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
goto bad_reg;
return env->cp15.c6_region[n];
} else {
if (arm_feature(env, ARM_FEATURE_OMAPCP))
op2 = 0;
switch (op2) {
case 0:
return env->cp15.c6_data;
@@ -933,6 +988,8 @@ uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
case 8: /* MMU TLB control. */
goto bad_reg;
case 9: /* Cache lockdown. */
if (arm_feature(env, ARM_FEATURE_OMAPCP))
return 0;
switch (op2) {
case 0:
return env->cp15.c9_data;
@@ -960,11 +1017,28 @@ uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
goto bad_reg;
case 15: /* Implementation specific. */
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
if (op2 == 0 && (insn & 0xf) == 1)
if (op2 == 0 && crm == 1)
return env->cp15.c15_cpar;
goto bad_reg;
}
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
switch (crm) {
case 0:
return 0;
case 1: /* Read TI925T configuration. */
return env->cp15.c15_ticonfig;
case 2: /* Read I_max. */
return env->cp15.c15_i_max;
case 3: /* Read I_min. */
return env->cp15.c15_i_min;
case 4: /* Read thread-ID. */
return env->cp15.c15_threadid;
case 8: /* TI925T_status */
return 0;
}
goto bad_reg;
}
return 0;
}
bad_reg:
vl.c
+1
View File
@@ -6999,6 +6999,7 @@ void register_machines(void)
qemu_register_machine(&spitzpda_machine);
qemu_register_machine(&borzoipda_machine);
qemu_register_machine(&terrierpda_machine);
qemu_register_machine(&palmte_machine);
#elif defined(TARGET_SH4)
qemu_register_machine(&shix_machine);
#elif defined(TARGET_ALPHA)
vl.h
+5
View File
@@ -1417,6 +1417,9 @@ extern QEMUMachine spitzpda_machine;
extern QEMUMachine borzoipda_machine;
extern QEMUMachine terrierpda_machine;
/* palm.c */
extern QEMUMachine palmte_machine;
/* ps2.c */
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
@@ -1606,6 +1609,8 @@ void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
#include "hw/pxa.h"
#include "hw/omap.h"
/* mcf_uart.c */
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);