mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Follow coding conventions
Remove explicit struct qualifiers and rename structure types. Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
@@ -35,7 +35,7 @@ void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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struct mouse_transform_info_s {
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struct MouseTransformInfo {
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/* Touchscreen resolution */
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int x;
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int y;
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+12
-12
@@ -11,7 +11,7 @@
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#include "devices.h"
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#include "console.h"
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struct ads7846_state_s {
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struct ADS7846State {
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qemu_irq interrupt;
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int input[8];
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@@ -46,7 +46,7 @@ struct ads7846_state_s {
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#define ADS_Z1POS(x, y) 600
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#define ADS_Z2POS(x, y) (600 + 6000 / ADS_XPOS(x, y))
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static void ads7846_int_update(struct ads7846_state_s *s)
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static void ads7846_int_update(ADS7846State *s)
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{
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if (s->interrupt)
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qemu_set_irq(s->interrupt, s->pressure == 0);
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@@ -54,14 +54,14 @@ static void ads7846_int_update(struct ads7846_state_s *s)
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uint32_t ads7846_read(void *opaque)
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{
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struct ads7846_state_s *s = (struct ads7846_state_s *) opaque;
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ADS7846State *s = (ADS7846State *) opaque;
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return s->output;
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}
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void ads7846_write(void *opaque, uint32_t value)
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{
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struct ads7846_state_s *s = (struct ads7846_state_s *) opaque;
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ADS7846State *s = (ADS7846State *) opaque;
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switch (s->cycle ++) {
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case 0:
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@@ -94,7 +94,7 @@ void ads7846_write(void *opaque, uint32_t value)
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static void ads7846_ts_event(void *opaque,
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int x, int y, int z, int buttons_state)
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{
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struct ads7846_state_s *s = opaque;
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ADS7846State *s = opaque;
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if (buttons_state) {
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x = 0x7fff - x;
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@@ -113,7 +113,7 @@ static void ads7846_ts_event(void *opaque,
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static void ads7846_save(QEMUFile *f, void *opaque)
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{
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struct ads7846_state_s *s = (struct ads7846_state_s *) opaque;
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ADS7846State *s = (ADS7846State *) opaque;
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int i;
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for (i = 0; i < 8; i ++)
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@@ -125,7 +125,7 @@ static void ads7846_save(QEMUFile *f, void *opaque)
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static int ads7846_load(QEMUFile *f, void *opaque, int version_id)
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{
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struct ads7846_state_s *s = (struct ads7846_state_s *) opaque;
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ADS7846State *s = (ADS7846State *) opaque;
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int i;
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for (i = 0; i < 8; i ++)
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@@ -140,12 +140,12 @@ static int ads7846_load(QEMUFile *f, void *opaque, int version_id)
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return 0;
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}
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struct ads7846_state_s *ads7846_init(qemu_irq penirq)
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ADS7846State *ads7846_init(qemu_irq penirq)
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{
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struct ads7846_state_s *s;
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s = (struct ads7846_state_s *)
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qemu_mallocz(sizeof(struct ads7846_state_s));
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memset(s, 0, sizeof(struct ads7846_state_s));
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ADS7846State *s;
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s = (ADS7846State *)
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qemu_mallocz(sizeof(ADS7846State));
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memset(s, 0, sizeof(ADS7846State));
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s->interrupt = penirq;
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+1
-1
@@ -37,7 +37,7 @@
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struct nand_state_t
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{
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struct nand_flash_s *nand;
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NANDFlashState *nand;
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unsigned int rdy:1;
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unsigned int ale:1;
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unsigned int cle:1;
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+14
-14
@@ -28,7 +28,7 @@
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typedef void (*blizzard_fn_t)(uint8_t *, const uint8_t *, unsigned int);
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struct blizzard_s {
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typedef struct {
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uint8_t reg;
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uint32_t addr;
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int swallow;
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@@ -120,7 +120,7 @@ struct blizzard_s {
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int pitch;
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blizzard_fn_t line_fn;
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} data;
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};
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} BlizzardState;
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/* Bytes(!) per pixel */
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static const int blizzard_iformat_bpp[0x10] = {
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@@ -144,7 +144,7 @@ static inline void blizzard_rgb2yuv(int r, int g, int b,
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*v = 0x80 + ((0xe0e * r - 0x0bc7 * g - 0x247 * b) >> 13);
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}
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static void blizzard_window(struct blizzard_s *s)
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static void blizzard_window(BlizzardState *s)
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{
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uint8_t *src, *dst;
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int bypp[2];
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@@ -175,7 +175,7 @@ static void blizzard_window(struct blizzard_s *s)
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fn(dst, src, bypl[2]);
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}
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static int blizzard_transfer_setup(struct blizzard_s *s)
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static int blizzard_transfer_setup(BlizzardState *s)
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{
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if (s->source > 3 || !s->bpp ||
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s->ix[1] < s->ix[0] || s->iy[1] < s->iy[0])
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@@ -199,7 +199,7 @@ static int blizzard_transfer_setup(struct blizzard_s *s)
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return 1;
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}
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static void blizzard_reset(struct blizzard_s *s)
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static void blizzard_reset(BlizzardState *s)
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{
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s->reg = 0;
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s->swallow = 0;
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@@ -280,14 +280,14 @@ static void blizzard_reset(struct blizzard_s *s)
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}
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static inline void blizzard_invalidate_display(void *opaque) {
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struct blizzard_s *s = (struct blizzard_s *) opaque;
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BlizzardState *s = (BlizzardState *) opaque;
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s->invalidate = 1;
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}
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static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)
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{
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struct blizzard_s *s = (struct blizzard_s *) opaque;
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BlizzardState *s = (BlizzardState *) opaque;
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switch (reg) {
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case 0x00: /* Revision Code */
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@@ -490,7 +490,7 @@ static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)
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static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
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{
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struct blizzard_s *s = (struct blizzard_s *) opaque;
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BlizzardState *s = (BlizzardState *) opaque;
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switch (reg) {
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case 0x04: /* PLL M-Divider */
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@@ -831,7 +831,7 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
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uint16_t s1d13745_read(void *opaque, int dc)
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{
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struct blizzard_s *s = (struct blizzard_s *) opaque;
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BlizzardState *s = (BlizzardState *) opaque;
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uint16_t value = blizzard_reg_read(s, s->reg);
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if (s->swallow -- > 0)
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@@ -844,7 +844,7 @@ uint16_t s1d13745_read(void *opaque, int dc)
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void s1d13745_write(void *opaque, int dc, uint16_t value)
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{
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struct blizzard_s *s = (struct blizzard_s *) opaque;
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BlizzardState *s = (BlizzardState *) opaque;
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if (s->swallow -- > 0)
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return;
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@@ -860,7 +860,7 @@ void s1d13745_write(void *opaque, int dc, uint16_t value)
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void s1d13745_write_block(void *opaque, int dc,
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void *buf, size_t len, int pitch)
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{
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struct blizzard_s *s = (struct blizzard_s *) opaque;
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BlizzardState *s = (BlizzardState *) opaque;
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while (len > 0) {
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if (s->reg == 0x90 && dc &&
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@@ -886,7 +886,7 @@ void s1d13745_write_block(void *opaque, int dc,
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static void blizzard_update_display(void *opaque)
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{
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struct blizzard_s *s = (struct blizzard_s *) opaque;
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BlizzardState *s = (BlizzardState *) opaque;
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int y, bypp, bypl, bwidth;
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uint8_t *src, *dst;
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@@ -935,7 +935,7 @@ static void blizzard_update_display(void *opaque)
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}
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static void blizzard_screen_dump(void *opaque, const char *filename) {
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struct blizzard_s *s = (struct blizzard_s *) opaque;
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BlizzardState *s = (BlizzardState *) opaque;
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blizzard_update_display(opaque);
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if (s && ds_get_data(s->state))
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@@ -955,7 +955,7 @@ static void blizzard_screen_dump(void *opaque, const char *filename) {
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void *s1d13745_init(qemu_irq gpio_int)
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{
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struct blizzard_s *s = (struct blizzard_s *) qemu_mallocz(sizeof(*s));
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BlizzardState *s = (BlizzardState *) qemu_mallocz(sizeof(*s));
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s->fb = qemu_malloc(0x180000);
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@@ -28,9 +28,14 @@
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//#define DEBUG
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struct cbus_slave_s;
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struct cbus_priv_s {
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struct cbus_s cbus;
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typedef struct {
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void *opaque;
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void (*io)(void *opaque, int rw, int reg, uint16_t *val);
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int addr;
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} CBusSlave;
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typedef struct {
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CBus cbus;
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int sel;
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int dat;
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@@ -48,16 +53,10 @@ struct cbus_priv_s {
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cbus_value,
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} cycle;
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struct cbus_slave_s *slave[8];
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};
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CBusSlave *slave[8];
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} CBusPriv;
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struct cbus_slave_s {
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void *opaque;
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void (*io)(void *opaque, int rw, int reg, uint16_t *val);
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int addr;
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};
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static void cbus_io(struct cbus_priv_s *s)
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static void cbus_io(CBusPriv *s)
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{
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if (s->slave[s->addr])
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s->slave[s->addr]->io(s->slave[s->addr]->opaque,
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@@ -66,7 +65,7 @@ static void cbus_io(struct cbus_priv_s *s)
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hw_error("%s: bad slave address %i\n", __FUNCTION__, s->addr);
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}
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static void cbus_cycle(struct cbus_priv_s *s)
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static void cbus_cycle(CBusPriv *s)
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{
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switch (s->cycle) {
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case cbus_address:
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@@ -97,7 +96,7 @@ static void cbus_cycle(struct cbus_priv_s *s)
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static void cbus_clk(void *opaque, int line, int level)
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{
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struct cbus_priv_s *s = (struct cbus_priv_s *) opaque;
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CBusPriv *s = (CBusPriv *) opaque;
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if (!s->sel && level && !s->clk) {
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if (s->dir)
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@@ -114,14 +113,14 @@ static void cbus_clk(void *opaque, int line, int level)
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static void cbus_dat(void *opaque, int line, int level)
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{
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struct cbus_priv_s *s = (struct cbus_priv_s *) opaque;
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CBusPriv *s = (CBusPriv *) opaque;
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s->dat = level;
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}
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static void cbus_sel(void *opaque, int line, int level)
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{
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struct cbus_priv_s *s = (struct cbus_priv_s *) opaque;
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CBusPriv *s = (CBusPriv *) opaque;
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if (!level) {
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s->dir = 1;
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@@ -132,9 +131,9 @@ static void cbus_sel(void *opaque, int line, int level)
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s->sel = level;
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}
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struct cbus_s *cbus_init(qemu_irq dat)
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CBus *cbus_init(qemu_irq dat)
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{
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struct cbus_priv_s *s = (struct cbus_priv_s *) qemu_mallocz(sizeof(*s));
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CBusPriv *s = (CBusPriv *) qemu_mallocz(sizeof(*s));
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s->dat_out = dat;
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s->cbus.clk = qemu_allocate_irqs(cbus_clk, s, 1)[0];
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@@ -148,16 +147,16 @@ struct cbus_s *cbus_init(qemu_irq dat)
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return &s->cbus;
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}
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void cbus_attach(struct cbus_s *bus, void *slave_opaque)
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void cbus_attach(CBus *bus, void *slave_opaque)
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{
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struct cbus_slave_s *slave = (struct cbus_slave_s *) slave_opaque;
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struct cbus_priv_s *s = (struct cbus_priv_s *) bus;
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CBusSlave *slave = (CBusSlave *) slave_opaque;
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CBusPriv *s = (CBusPriv *) bus;
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s->slave[slave->addr] = slave;
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}
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/* Retu/Vilma */
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struct cbus_retu_s {
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typedef struct {
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uint16_t irqst;
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uint16_t irqen;
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uint16_t cc[2];
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@@ -172,10 +171,10 @@ struct cbus_retu_s {
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int is_vilma;
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qemu_irq irq;
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struct cbus_slave_s cbus;
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};
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CBusSlave cbus;
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} CBusRetu;
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static void retu_interrupt_update(struct cbus_retu_s *s)
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static void retu_interrupt_update(CBusRetu *s)
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{
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qemu_set_irq(s->irq, s->irqst & ~s->irqen);
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}
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@@ -237,7 +236,7 @@ enum {
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retu_adc_self_temp = 13, /* RETU temperature */
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};
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static inline uint16_t retu_read(struct cbus_retu_s *s, int reg)
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static inline uint16_t retu_read(CBusRetu *s, int reg)
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{
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#ifdef DEBUG
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printf("RETU read at %02x\n", reg);
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@@ -304,7 +303,7 @@ static inline uint16_t retu_read(struct cbus_retu_s *s, int reg)
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}
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}
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static inline void retu_write(struct cbus_retu_s *s, int reg, uint16_t val)
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static inline void retu_write(CBusRetu *s, int reg, uint16_t val)
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{
|
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#ifdef DEBUG
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printf("RETU write of %04x at %02x\n", val, reg);
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@@ -379,7 +378,7 @@ static inline void retu_write(struct cbus_retu_s *s, int reg, uint16_t val)
|
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static void retu_io(void *opaque, int rw, int reg, uint16_t *val)
|
||||
{
|
||||
struct cbus_retu_s *s = (struct cbus_retu_s *) opaque;
|
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CBusRetu *s = (CBusRetu *) opaque;
|
||||
|
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if (rw)
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*val = retu_read(s, reg);
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@@ -389,7 +388,7 @@ static void retu_io(void *opaque, int rw, int reg, uint16_t *val)
|
||||
|
||||
void *retu_init(qemu_irq irq, int vilma)
|
||||
{
|
||||
struct cbus_retu_s *s = (struct cbus_retu_s *) qemu_mallocz(sizeof(*s));
|
||||
CBusRetu *s = (CBusRetu *) qemu_mallocz(sizeof(*s));
|
||||
|
||||
s->irq = irq;
|
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s->irqen = 0xffff;
|
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@@ -419,8 +418,8 @@ void *retu_init(qemu_irq irq, int vilma)
|
||||
|
||||
void retu_key_event(void *retu, int state)
|
||||
{
|
||||
struct cbus_slave_s *slave = (struct cbus_slave_s *) retu;
|
||||
struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque;
|
||||
CBusSlave *slave = (CBusSlave *) retu;
|
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CBusRetu *s = (CBusRetu *) slave->opaque;
|
||||
|
||||
s->irqst |= 1 << retu_int_pwr;
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retu_interrupt_update(s);
|
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@@ -434,8 +433,8 @@ void retu_key_event(void *retu, int state)
|
||||
#if 0
|
||||
static void retu_head_event(void *retu, int state)
|
||||
{
|
||||
struct cbus_slave_s *slave = (struct cbus_slave_s *) retu;
|
||||
struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque;
|
||||
CBusSlave *slave = (CBusSlave *) retu;
|
||||
CBusRetu *s = (CBusRetu *) slave->opaque;
|
||||
|
||||
if ((s->cc[0] & 0x500) == 0x500) { /* TODO: Which bits? */
|
||||
/* TODO: reissue the interrupt every 100ms or so. */
|
||||
@@ -451,8 +450,8 @@ static void retu_head_event(void *retu, int state)
|
||||
|
||||
static void retu_hook_event(void *retu, int state)
|
||||
{
|
||||
struct cbus_slave_s *slave = (struct cbus_slave_s *) retu;
|
||||
struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque;
|
||||
CBusSlave *slave = (CBusSlave *) retu;
|
||||
CBusRetu *s = (CBusRetu *) slave->opaque;
|
||||
|
||||
if ((s->cc[0] & 0x500) == 0x500) {
|
||||
/* TODO: reissue the interrupt every 100ms or so. */
|
||||
@@ -468,7 +467,7 @@ static void retu_hook_event(void *retu, int state)
|
||||
#endif
|
||||
|
||||
/* Tahvo/Betty */
|
||||
struct cbus_tahvo_s {
|
||||
typedef struct {
|
||||
uint16_t irqst;
|
||||
uint16_t irqen;
|
||||
uint8_t charger;
|
||||
@@ -478,10 +477,10 @@ struct cbus_tahvo_s {
|
||||
|
||||
int is_betty;
|
||||
qemu_irq irq;
|
||||
struct cbus_slave_s cbus;
|
||||
};
|
||||
CBusSlave cbus;
|
||||
} CBusTahvo;
|
||||
|
||||
static void tahvo_interrupt_update(struct cbus_tahvo_s *s)
|
||||
static void tahvo_interrupt_update(CBusTahvo *s)
|
||||
{
|
||||
qemu_set_irq(s->irq, s->irqst & ~s->irqen);
|
||||
}
|
||||
@@ -501,7 +500,7 @@ static void tahvo_interrupt_update(struct cbus_tahvo_s *s)
|
||||
#define TAHVO_REG_NOPR 0x0c /* (RW) Number of periods */
|
||||
#define TAHVO_REG_FRR 0x0d /* (RO) FR */
|
||||
|
||||
static inline uint16_t tahvo_read(struct cbus_tahvo_s *s, int reg)
|
||||
static inline uint16_t tahvo_read(CBusTahvo *s, int reg)
|
||||
{
|
||||
#ifdef DEBUG
|
||||
printf("TAHVO read at %02x\n", reg);
|
||||
@@ -543,7 +542,7 @@ static inline uint16_t tahvo_read(struct cbus_tahvo_s *s, int reg)
|
||||
}
|
||||
}
|
||||
|
||||
static inline void tahvo_write(struct cbus_tahvo_s *s, int reg, uint16_t val)
|
||||
static inline void tahvo_write(CBusTahvo *s, int reg, uint16_t val)
|
||||
{
|
||||
#ifdef DEBUG
|
||||
printf("TAHVO write of %04x at %02x\n", val, reg);
|
||||
@@ -595,7 +594,7 @@ static inline void tahvo_write(struct cbus_tahvo_s *s, int reg, uint16_t val)
|
||||
|
||||
static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val)
|
||||
{
|
||||
struct cbus_tahvo_s *s = (struct cbus_tahvo_s *) opaque;
|
||||
CBusTahvo *s = (CBusTahvo *) opaque;
|
||||
|
||||
if (rw)
|
||||
*val = tahvo_read(s, reg);
|
||||
@@ -605,7 +604,7 @@ static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val)
|
||||
|
||||
void *tahvo_init(qemu_irq irq, int betty)
|
||||
{
|
||||
struct cbus_tahvo_s *s = (struct cbus_tahvo_s *) qemu_mallocz(sizeof(*s));
|
||||
CBusTahvo *s = (CBusTahvo *) qemu_mallocz(sizeof(*s));
|
||||
|
||||
s->irq = irq;
|
||||
s->irqen = 0xffff;
|
||||
|
||||
+23
-25
@@ -11,27 +11,25 @@ int ssd0323_xfer_ssi(void *opaque, int data);
|
||||
void *ssd0323_init(qemu_irq *cmd_p);
|
||||
|
||||
/* ads7846.c */
|
||||
struct ads7846_state_s;
|
||||
typedef struct ADS7846State ADS7846State;
|
||||
uint32_t ads7846_read(void *opaque);
|
||||
void ads7846_write(void *opaque, uint32_t value);
|
||||
struct ads7846_state_s *ads7846_init(qemu_irq penirq);
|
||||
ADS7846State *ads7846_init(qemu_irq penirq);
|
||||
|
||||
/* tsc210x.c */
|
||||
struct uwire_slave_s;
|
||||
struct mouse_transform_info_s;
|
||||
struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
|
||||
struct uwire_slave_s *tsc2301_init(qemu_irq penirq, qemu_irq kbirq,
|
||||
uWireSlave *tsc2102_init(qemu_irq pint, AudioState *audio);
|
||||
uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq,
|
||||
qemu_irq dav, AudioState *audio);
|
||||
struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
|
||||
I2SCodec *tsc210x_codec(uWireSlave *chip);
|
||||
uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);
|
||||
void tsc210x_set_transform(struct uwire_slave_s *chip,
|
||||
struct mouse_transform_info_s *info);
|
||||
void tsc210x_key_event(struct uwire_slave_s *chip, int key, int down);
|
||||
void tsc210x_set_transform(uWireSlave *chip,
|
||||
MouseTransformInfo *info);
|
||||
void tsc210x_key_event(uWireSlave *chip, int key, int down);
|
||||
|
||||
/* tsc2005.c */
|
||||
void *tsc2005_init(qemu_irq pintdav);
|
||||
uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
|
||||
void tsc2005_set_transform(void *opaque, struct mouse_transform_info_s *info);
|
||||
void tsc2005_set_transform(void *opaque, MouseTransformInfo *info);
|
||||
|
||||
/* stellaris_input.c */
|
||||
void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
|
||||
@@ -44,13 +42,13 @@ void s1d13745_write_block(void *opaque, int dc,
|
||||
uint16_t s1d13745_read(void *opaque, int dc);
|
||||
|
||||
/* cbus.c */
|
||||
struct cbus_s {
|
||||
typedef struct {
|
||||
qemu_irq clk;
|
||||
qemu_irq dat;
|
||||
qemu_irq sel;
|
||||
};
|
||||
struct cbus_s *cbus_init(qemu_irq dat_out);
|
||||
void cbus_attach(struct cbus_s *bus, void *slave_opaque);
|
||||
} CBus;
|
||||
CBus *cbus_init(qemu_irq dat_out);
|
||||
void cbus_attach(CBus *bus, void *slave_opaque);
|
||||
|
||||
void *retu_init(qemu_irq irq, int vilma);
|
||||
void *tahvo_init(qemu_irq irq, int betty);
|
||||
@@ -58,20 +56,20 @@ void *tahvo_init(qemu_irq irq, int betty);
|
||||
void retu_key_event(void *retu, int state);
|
||||
|
||||
/* tusb6010.c */
|
||||
struct tusb_s;
|
||||
struct tusb_s *tusb6010_init(qemu_irq intr);
|
||||
int tusb6010_sync_io(struct tusb_s *s);
|
||||
int tusb6010_async_io(struct tusb_s *s);
|
||||
void tusb6010_power(struct tusb_s *s, int on);
|
||||
typedef struct TUSBState TUSBState;
|
||||
TUSBState *tusb6010_init(qemu_irq intr);
|
||||
int tusb6010_sync_io(TUSBState *s);
|
||||
int tusb6010_async_io(TUSBState *s);
|
||||
void tusb6010_power(TUSBState *s, int on);
|
||||
|
||||
/* tc6393xb.c */
|
||||
struct tc6393xb_s;
|
||||
typedef struct TC6393xbState TC6393xbState;
|
||||
#define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */
|
||||
struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq);
|
||||
void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
|
||||
TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq);
|
||||
void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
|
||||
qemu_irq handler);
|
||||
qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s);
|
||||
qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s);
|
||||
qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s);
|
||||
qemu_irq tc6393xb_l3v_get(TC6393xbState *s);
|
||||
|
||||
/* sm501.c */
|
||||
void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq,
|
||||
|
||||
@@ -50,7 +50,7 @@ static const uint8_t nand_ecc_precalc_table[] = {
|
||||
};
|
||||
|
||||
/* Update ECC parity count. */
|
||||
uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample)
|
||||
uint8_t ecc_digest(ECCState *s, uint8_t sample)
|
||||
{
|
||||
uint8_t idx = nand_ecc_precalc_table[sample];
|
||||
|
||||
@@ -65,7 +65,7 @@ uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample)
|
||||
}
|
||||
|
||||
/* Reinitialise the counters. */
|
||||
void ecc_reset(struct ecc_state_s *s)
|
||||
void ecc_reset(ECCState *s)
|
||||
{
|
||||
s->lp[0] = 0x0000;
|
||||
s->lp[1] = 0x0000;
|
||||
@@ -74,7 +74,7 @@ void ecc_reset(struct ecc_state_s *s)
|
||||
}
|
||||
|
||||
/* Save/restore */
|
||||
void ecc_put(QEMUFile *f, struct ecc_state_s *s)
|
||||
void ecc_put(QEMUFile *f, ECCState *s)
|
||||
{
|
||||
qemu_put_8s(f, &s->cp);
|
||||
qemu_put_be16s(f, &s->lp[0]);
|
||||
@@ -82,7 +82,7 @@ void ecc_put(QEMUFile *f, struct ecc_state_s *s)
|
||||
qemu_put_be16s(f, &s->count);
|
||||
}
|
||||
|
||||
void ecc_get(QEMUFile *f, struct ecc_state_s *s)
|
||||
void ecc_get(QEMUFile *f, ECCState *s)
|
||||
{
|
||||
qemu_get_8s(f, &s->cp);
|
||||
qemu_get_be16s(f, &s->lp[0]);
|
||||
|
||||
+13
-13
@@ -17,14 +17,14 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
|
||||
uint16_t unlock_addr0, uint16_t unlock_addr1);
|
||||
|
||||
/* nand.c */
|
||||
struct nand_flash_s;
|
||||
struct nand_flash_s *nand_init(int manf_id, int chip_id);
|
||||
void nand_done(struct nand_flash_s *s);
|
||||
void nand_setpins(struct nand_flash_s *s,
|
||||
typedef struct NANDFlashState NANDFlashState;
|
||||
NANDFlashState *nand_init(int manf_id, int chip_id);
|
||||
void nand_done(NANDFlashState *s);
|
||||
void nand_setpins(NANDFlashState *s,
|
||||
int cle, int ale, int ce, int wp, int gnd);
|
||||
void nand_getpins(struct nand_flash_s *s, int *rb);
|
||||
void nand_setio(struct nand_flash_s *s, uint8_t value);
|
||||
uint8_t nand_getio(struct nand_flash_s *s);
|
||||
void nand_getpins(NANDFlashState *s, int *rb);
|
||||
void nand_setio(NANDFlashState *s, uint8_t value);
|
||||
uint8_t nand_getio(NANDFlashState *s);
|
||||
|
||||
#define NAND_MFR_TOSHIBA 0x98
|
||||
#define NAND_MFR_SAMSUNG 0xec
|
||||
@@ -42,13 +42,13 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
|
||||
void *onenand_raw_otp(void *opaque);
|
||||
|
||||
/* ecc.c */
|
||||
struct ecc_state_s {
|
||||
typedef struct {
|
||||
uint8_t cp; /* Column parity */
|
||||
uint16_t lp[2]; /* Line parity */
|
||||
uint16_t count;
|
||||
};
|
||||
} ECCState;
|
||||
|
||||
uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
|
||||
void ecc_reset(struct ecc_state_s *s);
|
||||
void ecc_put(QEMUFile *f, struct ecc_state_s *s);
|
||||
void ecc_get(QEMUFile *f, struct ecc_state_s *s);
|
||||
uint8_t ecc_digest(ECCState *s, uint8_t sample);
|
||||
void ecc_reset(ECCState *s);
|
||||
void ecc_put(QEMUFile *f, ECCState *s);
|
||||
void ecc_get(QEMUFile *f, ECCState *s);
|
||||
|
||||
+2
-2
@@ -46,7 +46,7 @@ static void connex_init(ram_addr_t ram_size, int vga_ram_size,
|
||||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
struct pxa2xx_state_s *cpu;
|
||||
PXA2xxState *cpu;
|
||||
int index;
|
||||
|
||||
uint32_t connex_rom = 0x01000000;
|
||||
@@ -80,7 +80,7 @@ static void verdex_init(ram_addr_t ram_size, int vga_ram_size,
|
||||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
struct pxa2xx_state_s *cpu;
|
||||
PXA2xxState *cpu;
|
||||
int index;
|
||||
|
||||
uint32_t verdex_rom = 0x02000000;
|
||||
|
||||
@@ -46,12 +46,12 @@ void i2c_slave_save(QEMUFile *f, i2c_slave *dev);
|
||||
void i2c_slave_load(QEMUFile *f, i2c_slave *dev);
|
||||
|
||||
/* max111x.c */
|
||||
struct max111x_s;
|
||||
typedef struct MAX111xState MAX111xState;
|
||||
uint32_t max111x_read(void *opaque);
|
||||
void max111x_write(void *opaque, uint32_t value);
|
||||
struct max111x_s *max1110_init(qemu_irq cb);
|
||||
struct max111x_s *max1111_init(qemu_irq cb);
|
||||
void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
|
||||
MAX111xState *max1110_init(qemu_irq cb);
|
||||
MAX111xState *max1111_init(qemu_irq cb);
|
||||
void max111x_set_input(MAX111xState *s, int line, uint8_t value);
|
||||
|
||||
/* max7310.c */
|
||||
i2c_slave *max7310_init(i2c_bus *bus);
|
||||
|
||||
@@ -3859,9 +3859,9 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
|
||||
#define METADATA_SIZE 0x20
|
||||
|
||||
/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
|
||||
struct md_s {
|
||||
typedef struct {
|
||||
IDEState ide[2];
|
||||
struct pcmcia_card_s card;
|
||||
PCMCIACardState card;
|
||||
uint32_t attr_base;
|
||||
uint32_t io_base;
|
||||
|
||||
@@ -3873,7 +3873,7 @@ struct md_s {
|
||||
uint8_t ctrl;
|
||||
uint16_t io;
|
||||
int cycle;
|
||||
};
|
||||
} MicroDriveState;
|
||||
|
||||
/* Register bitfields */
|
||||
enum md_opt {
|
||||
@@ -3902,7 +3902,7 @@ enum md_ctrl {
|
||||
CTRL_SRST = 0x04,
|
||||
};
|
||||
|
||||
static inline void md_interrupt_update(struct md_s *s)
|
||||
static inline void md_interrupt_update(MicroDriveState *s)
|
||||
{
|
||||
if (!s->card.slot)
|
||||
return;
|
||||
@@ -3915,7 +3915,7 @@ static inline void md_interrupt_update(struct md_s *s)
|
||||
|
||||
static void md_set_irq(void *opaque, int irq, int level)
|
||||
{
|
||||
struct md_s *s = (struct md_s *) opaque;
|
||||
MicroDriveState *s = (MicroDriveState *) opaque;
|
||||
if (level)
|
||||
s->stat |= STAT_INT;
|
||||
else
|
||||
@@ -3924,7 +3924,7 @@ static void md_set_irq(void *opaque, int irq, int level)
|
||||
md_interrupt_update(s);
|
||||
}
|
||||
|
||||
static void md_reset(struct md_s *s)
|
||||
static void md_reset(MicroDriveState *s)
|
||||
{
|
||||
s->opt = OPT_MODE_MMAP;
|
||||
s->stat = 0;
|
||||
@@ -3936,7 +3936,7 @@ static void md_reset(struct md_s *s)
|
||||
|
||||
static uint8_t md_attr_read(void *opaque, uint32_t at)
|
||||
{
|
||||
struct md_s *s = (struct md_s *) opaque;
|
||||
MicroDriveState *s = (MicroDriveState *) opaque;
|
||||
if (at < s->attr_base) {
|
||||
if (at < s->card.cis_len)
|
||||
return s->card.cis[at];
|
||||
@@ -3969,7 +3969,7 @@ static uint8_t md_attr_read(void *opaque, uint32_t at)
|
||||
|
||||
static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
|
||||
{
|
||||
struct md_s *s = (struct md_s *) opaque;
|
||||
MicroDriveState *s = (MicroDriveState *) opaque;
|
||||
at -= s->attr_base;
|
||||
|
||||
switch (at) {
|
||||
@@ -4000,7 +4000,7 @@ static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
|
||||
|
||||
static uint16_t md_common_read(void *opaque, uint32_t at)
|
||||
{
|
||||
struct md_s *s = (struct md_s *) opaque;
|
||||
MicroDriveState *s = (MicroDriveState *) opaque;
|
||||
uint16_t ret;
|
||||
at -= s->io_base;
|
||||
|
||||
@@ -4059,7 +4059,7 @@ static uint16_t md_common_read(void *opaque, uint32_t at)
|
||||
|
||||
static void md_common_write(void *opaque, uint32_t at, uint16_t value)
|
||||
{
|
||||
struct md_s *s = (struct md_s *) opaque;
|
||||
MicroDriveState *s = (MicroDriveState *) opaque;
|
||||
at -= s->io_base;
|
||||
|
||||
switch (s->opt & OPT_MODE) {
|
||||
@@ -4120,7 +4120,7 @@ static void md_common_write(void *opaque, uint32_t at, uint16_t value)
|
||||
|
||||
static void md_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
struct md_s *s = (struct md_s *) opaque;
|
||||
MicroDriveState *s = (MicroDriveState *) opaque;
|
||||
int i;
|
||||
uint8_t drive1_selected;
|
||||
|
||||
@@ -4142,7 +4142,7 @@ static void md_save(QEMUFile *f, void *opaque)
|
||||
|
||||
static int md_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
struct md_s *s = (struct md_s *) opaque;
|
||||
MicroDriveState *s = (MicroDriveState *) opaque;
|
||||
int i;
|
||||
uint8_t drive1_selected;
|
||||
|
||||
@@ -4351,7 +4351,7 @@ static const uint8_t dscm1xxxx_cis[0x14a] = {
|
||||
|
||||
static int dscm1xxxx_attach(void *opaque)
|
||||
{
|
||||
struct md_s *md = (struct md_s *) opaque;
|
||||
MicroDriveState *md = (MicroDriveState *) opaque;
|
||||
md->card.attr_read = md_attr_read;
|
||||
md->card.attr_write = md_attr_write;
|
||||
md->card.common_read = md_common_read;
|
||||
@@ -4371,14 +4371,14 @@ static int dscm1xxxx_attach(void *opaque)
|
||||
|
||||
static int dscm1xxxx_detach(void *opaque)
|
||||
{
|
||||
struct md_s *md = (struct md_s *) opaque;
|
||||
MicroDriveState *md = (MicroDriveState *) opaque;
|
||||
md_reset(md);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv)
|
||||
PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv)
|
||||
{
|
||||
struct md_s *md = (struct md_s *) qemu_mallocz(sizeof(struct md_s));
|
||||
MicroDriveState *md = (MicroDriveState *) qemu_mallocz(sizeof(MicroDriveState));
|
||||
md->card.state = md;
|
||||
md->card.attach = dscm1xxxx_attach;
|
||||
md->card.detach = dscm1xxxx_detach;
|
||||
|
||||
+19
-19
@@ -24,7 +24,7 @@
|
||||
#include "qemu-timer.h"
|
||||
#include "console.h"
|
||||
|
||||
struct lm_kbd_s {
|
||||
typedef struct {
|
||||
i2c_slave i2c;
|
||||
int i2c_dir;
|
||||
int i2c_cycle;
|
||||
@@ -66,7 +66,7 @@ struct lm_kbd_s {
|
||||
uint8_t addr[3];
|
||||
QEMUTimer *tm[3];
|
||||
} pwm;
|
||||
};
|
||||
} LM823KbdState;
|
||||
|
||||
#define INT_KEYPAD (1 << 0)
|
||||
#define INT_ERROR (1 << 3)
|
||||
@@ -78,16 +78,16 @@ struct lm_kbd_s {
|
||||
#define ERR_KEYOVR (1 << 2)
|
||||
#define ERR_FIFOOVR (1 << 6)
|
||||
|
||||
static void lm_kbd_irq_update(struct lm_kbd_s *s)
|
||||
static void lm_kbd_irq_update(LM823KbdState *s)
|
||||
{
|
||||
qemu_set_irq(s->nirq, !s->status);
|
||||
}
|
||||
|
||||
static void lm_kbd_gpio_update(struct lm_kbd_s *s)
|
||||
static void lm_kbd_gpio_update(LM823KbdState *s)
|
||||
{
|
||||
}
|
||||
|
||||
static void lm_kbd_reset(struct lm_kbd_s *s)
|
||||
static void lm_kbd_reset(LM823KbdState *s)
|
||||
{
|
||||
s->config = 0x80;
|
||||
s->status = INT_NOINIT;
|
||||
@@ -100,18 +100,18 @@ static void lm_kbd_reset(struct lm_kbd_s *s)
|
||||
lm_kbd_gpio_update(s);
|
||||
}
|
||||
|
||||
static void lm_kbd_error(struct lm_kbd_s *s, int err)
|
||||
static void lm_kbd_error(LM823KbdState *s, int err)
|
||||
{
|
||||
s->error |= err;
|
||||
s->status |= INT_ERROR;
|
||||
lm_kbd_irq_update(s);
|
||||
}
|
||||
|
||||
static void lm_kbd_pwm_tick(struct lm_kbd_s *s, int line)
|
||||
static void lm_kbd_pwm_tick(LM823KbdState *s, int line)
|
||||
{
|
||||
}
|
||||
|
||||
static void lm_kbd_pwm_start(struct lm_kbd_s *s, int line)
|
||||
static void lm_kbd_pwm_start(LM823KbdState *s, int line)
|
||||
{
|
||||
lm_kbd_pwm_tick(s, line);
|
||||
}
|
||||
@@ -158,7 +158,7 @@ enum {
|
||||
#define LM832x_MAX_KPX 8
|
||||
#define LM832x_MAX_KPY 12
|
||||
|
||||
static uint8_t lm_kbd_read(struct lm_kbd_s *s, int reg, int byte)
|
||||
static uint8_t lm_kbd_read(LM823KbdState *s, int reg, int byte)
|
||||
{
|
||||
int ret;
|
||||
|
||||
@@ -239,7 +239,7 @@ static uint8_t lm_kbd_read(struct lm_kbd_s *s, int reg, int byte)
|
||||
return ret >> (byte << 3);
|
||||
}
|
||||
|
||||
static void lm_kbd_write(struct lm_kbd_s *s, int reg, int byte, uint8_t value)
|
||||
static void lm_kbd_write(LM823KbdState *s, int reg, int byte, uint8_t value)
|
||||
{
|
||||
switch (reg) {
|
||||
case LM832x_CMD_WRITE_CFG:
|
||||
@@ -378,7 +378,7 @@ static void lm_kbd_write(struct lm_kbd_s *s, int reg, int byte, uint8_t value)
|
||||
|
||||
static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event)
|
||||
{
|
||||
struct lm_kbd_s *s = (struct lm_kbd_s *) i2c;
|
||||
LM823KbdState *s = (LM823KbdState *) i2c;
|
||||
|
||||
switch (event) {
|
||||
case I2C_START_RECV:
|
||||
@@ -394,14 +394,14 @@ static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event)
|
||||
|
||||
static int lm_i2c_rx(i2c_slave *i2c)
|
||||
{
|
||||
struct lm_kbd_s *s = (struct lm_kbd_s *) i2c;
|
||||
LM823KbdState *s = (LM823KbdState *) i2c;
|
||||
|
||||
return lm_kbd_read(s, s->reg, s->i2c_cycle ++);
|
||||
}
|
||||
|
||||
static int lm_i2c_tx(i2c_slave *i2c, uint8_t data)
|
||||
{
|
||||
struct lm_kbd_s *s = (struct lm_kbd_s *) i2c;
|
||||
LM823KbdState *s = (LM823KbdState *) i2c;
|
||||
|
||||
if (!s->i2c_cycle)
|
||||
s->reg = data;
|
||||
@@ -414,7 +414,7 @@ static int lm_i2c_tx(i2c_slave *i2c, uint8_t data)
|
||||
|
||||
static void lm_kbd_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
struct lm_kbd_s *s = (struct lm_kbd_s *) opaque;
|
||||
LM823KbdState *s = (LM823KbdState *) opaque;
|
||||
int i;
|
||||
|
||||
i2c_slave_save(f, &s->i2c);
|
||||
@@ -450,7 +450,7 @@ static void lm_kbd_save(QEMUFile *f, void *opaque)
|
||||
|
||||
static int lm_kbd_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
struct lm_kbd_s *s = (struct lm_kbd_s *) opaque;
|
||||
LM823KbdState *s = (LM823KbdState *) opaque;
|
||||
int i;
|
||||
|
||||
i2c_slave_load(f, &s->i2c);
|
||||
@@ -489,11 +489,11 @@ static int lm_kbd_load(QEMUFile *f, void *opaque, int version_id)
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq)
|
||||
i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq)
|
||||
{
|
||||
struct lm_kbd_s *s;
|
||||
LM823KbdState *s;
|
||||
|
||||
s = (struct lm_kbd_s *) i2c_slave_init(bus, 0, sizeof(struct lm_kbd_s));
|
||||
s = (LM823KbdState *) i2c_slave_init(bus, 0, sizeof(LM823KbdState));
|
||||
s->model = 0x8323;
|
||||
s->pwm.tm[0] = qemu_new_timer(vm_clock, lm_kbd_pwm0_tick, s);
|
||||
s->pwm.tm[1] = qemu_new_timer(vm_clock, lm_kbd_pwm1_tick, s);
|
||||
@@ -514,7 +514,7 @@ struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq)
|
||||
|
||||
void lm832x_key_event(struct i2c_slave *i2c, int key, int state)
|
||||
{
|
||||
struct lm_kbd_s *s = (struct lm_kbd_s *) i2c;
|
||||
LM823KbdState *s = (LM823KbdState *) i2c;
|
||||
|
||||
if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR))
|
||||
return;
|
||||
|
||||
+1
-1
@@ -75,7 +75,7 @@ static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size,
|
||||
{
|
||||
uint32_t sector_len = 256 * 1024;
|
||||
target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
|
||||
struct pxa2xx_state_s *cpu;
|
||||
PXA2xxState *cpu;
|
||||
qemu_irq *mst_irq;
|
||||
int i, index;
|
||||
|
||||
|
||||
+1
-1
@@ -33,6 +33,6 @@
|
||||
#define S1_IRQ 15
|
||||
|
||||
extern qemu_irq
|
||||
*mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq);
|
||||
*mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq);
|
||||
|
||||
#endif /* __MAINSTONE_H__ */
|
||||
|
||||
+15
-15
@@ -10,7 +10,7 @@
|
||||
#include "hw.h"
|
||||
#include "i2c.h"
|
||||
|
||||
struct max111x_s {
|
||||
struct MAX111xState {
|
||||
qemu_irq interrupt;
|
||||
uint8_t tb1, rb2, rb3;
|
||||
int cycle;
|
||||
@@ -36,7 +36,7 @@ struct max111x_s {
|
||||
|
||||
uint32_t max111x_read(void *opaque)
|
||||
{
|
||||
struct max111x_s *s = (struct max111x_s *) opaque;
|
||||
MAX111xState *s = (MAX111xState *) opaque;
|
||||
|
||||
if (!s->tb1)
|
||||
return 0;
|
||||
@@ -54,7 +54,7 @@ uint32_t max111x_read(void *opaque)
|
||||
/* Interpret a control-byte */
|
||||
void max111x_write(void *opaque, uint32_t value)
|
||||
{
|
||||
struct max111x_s *s = (struct max111x_s *) opaque;
|
||||
MAX111xState *s = (MAX111xState *) opaque;
|
||||
int measure, chan;
|
||||
|
||||
/* Ignore the value if START bit is zero */
|
||||
@@ -92,7 +92,7 @@ void max111x_write(void *opaque, uint32_t value)
|
||||
|
||||
static void max111x_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
struct max111x_s *s = (struct max111x_s *) opaque;
|
||||
MAX111xState *s = (MAX111xState *) opaque;
|
||||
int i;
|
||||
|
||||
qemu_put_8s(f, &s->tb1);
|
||||
@@ -106,7 +106,7 @@ static void max111x_save(QEMUFile *f, void *opaque)
|
||||
|
||||
static int max111x_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
struct max111x_s *s = (struct max111x_s *) opaque;
|
||||
MAX111xState *s = (MAX111xState *) opaque;
|
||||
int i;
|
||||
|
||||
qemu_get_8s(f, &s->tb1);
|
||||
@@ -121,12 +121,12 @@ static int max111x_load(QEMUFile *f, void *opaque, int version_id)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct max111x_s *max111x_init(qemu_irq cb)
|
||||
static MAX111xState *max111x_init(qemu_irq cb)
|
||||
{
|
||||
struct max111x_s *s;
|
||||
s = (struct max111x_s *)
|
||||
qemu_mallocz(sizeof(struct max111x_s));
|
||||
memset(s, 0, sizeof(struct max111x_s));
|
||||
MAX111xState *s;
|
||||
s = (MAX111xState *)
|
||||
qemu_mallocz(sizeof(MAX111xState));
|
||||
memset(s, 0, sizeof(MAX111xState));
|
||||
|
||||
s->interrupt = cb;
|
||||
|
||||
@@ -146,21 +146,21 @@ static struct max111x_s *max111x_init(qemu_irq cb)
|
||||
return s;
|
||||
}
|
||||
|
||||
struct max111x_s *max1110_init(qemu_irq cb)
|
||||
MAX111xState *max1110_init(qemu_irq cb)
|
||||
{
|
||||
struct max111x_s *s = max111x_init(cb);
|
||||
MAX111xState *s = max111x_init(cb);
|
||||
s->inputs = 8;
|
||||
return s;
|
||||
}
|
||||
|
||||
struct max111x_s *max1111_init(qemu_irq cb)
|
||||
MAX111xState *max1111_init(qemu_irq cb)
|
||||
{
|
||||
struct max111x_s *s = max111x_init(cb);
|
||||
MAX111xState *s = max111x_init(cb);
|
||||
s->inputs = 4;
|
||||
return s;
|
||||
}
|
||||
|
||||
void max111x_set_input(struct max111x_s *s, int line, uint8_t value)
|
||||
void max111x_set_input(MAX111xState *s, int line, uint8_t value)
|
||||
{
|
||||
if (line >= s->inputs) {
|
||||
printf("%s: There's no input %i\n", __FUNCTION__, line);
|
||||
|
||||
+14
-14
@@ -10,7 +10,7 @@
|
||||
#include "hw.h"
|
||||
#include "i2c.h"
|
||||
|
||||
struct max7310_s {
|
||||
typedef struct {
|
||||
i2c_slave i2c;
|
||||
int i2c_command_byte;
|
||||
int len;
|
||||
@@ -22,11 +22,11 @@ struct max7310_s {
|
||||
uint8_t command;
|
||||
qemu_irq handler[8];
|
||||
qemu_irq *gpio_in;
|
||||
};
|
||||
} MAX7310State;
|
||||
|
||||
void max7310_reset(i2c_slave *i2c)
|
||||
{
|
||||
struct max7310_s *s = (struct max7310_s *) i2c;
|
||||
MAX7310State *s = (MAX7310State *) i2c;
|
||||
s->level &= s->direction;
|
||||
s->direction = 0xff;
|
||||
s->polarity = 0xf0;
|
||||
@@ -36,7 +36,7 @@ void max7310_reset(i2c_slave *i2c)
|
||||
|
||||
static int max7310_rx(i2c_slave *i2c)
|
||||
{
|
||||
struct max7310_s *s = (struct max7310_s *) i2c;
|
||||
MAX7310State *s = (MAX7310State *) i2c;
|
||||
|
||||
switch (s->command) {
|
||||
case 0x00: /* Input port */
|
||||
@@ -71,7 +71,7 @@ static int max7310_rx(i2c_slave *i2c)
|
||||
|
||||
static int max7310_tx(i2c_slave *i2c, uint8_t data)
|
||||
{
|
||||
struct max7310_s *s = (struct max7310_s *) i2c;
|
||||
MAX7310State *s = (MAX7310State *) i2c;
|
||||
uint8_t diff;
|
||||
int line;
|
||||
|
||||
@@ -126,7 +126,7 @@ static int max7310_tx(i2c_slave *i2c, uint8_t data)
|
||||
|
||||
static void max7310_event(i2c_slave *i2c, enum i2c_event event)
|
||||
{
|
||||
struct max7310_s *s = (struct max7310_s *) i2c;
|
||||
MAX7310State *s = (MAX7310State *) i2c;
|
||||
s->len = 0;
|
||||
|
||||
switch (event) {
|
||||
@@ -146,7 +146,7 @@ static void max7310_event(i2c_slave *i2c, enum i2c_event event)
|
||||
|
||||
static void max7310_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
struct max7310_s *s = (struct max7310_s *) opaque;
|
||||
MAX7310State *s = (MAX7310State *) opaque;
|
||||
|
||||
qemu_put_be32(f, s->i2c_command_byte);
|
||||
qemu_put_be32(f, s->len);
|
||||
@@ -162,7 +162,7 @@ static void max7310_save(QEMUFile *f, void *opaque)
|
||||
|
||||
static int max7310_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
struct max7310_s *s = (struct max7310_s *) opaque;
|
||||
MAX7310State *s = (MAX7310State *) opaque;
|
||||
|
||||
s->i2c_command_byte = qemu_get_be32(f);
|
||||
s->len = qemu_get_be32(f);
|
||||
@@ -179,7 +179,7 @@ static int max7310_load(QEMUFile *f, void *opaque, int version_id)
|
||||
|
||||
static void max7310_gpio_set(void *opaque, int line, int level)
|
||||
{
|
||||
struct max7310_s *s = (struct max7310_s *) opaque;
|
||||
MAX7310State *s = (MAX7310State *) opaque;
|
||||
if (line >= ARRAY_SIZE(s->handler) || line < 0)
|
||||
hw_error("bad GPIO line");
|
||||
|
||||
@@ -191,10 +191,10 @@ static void max7310_gpio_set(void *opaque, int line, int level)
|
||||
|
||||
/* MAX7310 is SMBus-compatible (can be used with only SMBus protocols),
|
||||
* but also accepts sequences that are not SMBus so return an I2C device. */
|
||||
struct i2c_slave *max7310_init(i2c_bus *bus)
|
||||
i2c_slave *max7310_init(i2c_bus *bus)
|
||||
{
|
||||
struct max7310_s *s = (struct max7310_s *)
|
||||
i2c_slave_init(bus, 0, sizeof(struct max7310_s));
|
||||
MAX7310State *s = (MAX7310State *)
|
||||
i2c_slave_init(bus, 0, sizeof(MAX7310State));
|
||||
s->i2c.event = max7310_event;
|
||||
s->i2c.recv = max7310_rx;
|
||||
s->i2c.send = max7310_tx;
|
||||
@@ -210,13 +210,13 @@ struct i2c_slave *max7310_init(i2c_bus *bus)
|
||||
|
||||
qemu_irq *max7310_gpio_in_get(i2c_slave *i2c)
|
||||
{
|
||||
struct max7310_s *s = (struct max7310_s *) i2c;
|
||||
MAX7310State *s = (MAX7310State *) i2c;
|
||||
return s->gpio_in;
|
||||
}
|
||||
|
||||
void max7310_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler)
|
||||
{
|
||||
struct max7310_s *s = (struct max7310_s *) i2c;
|
||||
MAX7310State *s = (MAX7310State *) i2c;
|
||||
if (line >= ARRAY_SIZE(s->handler) || line < 0)
|
||||
hw_error("bad GPIO line");
|
||||
|
||||
|
||||
+1
-1
@@ -216,7 +216,7 @@ mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
|
||||
return 0;
|
||||
}
|
||||
|
||||
qemu_irq *mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq)
|
||||
qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq)
|
||||
{
|
||||
mst_irq_state *s;
|
||||
int iomemtype;
|
||||
|
||||
@@ -45,7 +45,7 @@
|
||||
# define MAX_PAGE 0x800
|
||||
# define MAX_OOB 0x40
|
||||
|
||||
struct nand_flash_s {
|
||||
struct NANDFlashState {
|
||||
uint8_t manf_id, chip_id;
|
||||
int size, pages;
|
||||
int page_shift, oob_shift, erase_shift, addr_shift;
|
||||
@@ -64,9 +64,9 @@ struct nand_flash_s {
|
||||
int status;
|
||||
int offset;
|
||||
|
||||
void (*blk_write)(struct nand_flash_s *s);
|
||||
void (*blk_erase)(struct nand_flash_s *s);
|
||||
void (*blk_load)(struct nand_flash_s *s, uint32_t addr, int offset);
|
||||
void (*blk_write)(NANDFlashState *s);
|
||||
void (*blk_erase)(NANDFlashState *s);
|
||||
void (*blk_load)(NANDFlashState *s, uint32_t addr, int offset);
|
||||
};
|
||||
|
||||
# define NAND_NO_AUTOINCR 0x00000001
|
||||
@@ -106,7 +106,7 @@ struct nand_flash_s {
|
||||
# include "nand.c"
|
||||
|
||||
/* Information based on Linux drivers/mtd/nand/nand_ids.c */
|
||||
static const struct nand_info_s {
|
||||
static const struct {
|
||||
int size;
|
||||
int width;
|
||||
int page_shift;
|
||||
@@ -200,7 +200,7 @@ static const struct nand_info_s {
|
||||
[0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
|
||||
};
|
||||
|
||||
static void nand_reset(struct nand_flash_s *s)
|
||||
static void nand_reset(NANDFlashState *s)
|
||||
{
|
||||
s->cmd = NAND_CMD_READ0;
|
||||
s->addr = 0;
|
||||
@@ -210,7 +210,7 @@ static void nand_reset(struct nand_flash_s *s)
|
||||
s->status &= NAND_IOSTATUS_UNPROTCT;
|
||||
}
|
||||
|
||||
static void nand_command(struct nand_flash_s *s)
|
||||
static void nand_command(NANDFlashState *s)
|
||||
{
|
||||
switch (s->cmd) {
|
||||
case NAND_CMD_READ0:
|
||||
@@ -279,7 +279,7 @@ static void nand_command(struct nand_flash_s *s)
|
||||
|
||||
static void nand_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
struct nand_flash_s *s = (struct nand_flash_s *) opaque;
|
||||
NANDFlashState *s = (NANDFlashState *) opaque;
|
||||
qemu_put_byte(f, s->cle);
|
||||
qemu_put_byte(f, s->ale);
|
||||
qemu_put_byte(f, s->ce);
|
||||
@@ -299,7 +299,7 @@ static void nand_save(QEMUFile *f, void *opaque)
|
||||
|
||||
static int nand_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
struct nand_flash_s *s = (struct nand_flash_s *) opaque;
|
||||
NANDFlashState *s = (NANDFlashState *) opaque;
|
||||
s->cle = qemu_get_byte(f);
|
||||
s->ale = qemu_get_byte(f);
|
||||
s->ce = qemu_get_byte(f);
|
||||
@@ -325,7 +325,7 @@ static int nand_load(QEMUFile *f, void *opaque, int version_id)
|
||||
*
|
||||
* CE, WP and R/B are active low.
|
||||
*/
|
||||
void nand_setpins(struct nand_flash_s *s,
|
||||
void nand_setpins(NANDFlashState *s,
|
||||
int cle, int ale, int ce, int wp, int gnd)
|
||||
{
|
||||
s->cle = cle;
|
||||
@@ -339,12 +339,12 @@ void nand_setpins(struct nand_flash_s *s,
|
||||
s->status &= ~NAND_IOSTATUS_UNPROTCT;
|
||||
}
|
||||
|
||||
void nand_getpins(struct nand_flash_s *s, int *rb)
|
||||
void nand_getpins(NANDFlashState *s, int *rb)
|
||||
{
|
||||
*rb = 1;
|
||||
}
|
||||
|
||||
void nand_setio(struct nand_flash_s *s, uint8_t value)
|
||||
void nand_setio(NANDFlashState *s, uint8_t value)
|
||||
{
|
||||
if (!s->ce && s->cle) {
|
||||
if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
|
||||
@@ -415,7 +415,7 @@ void nand_setio(struct nand_flash_s *s, uint8_t value)
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t nand_getio(struct nand_flash_s *s)
|
||||
uint8_t nand_getio(NANDFlashState *s)
|
||||
{
|
||||
int offset;
|
||||
|
||||
@@ -438,17 +438,17 @@ uint8_t nand_getio(struct nand_flash_s *s)
|
||||
return *(s->ioaddr ++);
|
||||
}
|
||||
|
||||
struct nand_flash_s *nand_init(int manf_id, int chip_id)
|
||||
NANDFlashState *nand_init(int manf_id, int chip_id)
|
||||
{
|
||||
int pagesize;
|
||||
struct nand_flash_s *s;
|
||||
NANDFlashState *s;
|
||||
int index;
|
||||
|
||||
if (nand_flash_ids[chip_id].size == 0) {
|
||||
hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
s = (struct nand_flash_s *) qemu_mallocz(sizeof(struct nand_flash_s));
|
||||
s = (NANDFlashState *) qemu_mallocz(sizeof(NANDFlashState));
|
||||
index = drive_get_index(IF_MTD, 0, 0);
|
||||
if (index != -1)
|
||||
s->bdrv = drives_table[index].bdrv;
|
||||
@@ -499,7 +499,7 @@ struct nand_flash_s *nand_init(int manf_id, int chip_id)
|
||||
return s;
|
||||
}
|
||||
|
||||
void nand_done(struct nand_flash_s *s)
|
||||
void nand_done(NANDFlashState *s)
|
||||
{
|
||||
if (s->bdrv) {
|
||||
bdrv_close(s->bdrv);
|
||||
@@ -515,7 +515,7 @@ void nand_done(struct nand_flash_s *s)
|
||||
#else
|
||||
|
||||
/* Program a single page */
|
||||
static void glue(nand_blk_write_, PAGE_SIZE)(struct nand_flash_s *s)
|
||||
static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s)
|
||||
{
|
||||
uint32_t off, page, sector, soff;
|
||||
uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
|
||||
@@ -561,7 +561,7 @@ static void glue(nand_blk_write_, PAGE_SIZE)(struct nand_flash_s *s)
|
||||
}
|
||||
|
||||
/* Erase a single block */
|
||||
static void glue(nand_blk_erase_, PAGE_SIZE)(struct nand_flash_s *s)
|
||||
static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s)
|
||||
{
|
||||
uint32_t i, page, addr;
|
||||
uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
|
||||
@@ -606,7 +606,7 @@ static void glue(nand_blk_erase_, PAGE_SIZE)(struct nand_flash_s *s)
|
||||
}
|
||||
}
|
||||
|
||||
static void glue(nand_blk_load_, PAGE_SIZE)(struct nand_flash_s *s,
|
||||
static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s,
|
||||
uint32_t addr, int offset)
|
||||
{
|
||||
if (PAGE(addr) >= s->pages)
|
||||
@@ -638,7 +638,7 @@ static void glue(nand_blk_load_, PAGE_SIZE)(struct nand_flash_s *s,
|
||||
s->addr += PAGE_SIZE;
|
||||
}
|
||||
|
||||
static void glue(nand_init_, PAGE_SIZE)(struct nand_flash_s *s)
|
||||
static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s)
|
||||
{
|
||||
s->oob_shift = PAGE_SHIFT - 5;
|
||||
s->pages = s->size >> PAGE_SHIFT;
|
||||
|
||||
+6
-6
@@ -40,14 +40,14 @@ struct n800_s {
|
||||
struct {
|
||||
void *opaque;
|
||||
uint32_t (*txrx)(void *opaque, uint32_t value, int len);
|
||||
struct uwire_slave_s *chip;
|
||||
uWireSlave *chip;
|
||||
} ts;
|
||||
i2c_bus *i2c;
|
||||
|
||||
int keymap[0x80];
|
||||
i2c_slave *kbd;
|
||||
|
||||
struct tusb_s *usb;
|
||||
TUSBState *usb;
|
||||
void *retu;
|
||||
void *tahvo;
|
||||
void *nand;
|
||||
@@ -195,13 +195,13 @@ static void n8x0_i2c_setup(struct n800_s *s)
|
||||
}
|
||||
|
||||
/* Touchscreen and keypad controller */
|
||||
static struct mouse_transform_info_s n800_pointercal = {
|
||||
static MouseTransformInfo n800_pointercal = {
|
||||
.x = 800,
|
||||
.y = 480,
|
||||
.a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
|
||||
};
|
||||
|
||||
static struct mouse_transform_info_s n810_pointercal = {
|
||||
static MouseTransformInfo n810_pointercal = {
|
||||
.x = 800,
|
||||
.y = 480,
|
||||
.a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
|
||||
@@ -729,7 +729,7 @@ static void n8x0_cbus_setup(struct n800_s *s)
|
||||
qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0];
|
||||
qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0];
|
||||
|
||||
struct cbus_s *cbus = cbus_init(dat_out);
|
||||
CBus *cbus = cbus_init(dat_out);
|
||||
|
||||
omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk);
|
||||
omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat);
|
||||
@@ -764,7 +764,7 @@ static void n8x0_usb_setup(struct n800_s *s)
|
||||
{
|
||||
qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0];
|
||||
qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
|
||||
struct tusb_s *tusb = tusb6010_init(tusb_irq);
|
||||
TUSBState *tusb = tusb6010_init(tusb_irq);
|
||||
|
||||
/* Using the NOR interface */
|
||||
omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
|
||||
|
||||
@@ -681,7 +681,7 @@ struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
|
||||
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
|
||||
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
|
||||
|
||||
struct uwire_slave_s {
|
||||
struct uWireSlave {
|
||||
uint16_t (*receive)(void *opaque);
|
||||
void (*send)(void *opaque, uint16_t data);
|
||||
void *opaque;
|
||||
@@ -690,7 +690,7 @@ struct omap_uwire_s;
|
||||
struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
||||
qemu_irq *irq, qemu_irq dma, omap_clk clk);
|
||||
void omap_uwire_attach(struct omap_uwire_s *s,
|
||||
struct uwire_slave_s *slave, int chipselect);
|
||||
uWireSlave *slave, int chipselect);
|
||||
|
||||
struct omap_mcspi_s;
|
||||
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
|
||||
@@ -703,7 +703,7 @@ struct omap_rtc_s;
|
||||
struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
|
||||
qemu_irq *irq, omap_clk clk);
|
||||
|
||||
struct i2s_codec_s {
|
||||
struct I2SCodec {
|
||||
void *opaque;
|
||||
|
||||
/* The CPU can call this if it is generating the clock signal on the
|
||||
@@ -730,7 +730,7 @@ struct i2s_codec_s {
|
||||
struct omap_mcbsp_s;
|
||||
struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
||||
qemu_irq *irq, qemu_irq *dma, omap_clk clk);
|
||||
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
|
||||
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
|
||||
|
||||
struct omap_lpg_s;
|
||||
struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user