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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-20-2019' into staging

Browse Source 
MIPS queue for August 20th, 2019

# gpg: Signature made Mon 19 Aug 2019 19:07:18 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-aug-20-2019:
  target/mips: tests/tcg: Fix target configurations for MSA tests
  target/mips: tests/tcg: Add optional printing of more detailed failure info
  target/mips: Style improvements in mips_mipssim.c
  target/mips: Style improvements in mips_malta.c
  target/mips: Style improvements in mips_int.c
  target/mips: Style improvements in mips_fulong2e.c
  target/mips: Style improvements in cps.c
  target/mips: Style improvements in translate.c
  target/mips: Style improvements in machine.c
  target/mips: Style improvements in cpu.c
  target/mips: Style improvements in cp0_timer.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2019-08-20 13:40:48 +01:00
parent 156d320349 6eed53f71b
commit bbd69d36d1
18 changed files with 3219 additions and 2560 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/mips/cps.c
+4 -2
View File
@@ -38,8 +38,10 @@ static void mips_cps_init(Object *obj)
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
MIPSCPSState *s = MIPS_CPS(obj);
/* Cover entire address space as there do not seem to be any
* constraints for the base address of CPC and GIC. */
/*
* Cover entire address space as there do not seem to be any
* constraints for the base address of CPC and GIC.
*/
memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
sysbus_init_mmio(sbd, &s->container);
}
hw/mips/mips_fulong2e.c
+57 -37
View File
@@ -48,13 +48,13 @@
#define DEBUG_FULONG2E_INIT
#define ENVP_ADDR 0x80002000l
#define ENVP_NB_ENTRIES 16
#define ENVP_ENTRY_SIZE 256
#define ENVP_ADDR 0x80002000l
#define ENVP_NB_ENTRIES 16
#define ENVP_ENTRY_SIZE 256
/* fulong 2e has a 512k flash: Winbond W39L040AP70Z */
#define BIOS_SIZE (512 * KiB)
#define MAX_IDE_BUS 2
#define BIOS_SIZE (512 * KiB)
#define MAX_IDE_BUS 2
/*
* PMON is not part of qemu and released with BSD license, anyone
@@ -83,14 +83,15 @@ static struct _loaderparams {
const char *initrd_filename;
} loaderparams;
static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
const char *string, ...)
{
va_list ap;
int32_t table_addr;
if (index >= ENVP_NB_ENTRIES)
if (index >= ENVP_NB_ENTRIES) {
return;
}
if (string == NULL) {
prom_buf[index] = 0;
@@ -105,7 +106,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
va_end(ap);
}
static int64_t load_kernel (CPUMIPSState *env)
static int64_t load_kernel(CPUMIPSState *env)
{
int64_t kernel_entry, kernel_low, kernel_high, initrd_size;
int index = 0;
@@ -130,16 +131,18 @@ static int64_t load_kernel (CPUMIPSState *env)
initrd_size = 0;
initrd_offset = 0;
if (loaderparams.initrd_filename) {
initrd_size = get_image_size (loaderparams.initrd_filename);
initrd_size = get_image_size(loaderparams.initrd_filename);
if (initrd_size > 0) {
initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
INITRD_PAGE_MASK;
if (initrd_offset + initrd_size > ram_size) {
error_report("memory too small for initial ram disk '%s'",
loaderparams.initrd_filename);
exit(1);
}
initrd_size = load_image_targphys(loaderparams.initrd_filename,
initrd_offset, ram_size - initrd_offset);
initrd_offset,
ram_size - initrd_offset);
}
if (initrd_size == (target_ulong) -1) {
error_report("could not load initial ram disk '%s'",
@@ -154,9 +157,10 @@ static int64_t load_kernel (CPUMIPSState *env)
prom_set(prom_buf, index++, "%s", loaderparams.kernel_filename);
if (initrd_size > 0) {
prom_set(prom_buf, index++, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
loaderparams.kernel_cmdline);
prom_set(prom_buf, index++,
"rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
cpu_mips_phys_to_kseg0(NULL, initrd_offset),
initrd_size, loaderparams.kernel_cmdline);
} else {
prom_set(prom_buf, index++, "%s", loaderparams.kernel_cmdline);
}
@@ -175,34 +179,48 @@ static int64_t load_kernel (CPUMIPSState *env)
return kernel_entry;
}
static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr)
static void write_bootloader(CPUMIPSState *env, uint8_t *base,
int64_t kernel_addr)
{
uint32_t *p;
/* Small bootloader */
p = (uint32_t *) base;
p = (uint32_t *)base;
stl_p(p++, 0x0bf00010); /* j 0x1fc00040 */
stl_p(p++, 0x00000000); /* nop */
/* j 0x1fc00040 */
stl_p(p++, 0x0bf00010);
/* nop */
stl_p(p++, 0x00000000);
/* Second part of the bootloader */
p = (uint32_t *) (base + 0x040);
p = (uint32_t *)(base + 0x040);
stl_p(p++, 0x3c040000); /* lui a0, 0 */
stl_p(p++, 0x34840002); /* ori a0, a0, 2 */
stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */
stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(env->ram_size) */
stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */;
stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */
stl_p(p++, 0x03e00008); /* jr ra */
stl_p(p++, 0x00000000); /* nop */
/* lui a0, 0 */
stl_p(p++, 0x3c040000);
/* ori a0, a0, 2 */
stl_p(p++, 0x34840002);
/* lui a1, high(ENVP_ADDR) */
stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
/* ori a1, a0, low(ENVP_ADDR) */
stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
/* lui a2, high(ENVP_ADDR + 8) */
stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
/* ori a2, a2, low(ENVP_ADDR + 8) */
stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
/* lui a3, high(env->ram_size) */
stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16));
/* ori a3, a3, low(env->ram_size) */
stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff));
/* lui ra, high(kernel_addr) */
stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff));
/* ori ra, ra, low(kernel_addr) */
stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff));
/* jr ra */
stl_p(p++, 0x03e00008);
/* nop */
stl_p(p++, 0x00000000);
}
static void main_cpu_reset(void *opaque)
{
MIPSCPU *cpu = opaque;
@@ -252,11 +270,11 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq intc,
}
/* Network support */
static void network_init (PCIBus *pci_bus)
static void network_init(PCIBus *pci_bus)
{
int i;
for(i = 0; i < nb_nics; i++) {
for (i = 0; i < nb_nics; i++) {
NICInfo *nd = &nd_table[i];
const char *default_devaddr = NULL;
@@ -308,15 +326,17 @@ static void mips_fulong2e_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0, ram);
memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
/* We do not support flash operation, just loading pmon.bin as raw BIOS.
* Please use -L to set the BIOS path and -bios to set bios name. */
/*
* We do not support flash operation, just loading pmon.bin as raw BIOS.
* Please use -L to set the BIOS path and -bios to set bios name.
*/
if (kernel_filename) {
loaderparams.ram_size = ram_size;
loaderparams.kernel_filename = kernel_filename;
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel (env);
kernel_entry = load_kernel(env);
write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
} else {
if (bios_name == NULL) {
hw/mips/mips_int.c
+2 -1
View File
@@ -35,8 +35,9 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
CPUState *cs = CPU(cpu);
bool locked = false;
if (irq < 0 || irq > 7)
if (irq < 0 || irq > 7) {
return;
}
/* Make sure locking works even if BQL is already held by the caller */
if (!qemu_mutex_iothread_locked()) {
hw/mips/mips_malta.c
+128 -88
View File
@@ -60,18 +60,18 @@
#include "hw/semihosting/semihost.h"
#include "hw/mips/cps.h"
#define ENVP_ADDR 0x80002000l
#define ENVP_NB_ENTRIES 16
#define ENVP_ENTRY_SIZE 256
#define ENVP_ADDR 0x80002000l
#define ENVP_NB_ENTRIES 16
#define ENVP_ENTRY_SIZE 256
/* Hardware addresses */
#define FLASH_ADDRESS 0x1e000000ULL
#define FPGA_ADDRESS 0x1f000000ULL
#define RESET_ADDRESS 0x1fc00000ULL
#define FLASH_ADDRESS 0x1e000000ULL
#define FPGA_ADDRESS 0x1f000000ULL
#define RESET_ADDRESS 0x1fc00000ULL
#define FLASH_SIZE 0x400000
#define FLASH_SIZE 0x400000
#define MAX_IDE_BUS 2
#define MAX_IDE_BUS 2
typedef struct {
MemoryRegion iomem;
@@ -117,10 +117,11 @@ static void malta_fpga_update_display(void *opaque)
MaltaFPGAState *s = opaque;
for (i = 7 ; i >= 0 ; i--) {
if (s->leds & (1 << i))
if (s->leds & (1 << i)) {
leds_text[i] = '#';
else
} else {
leds_text[i] = ' ';
}
}
leds_text[8] = '\0';
@@ -140,8 +141,6 @@ static void malta_fpga_update_display(void *opaque)
* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
*/
//~ #define DEBUG
#if defined(DEBUG)
# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
#else
@@ -156,7 +155,7 @@ struct _eeprom24c0x_t {
uint8_t scl;
uint8_t sda;
uint8_t data;
//~ uint16_t size;
/* uint16_t size; */
uint8_t contents[256];
};
@@ -164,22 +163,38 @@ typedef struct _eeprom24c0x_t eeprom24c0x_t;
static eeprom24c0x_t spd_eeprom = {
.contents = {
/* 00000000: */ 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00,
/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
/* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00,
/* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF,
/* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
/* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
/* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
/* 00000000: */
0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
/* 00000008: */
0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
/* 00000010: */
0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
/* 00000018: */
0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
/* 00000020: */
0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
/* 00000028: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000030: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000038: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
/* 00000040: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000048: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000050: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000058: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000060: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000068: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000070: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000078: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
},
};
@@ -349,7 +364,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
/* SWITCH Register */
case 0x00200:
val = 0x00000000; /* All switches closed */
/* ori a3, a3, low(ram_low_size) */
val = 0x00000000;
break;
/* STATUS Register */
@@ -388,10 +404,11 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
/* GPINP Register */
case 0x00a08:
/* IN = OUT until a real I2C control is implemented */
if (s->i2csel)
if (s->i2csel) {
val = s->i2cout;
else
} else {
val = 0x00;
}
break;
/* I2CINP Register */
@@ -416,8 +433,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
default:
#if 0
printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
addr);
printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
addr);
#endif
break;
}
@@ -469,8 +486,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
/* SOFTRES Register */
case 0x00500:
if (val == 0x42)
if (val == 0x42) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
break;
/* BRKRES Register */
@@ -503,8 +521,8 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
default:
#if 0
printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
addr);
printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
addr);
#endif
break;
}
@@ -563,7 +581,7 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
&s->iomem, 0, 0x900);
memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
&s->iomem, 0xa00, 0x10000-0xa00);
&s->iomem, 0xa00, 0x10000 - 0xa00);
memory_region_add_subregion(address_space, base, &s->iomem_lo);
memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
@@ -587,7 +605,7 @@ static void network_init(PCIBus *pci_bus)
{
int i;
for(i = 0; i < nb_nics; i++) {
for (i = 0; i < nb_nics; i++) {
NICInfo *nd = &nd_table[i];
const char *default_devaddr = NULL;
@@ -801,27 +819,28 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
/* jalrc t8 */
}
/* ROM and pseudo bootloader
The following code implements a very very simple bootloader. It first
loads the registers a0 to a3 to the values expected by the OS, and
then jump at the kernel address.
The bootloader should pass the locations of the kernel arguments and
environment variables tables. Those tables contain the 32-bit address
of NULL terminated strings. The environment variables table should be
terminated by a NULL address.
For a simpler implementation, the number of kernel arguments is fixed
to two (the name of the kernel and the command line), and the two
tables are actually the same one.
The registers a0 to a3 should contain the following values:
a0 - number of kernel arguments
a1 - 32-bit address of the kernel arguments table
a2 - 32-bit address of the environment variables table
a3 - RAM size in bytes
*/
/*
* ROM and pseudo bootloader
*
* The following code implements a very very simple bootloader. It first
* loads the registers a0 to a3 to the values expected by the OS, and
* then jump at the kernel address.
*
* The bootloader should pass the locations of the kernel arguments and
* environment variables tables. Those tables contain the 32-bit address
* of NULL terminated strings. The environment variables table should be
* terminated by a NULL address.
*
* For a simpler implementation, the number of kernel arguments is fixed
* to two (the name of the kernel and the command line), and the two
* tables are actually the same one.
*
* The registers a0 to a3 should contain the following values:
* a0 - number of kernel arguments
* a1 - 32-bit address of the kernel arguments table
* a2 - 32-bit address of the environment variables table
* a3 - RAM size in bytes
*/
static void write_bootloader(uint8_t *base, int64_t run_addr,
int64_t kernel_entry)
{
@@ -859,14 +878,23 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
} else {
stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
}
stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); /* lui a3, high(ram_low_size) */
stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); /* ori a3, a3, low(ram_low_size) */
/* lui sp, high(ENVP_ADDR) */
stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
/* ori sp, sp, low(ENVP_ADDR) */
stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
/* lui a1, high(ENVP_ADDR) */
stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
/* ori a1, a1, low(ENVP_ADDR) */
stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
/* lui a2, high(ENVP_ADDR + 8) */
stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
/* ori a2, a2, low(ENVP_ADDR + 8) */
stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
/* lui a3, high(ram_low_size) */
stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
/* ori a3, a3, low(ram_low_size) */
stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
/* Load BAR registers as done by YAMON */
stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
@@ -970,14 +998,15 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
}
static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
const char *string, ...)
{
va_list ap;
int32_t table_addr;
if (index >= ENVP_NB_ENTRIES)
if (index >= ENVP_NB_ENTRIES) {
return;
}
if (string == NULL) {
prom_buf[index] = 0;
@@ -993,7 +1022,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
}
/* Kernel */
static int64_t load_kernel (void)
static int64_t load_kernel(void)
{
int64_t kernel_entry, kernel_high, initrd_size;
long kernel_size;
@@ -1041,11 +1070,13 @@ static int64_t load_kernel (void)
initrd_size = 0;
initrd_offset = 0;
if (loaderparams.initrd_filename) {
initrd_size = get_image_size (loaderparams.initrd_filename);
initrd_size = get_image_size(loaderparams.initrd_filename);
if (initrd_size > 0) {
/* The kernel allocates the bootmap memory in the low memory after
the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
pages. */
/*
* The kernel allocates the bootmap memory in the low memory after
* the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
* pages.
*/
initrd_offset = (loaderparams.ram_low_size - initrd_size
- (128 * KiB)
- ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
@@ -1071,9 +1102,10 @@ static int64_t load_kernel (void)
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
if (initrd_size > 0) {
prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
xlate_to_kseg0(NULL, initrd_offset), initrd_size,
loaderparams.kernel_cmdline);
prom_set(prom_buf, prom_index++,
"rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
xlate_to_kseg0(NULL, initrd_offset),
initrd_size, loaderparams.kernel_cmdline);
} else {
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
}
@@ -1113,9 +1145,11 @@ static void main_cpu_reset(void *opaque)
cpu_reset(CPU(cpu));
/* The bootloader does not need to be rewritten as it is located in a
read only location. The kernel location and the arguments table
location does not change. */
/*
* The bootloader does not need to be rewritten as it is located in a
* read only location. The kernel location and the arguments table
* location does not change.
*/
if (loaderparams.kernel_filename) {
env->CP0_Status &= ~(1 << CP0St_ERL);
}
@@ -1213,9 +1247,11 @@ void mips_malta_init(MachineState *machine)
DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA);
MaltaState *s = MIPS_MALTA(dev);
/* The whole address space decoded by the GT-64120A doesn't generate
exception when accessing invalid memory. Create an empty slot to
emulate this feature. */
/*
* The whole address space decoded by the GT-64120A doesn't generate
* exception when accessing invalid memory. Create an empty slot to
* emulate this feature.\
*/
empty_slot_init(0, 0x20000000);
qdev_init_nofail(dev);
@@ -1331,8 +1367,10 @@ void mips_malta_init(MachineState *machine)
exit(1);
}
}
/* In little endian mode the 32bit words in the bios are swapped,
a neat trick which allows bi-endian firmware. */
/*
* In little endian mode the 32bit words in the bios are swapped,
* a neat trick which allows bi-endian firmware.
*/
#ifndef TARGET_WORDS_BIGENDIAN
{
uint32_t *end, *addr;
@@ -1386,8 +1424,10 @@ void mips_malta_init(MachineState *machine)
piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
/* Interrupt controller */
/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
/*
* Interrupt controller
* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
*/
s->i8259 = i8259_init(isa_bus, i8259_irq);
isa_bus_irqs(isa_bus, s->i8259);
hw/mips/mips_mipssim.c
+12 -7
View File
@@ -3,7 +3,7 @@
*
* Emulates a very simple machine model similar to the one used by the
* proprietary MIPS emulator.
*
*
* Copyright (c) 2007 Thiemo Seufer
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
@@ -76,8 +76,9 @@ static int64_t load_kernel(void)
(uint64_t *)&kernel_high, big_endian,
EM_MIPS, 1, 0);
if (kernel_size >= 0) {
if ((entry & ~0x7fffffffULL) == 0x80000000)
if ((entry & ~0x7fffffffULL) == 0x80000000) {
entry = (int32_t)entry;
}
} else {
error_report("could not load kernel '%s': %s",
loaderparams.kernel_filename,
@@ -89,9 +90,10 @@ static int64_t load_kernel(void)
initrd_size = 0;
initrd_offset = 0;
if (loaderparams.initrd_filename) {
initrd_size = get_image_size (loaderparams.initrd_filename);
initrd_size = get_image_size(loaderparams.initrd_filename);
if (initrd_size > 0) {
initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
INITRD_PAGE_MASK;
if (initrd_offset + initrd_size > loaderparams.ram_size) {
error_report("memory too small for initial ram disk '%s'",
loaderparams.initrd_filename);
@@ -175,8 +177,9 @@ mips_mipssim_init(MachineState *machine)
/* Map the BIOS / boot exception handler. */
memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
/* Load a BIOS / boot exception handler image. */
if (bios_name == NULL)
if (bios_name == NULL) {
bios_name = BIOS_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
@@ -212,8 +215,10 @@ mips_mipssim_init(MachineState *machine)
get_system_io(), 0, 0x00010000);
memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa);
/* A single 16450 sits at offset 0x3f8. It is attached to
MIPS CPU INT2, which is interrupt 4. */
/*
* A single 16450 sits at offset 0x3f8. It is attached to
* MIPS CPU INT2, which is interrupt 4.
*/
if (serial_hd(0))
serial_init(0x3f8, env->irq[4], 115200, serial_hd(0),
get_system_io());
target/mips/cp0_timer.c
+23 -19
View File
@@ -30,7 +30,7 @@
#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
/* XXX: do not use a global */
uint32_t cpu_mips_get_random (CPUMIPSState *env)
uint32_t cpu_mips_get_random(CPUMIPSState *env)
{
static uint32_t seed = 1;
static uint32_t prev_idx = 0;
@@ -43,8 +43,10 @@ uint32_t cpu_mips_get_random (CPUMIPSState *env)
/* Don't return same value twice, so get another value */
do {
/* Use a simple algorithm of Linear Congruential Generator
* from ISO/IEC 9899 standard. */
/*
* Use a simple algorithm of Linear Congruential Generator
* from ISO/IEC 9899 standard.
*/
seed = 1103515245 * seed + 12345;
idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
} while (idx == prev_idx);
@@ -74,7 +76,7 @@ static void cpu_mips_timer_expire(CPUMIPSState *env)
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
uint32_t cpu_mips_get_count (CPUMIPSState *env)
uint32_t cpu_mips_get_count(CPUMIPSState *env)
{
if (env->CP0_Cause & (1 << CP0Ca_DC)) {
return env->CP0_Count;
@@ -92,16 +94,16 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env)
}
}
void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
void cpu_mips_store_count(CPUMIPSState *env, uint32_t count)
{
/*
* This gets called from cpu_state_reset(), potentially before timer init.
* So env->timer may be NULL, which is also the case with KVM enabled so
* treat timer as disabled in that case.
*/
if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer)
if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) {
env->CP0_Count = count;
else {
} else {
/* Store new count register */
env->CP0_Count = count -
(uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD);
@@ -110,13 +112,15 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
}
}
void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
{
env->CP0_Compare = value;
if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
cpu_mips_timer_update(env);
if (env->insn_flags & ISA_MIPS32R2)
}
if (env->insn_flags & ISA_MIPS32R2) {
env->CP0_Cause &= ~(1 << CP0Ca_TI);
}
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
@@ -132,27 +136,27 @@ void cpu_mips_stop_count(CPUMIPSState *env)
TIMER_PERIOD);
}
static void mips_timer_cb (void *opaque)
static void mips_timer_cb(void *opaque)
{
CPUMIPSState *env;
env = opaque;
#if 0
qemu_log("%s\n", __func__);
#endif
if (env->CP0_Cause & (1 << CP0Ca_DC))
if (env->CP0_Cause & (1 << CP0Ca_DC)) {
return;
}
/* ??? This callback should occur when the counter is exactly equal to
the comparator value. Offset the count by one to avoid immediately
retriggering the callback before any virtual time has passed. */
/*
* ??? This callback should occur when the counter is exactly equal to
* the comparator value. Offset the count by one to avoid immediately
* retriggering the callback before any virtual time has passed.
*/
env->CP0_Count++;
cpu_mips_timer_expire(env);
env->CP0_Count--;
}
void cpu_mips_clock_init (MIPSCPU *cpu)
void cpu_mips_clock_init(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;
target/mips/cpu.c
+11 -6
View File
@@ -57,9 +57,11 @@ static bool mips_cpu_has_work(CPUState *cs)
CPUMIPSState *env = &cpu->env;
bool has_work = false;
/* Prior to MIPS Release 6 it is implementation dependent if non-enabled
interrupts wake-up the CPU, however most of the implementations only
check for interrupts that can be taken. */
/*
* Prior to MIPS Release 6 it is implementation dependent if non-enabled
* interrupts wake-up the CPU, however most of the implementations only
* check for interrupts that can be taken.
*/
if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
if (cpu_mips_hw_interrupts_enabled(env) ||
@@ -70,8 +72,10 @@ static bool mips_cpu_has_work(CPUState *cs)
/* MIPS-MT has the ability to halt the CPU. */
if (env->CP0_Config3 & (1 << CP0C3_MT)) {
/* The QEMU model will issue an _WAKE request whenever the CPUs
should be woken up. */
/*
* The QEMU model will issue an _WAKE request whenever the CPUs
* should be woken up.
*/
if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
has_work = true;
}
@@ -112,7 +116,8 @@ static void mips_cpu_reset(CPUState *s)
#endif
}
static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
MIPSCPU *cpu = MIPS_CPU(s);
CPUMIPSState *env = &cpu->env;
target/mips/machine.c
+2 -2
View File
@@ -24,7 +24,7 @@ static int get_fpr(QEMUFile *f, void *pv, size_t size,
int i;
fpr_t *v = pv;
/* Restore entire MSA vector register */
for (i = 0; i < MSA_WRLEN/64; i++) {
for (i = 0; i < MSA_WRLEN / 64; i++) {
qemu_get_sbe64s(f, &v->wr.d[i]);
}
return 0;
@@ -36,7 +36,7 @@ static int put_fpr(QEMUFile *f, void *pv, size_t size,
int i;
fpr_t *v = pv;
/* Save entire MSA vector register */
for (i = 0; i < MSA_WRLEN/64; i++) {
for (i = 0; i < MSA_WRLEN / 64; i++) {
qemu_put_sbe64s(f, &v->wr.d[i]);
}
target/mips/translate.c
+382 -369
View File
File diff suppressed because it is too large Load Diff
tests/tcg/mips/include/test_utils_128.h
+22 -1
View File
@@ -27,7 +27,8 @@
#include <inttypes.h>
#include <string.h>
#define PRINT_RESULTS 0
#define PRINT_RESULTS 0
#define PRINT_FAILURES 0
static inline int32_t check_results_128(const char *isa_ase_name,
@@ -65,6 +66,26 @@ static inline int32_t check_results_128(const char *isa_ase_name,
(b128_result[2 * i + 1] == b128_expect[2 * i + 1])) {
pass_count++;
} else {
#if PRINT_FAILURES
uint32_t ii;
uint64_t a, b;
printf("\n");
printf("FAILURE for test case %d!\n", i);
memcpy(&a, (b128_expect + 2 * i), 8);
memcpy(&b, (b128_expect + 2 * i + 1), 8);
printf("Expected result : { 0x%016llxULL, 0x%016llxULL, },\n",
a, b);
memcpy(&a, (b128_result + 2 * i), 8);
memcpy(&b, (b128_result + 2 * i + 1), 8);
printf("Actual result : { 0x%016llxULL, 0x%016llxULL, },\n",
a, b);
printf("\n");
#endif
fail_count++;
}
}
tests/tcg/mips/user/ase/msa/test_msa_compile_32r5eb.sh
Executable
+917
View File
File diff suppressed because it is too large Load Diff
tests/tcg/mips/user/ase/msa/test_msa_compile_32r5el.sh
Executable
+917
View File
File diff suppressed because it is too large Load Diff
tests/tcg/mips/user/ase/msa/test_msa_compile_32r6eb.sh
-643
View File
File diff suppressed because it is too large Load Diff
tests/tcg/mips/user/ase/msa/test_msa_compile_32r6el.sh
-643
View File
File diff suppressed because it is too large Load Diff
tests/tcg/mips/user/ase/msa/test_msa_run_32r5eb.sh
Executable
+371
View File
@@ -0,0 +1,371 @@
PATH_TO_QEMU="../../../../../../mips-linux-user/qemu-mips"
#
# Bit Count
# ---------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_d_32r5eb
#
# Bit move
# --------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsl_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsl_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsl_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsl_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsr_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsr_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsr_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsr_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bmnz_v_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bmz_v_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bsel_v_32r5eb
#
# Bit Set
# -------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bclr_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bclr_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bclr_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bclr_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bneg_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bneg_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bneg_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bneg_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bset_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bset_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bset_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bset_d_32r5eb
#
# Fixed Multiply
# --------------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_madd_q_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_madd_q_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddr_q_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddr_q_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msub_q_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msub_q_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubr_q_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubr_q_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mul_q_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mul_q_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulr_q_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulr_q_w_32r5eb
#
# Float Max Min
# -------------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmax_a_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmax_a_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmax_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmax_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmin_a_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmin_a_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmin_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmin_d_32r5eb
#
# Int Add
# -------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_add_a_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_add_a_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_add_a_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_add_a_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_a_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_a_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_a_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_a_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_u_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_addv_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_addv_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_addv_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_addv_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_u_d_32r5eb
#
# Int Average
# -----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_u_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_u_d_32r5eb
#
# Int Compare
# -----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ceq_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ceq_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ceq_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ceq_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_u_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_u_d_32r5eb
#
# Int Divide
# ----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_u_d_32r5eb
#
# Int Dot Product
# ---------------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_u_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_u_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_u_d_32r5eb
#
# Int Max Min
# -----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_a_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_a_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_a_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_a_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_u_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_a_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_a_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_a_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_a_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_u_d_32r5eb
#
# Int Modulo
# ----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_u_d_32r5eb
#
# Int Multiply
# ------------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddv_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddv_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddv_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddv_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubv_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubv_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubv_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubv_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulv_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulv_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulv_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulv_d_32r5eb
#
# Int Subtract
# ------------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_u_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_u_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_u_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsus_u_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsus_u_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsus_u_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsus_u_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsuu_s_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsuu_s_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsuu_s_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsuu_s_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subv_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subv_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subv_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subv_d_32r5eb
#
# Interleave
# ----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvev_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvev_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvev_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvev_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvod_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvod_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvod_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvod_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvl_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvl_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvl_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvl_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvr_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvr_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvr_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvr_d_32r5eb
#
# Logic
# -----
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_and_v_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nor_v_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_or_v_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_xor_v_32r5eb
#
# Move
# ----
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_move_v_32r5eb
#
# Pack
# ----
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckev_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckev_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckev_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckev_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckod_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckod_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckod_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckod_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_vshf_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_vshf_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_vshf_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_vshf_d_32r5eb
#
# Shift
# -----
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sll_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sll_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sll_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sll_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sra_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sra_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sra_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sra_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srar_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srar_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srar_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srar_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srl_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srl_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srl_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srl_d_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srlr_b_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srlr_h_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srlr_w_32r5eb
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srlr_d_32r5eb
tests/tcg/mips/user/ase/msa/test_msa_run_32r5el.sh
Executable
+371
View File
@@ -0,0 +1,371 @@
PATH_TO_QEMU="../../../../../../mipsel-linux-user/qemu-mipsel"
#
# Bit Count
# ---------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_d_32r5el
#
# Bit move
# --------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsl_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsl_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsl_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsl_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsr_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsr_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsr_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_binsr_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bmnz_v_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bmz_v_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bsel_v_32r5el
#
# Bit Set
# -------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bclr_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bclr_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bclr_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bclr_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bneg_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bneg_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bneg_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bneg_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bset_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bset_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bset_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_bset_d_32r5el
#
# Fixed Multiply
# --------------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_madd_q_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_madd_q_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddr_q_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddr_q_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msub_q_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msub_q_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubr_q_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubr_q_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mul_q_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mul_q_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulr_q_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulr_q_w_32r5el
#
# Float Max Min
# -------------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmax_a_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmax_a_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmax_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmax_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmin_a_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmin_a_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmin_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_fmin_d_32r5el
#
# Int Add
# -------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_add_a_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_add_a_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_add_a_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_add_a_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_a_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_a_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_a_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_a_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_adds_u_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_addv_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_addv_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_addv_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_addv_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hadd_u_d_32r5el
#
# Int Average
# -----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ave_u_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_aver_u_d_32r5el
#
# Int Compare
# -----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ceq_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ceq_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ceq_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ceq_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_cle_u_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_clt_u_d_32r5el
#
# Int Divide
# ----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_div_u_d_32r5el
#
# Int Dot Product
# ---------------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dotp_u_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpadd_u_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_dpsub_u_d_32r5el
#
# Int Max Min
# -----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_a_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_a_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_a_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_a_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_max_u_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_a_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_a_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_a_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_a_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_min_u_d_32r5el
#
# Int Modulo
# ----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mod_u_d_32r5el
#
# Int Multiply
# ------------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddv_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddv_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddv_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_maddv_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubv_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubv_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubv_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_msubv_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulv_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulv_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulv_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_mulv_d_32r5el
#
# Int Subtract
# ------------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_asub_u_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_hsub_u_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subs_u_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsus_u_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsus_u_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsus_u_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsus_u_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsuu_s_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsuu_s_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsuu_s_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subsuu_s_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subv_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subv_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subv_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_subv_d_32r5el
#
# Interleave
# ----------
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvev_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvev_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvev_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvev_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvod_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvod_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvod_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvod_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvl_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvl_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvl_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvl_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvr_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvr_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvr_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_ilvr_d_32r5el
#
# Logic
# -----
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_and_v_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nor_v_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_or_v_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_xor_v_32r5el
#
# Move
# ----
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_move_v_32r5el
#
# Pack
# ----
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckev_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckev_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckev_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckev_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckod_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckod_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckod_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pckod_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_vshf_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_vshf_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_vshf_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_vshf_d_32r5el
#
# Shift
# -----
#
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sll_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sll_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sll_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sll_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sra_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sra_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sra_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_sra_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srar_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srar_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srar_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srar_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srl_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srl_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srl_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srl_d_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srlr_b_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srlr_h_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srlr_w_32r5el
$PATH_TO_QEMU -cpu P5600 /tmp/test_msa_srlr_d_32r5el
tests/tcg/mips/user/ase/msa/test_msa_run_32r6eb.sh
-371
View File
@@ -1,371 +0,0 @@
PATH_TO_QEMU="../../../../../../mips64-linux-user/qemu-mips64"
#
# Bit Count
# ---------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_d_32r6eb
#
# Bit move
# --------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsl_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsl_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsl_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsl_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsr_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsr_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsr_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsr_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bmnz_v_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bmz_v_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bsel_v_32r6eb
#
# Bit Set
# -------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bclr_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bclr_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bclr_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bclr_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bneg_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bneg_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bneg_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bneg_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bset_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bset_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bset_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bset_d_32r6eb
#
# Fixed Multiply
# --------------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_madd_q_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_madd_q_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddr_q_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddr_q_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msub_q_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msub_q_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubr_q_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubr_q_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mul_q_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mul_q_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulr_q_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulr_q_w_32r6eb
#
# Float Max Min
# -------------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmax_a_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmax_a_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmax_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmax_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmin_a_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmin_a_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmin_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmin_d_32r6eb
#
# Int Add
# -------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_add_a_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_add_a_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_add_a_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_add_a_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_a_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_a_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_a_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_a_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_u_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_addv_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_addv_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_addv_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_addv_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_u_d_32r6eb
#
# Int Average
# -----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_u_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_u_d_32r6eb
#
# Int Compare
# -----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ceq_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ceq_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ceq_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ceq_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_u_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_u_d_32r6eb
#
# Int Divide
# ----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_u_d_32r6eb
#
# Int Dot Product
# ---------------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_u_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_u_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_u_d_32r6eb
#
# Int Max Min
# -----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_a_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_a_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_a_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_a_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_u_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_a_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_a_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_a_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_a_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_u_d_32r6eb
#
# Int Modulo
# ----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_u_d_32r6eb
#
# Int Multiply
# ------------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddv_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddv_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddv_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddv_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubv_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubv_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubv_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubv_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulv_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulv_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulv_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulv_d_32r6eb
#
# Int Subtract
# ------------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_u_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_u_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_u_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsus_u_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsus_u_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsus_u_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsus_u_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsuu_s_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsuu_s_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsuu_s_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsuu_s_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subv_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subv_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subv_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subv_d_32r6eb
#
# Interleave
# ----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvev_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvev_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvev_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvev_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvod_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvod_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvod_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvod_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvl_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvl_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvl_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvl_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvr_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvr_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvr_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvr_d_32r6eb
#
# Logic
# -----
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_and_v_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nor_v_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_or_v_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_xor_v_32r6eb
#
# Move
# ----
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_move_v_32r6eb
#
# Pack
# ----
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckev_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckev_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckev_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckev_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckod_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckod_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckod_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckod_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_vshf_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_vshf_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_vshf_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_vshf_d_32r6eb
#
# Shift
# -----
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sll_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sll_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sll_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sll_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sra_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sra_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sra_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sra_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srar_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srar_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srar_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srar_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srl_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srl_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srl_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srl_d_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srlr_b_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srlr_h_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srlr_w_32r6eb
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srlr_d_32r6eb
tests/tcg/mips/user/ase/msa/test_msa_run_32r6el.sh
-371
View File
@@ -1,371 +0,0 @@
PATH_TO_QEMU="../../../../../../mips64el-linux-user/qemu-mips64el"
#
# Bit Count
# ---------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_d_32r6el
#
# Bit move
# --------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsl_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsl_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsl_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsl_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsr_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsr_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsr_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_binsr_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bmnz_v_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bmz_v_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bsel_v_32r6el
#
# Bit Set
# -------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bclr_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bclr_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bclr_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bclr_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bneg_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bneg_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bneg_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bneg_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bset_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bset_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bset_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_bset_d_32r6el
#
# Fixed Multiply
# --------------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_madd_q_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_madd_q_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddr_q_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddr_q_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msub_q_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msub_q_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubr_q_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubr_q_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mul_q_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mul_q_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulr_q_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulr_q_w_32r6el
#
# Float Max Min
# -------------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmax_a_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmax_a_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmax_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmax_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmin_a_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmin_a_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmin_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_fmin_d_32r6el
#
# Int Add
# -------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_add_a_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_add_a_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_add_a_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_add_a_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_a_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_a_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_a_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_a_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_adds_u_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_addv_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_addv_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_addv_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_addv_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hadd_u_d_32r6el
#
# Int Average
# -----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ave_u_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_aver_u_d_32r6el
#
# Int Compare
# -----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ceq_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ceq_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ceq_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ceq_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_cle_u_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_clt_u_d_32r6el
#
# Int Divide
# ----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_div_u_d_32r6el
#
# Int Dot Product
# ---------------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dotp_u_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpadd_u_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_dpsub_u_d_32r6el
#
# Int Max Min
# -----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_a_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_a_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_a_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_a_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_max_u_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_a_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_a_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_a_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_a_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_min_u_d_32r6el
#
# Int Modulo
# ----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mod_u_d_32r6el
#
# Int Multiply
# ------------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddv_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddv_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddv_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_maddv_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubv_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubv_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubv_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_msubv_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulv_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulv_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulv_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_mulv_d_32r6el
#
# Int Subtract
# ------------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_asub_u_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_hsub_u_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subs_u_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsus_u_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsus_u_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsus_u_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsus_u_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsuu_s_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsuu_s_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsuu_s_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subsuu_s_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subv_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subv_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subv_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_subv_d_32r6el
#
# Interleave
# ----------
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvev_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvev_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvev_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvev_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvod_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvod_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvod_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvod_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvl_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvl_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvl_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvl_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvr_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvr_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvr_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_ilvr_d_32r6el
#
# Logic
# -----
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_and_v_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nor_v_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_or_v_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_xor_v_32r6el
#
# Move
# ----
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_move_v_32r6el
#
# Pack
# ----
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckev_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckev_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckev_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckev_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckod_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckod_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckod_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pckod_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_vshf_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_vshf_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_vshf_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_vshf_d_32r6el
#
# Shift
# -----
#
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sll_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sll_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sll_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sll_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sra_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sra_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sra_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_sra_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srar_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srar_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srar_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srar_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srl_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srl_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srl_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srl_d_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srlr_b_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srlr_h_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srlr_w_32r6el
$PATH_TO_QEMU -cpu I6400 /tmp/test_msa_srlr_d_32r6el