mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-2018' into staging
MIPS queue Aug 16, 2018 # gpg: Signature made Thu 16 Aug 2018 18:19:36 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-aug-2018: qemu-doc: Amend MIPS-related items linux-user: Add preprocessor availability control to some syscalls linux-user: Update MIPS syscall numbers up to kernel 4.18 headers elf: Add ELF flags for MIPS machine variants elf: Remove duplicate preprocessor constant definition target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 target/mips: Don't update BadVAddr register in Debug Mode target/mips: Implement CP0 Config1.WR bit functionality target/mips: Add CP0 BadInstrX register target/mips: Update some CP0 registers bit definitions target/mips: Fix two instances of shadow variables target/mips: Mark switch fallthroughs with interpretable comments target/mips: Avoid case statements formulated by ranges - part 2 target/mips: Avoid case statements formulated by ranges - part 1 MAINTAINERS: Update target/mips maintainer's email addresses Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
@@ -12,8 +12,11 @@ Fabrice Bellard <fabrice@bellard.org> bellard <bellard@c046a42c-6fe2-441c-8c8c-7
|
||||
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
|
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Jocelyn Mayer <l_indien@magic.fr> j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>
|
||||
Paul Brook <paul@codesourcery.com> pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>
|
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Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
|
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Paul Burton <paul.burton@mips.com> <paul@archlinuxmips.org>
|
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Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@mips.com>
|
||||
Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@imgtec.com>
|
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Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
|
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Paul Burton <pburton@wavecomp.com> <paul.burton@imgtec.com>
|
||||
Paul Burton <pburton@wavecomp.com> <paul@archlinuxmips.org>
|
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Thiemo Seufer <ths@networkno.de> ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
|
||||
malc <av1474@comtv.ru> malc <malc@c046a42c-6fe2-441c-8c8c-71466251a162>
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|
||||
|
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+5
-4
@@ -187,7 +187,7 @@ F: disas/microblaze.c
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||||
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MIPS
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M: Aurelien Jarno <aurelien@aurel32.net>
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M: Aleksandar Markovic <aleksandar.markovic@mips.com>
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M: Aleksandar Markovic <amarkovic@wavecomp.com>
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||||
S: Maintained
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||||
F: target/mips/
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||||
F: hw/mips/
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||||
@@ -718,7 +718,7 @@ S: Maintained
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||||
F: hw/mips/mips_malta.c
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||||
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Mipssim
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||||
M: Aleksandar Markovic <aleksandar.markovic@mips.com>
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||||
M: Aleksandar Markovic <amarkovic@wavecomp.com>
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||||
S: Odd Fixes
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||||
F: hw/mips/mips_mipssim.c
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||||
F: hw/net/mipsnet.c
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||||
@@ -729,14 +729,15 @@ S: Maintained
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||||
F: hw/mips/mips_r4k.c
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||||
|
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Fulong 2E
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M: Aleksandar Markovic <aleksandar.markovic@mips.com>
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||||
M: Aleksandar Markovic <amarkovic@wavecomp.com>
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S: Odd Fixes
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||||
F: hw/mips/mips_fulong2e.c
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F: hw/isa/vt82c686.c
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F: include/hw/isa/vt82c686.h
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|
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Boston
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||||
M: Paul Burton <paul.burton@mips.com>
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M: Paul Burton <pburton@wavecomp.com>
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S: Maintained
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F: hw/core/loader-fit.c
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||||
F: hw/mips/boston.c
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||||
|
||||
+23
-1
@@ -61,7 +61,29 @@ typedef int64_t Elf64_Sxword;
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||||
#define EF_MIPS_ABI 0x0000f000
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#define EF_MIPS_FP64 0x00000200
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#define EF_MIPS_NAN2008 0x00000400
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#define EF_MIPS_ARCH 0xf0000000
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||||
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||||
/* MIPS machine variant */
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#define EF_MIPS_MACH_NONE 0x00000000 /* A standard MIPS implementation */
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#define EF_MIPS_MACH_3900 0x00810000 /* Toshiba R3900 */
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#define EF_MIPS_MACH_4010 0x00820000 /* LSI R4010 */
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#define EF_MIPS_MACH_4100 0x00830000 /* NEC VR4100 */
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#define EF_MIPS_MACH_4650 0x00850000 /* MIPS R4650 */
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#define EF_MIPS_MACH_4120 0x00870000 /* NEC VR4120 */
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#define EF_MIPS_MACH_4111 0x00880000 /* NEC VR4111/VR4181 */
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#define EF_MIPS_MACH_SB1 0x008a0000 /* Broadcom SB-1 */
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#define EF_MIPS_MACH_OCTEON 0x008b0000 /* Cavium Networks Octeon */
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#define EF_MIPS_MACH_XLR 0x008c0000 /* RMI Xlr */
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#define EF_MIPS_MACH_OCTEON2 0x008d0000 /* Cavium Networks Octeon2 */
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||||
#define EF_MIPS_MACH_OCTEON3 0x008e0000 /* Cavium Networks Octeon3 */
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||||
#define EF_MIPS_MACH_5400 0x00910000 /* NEC VR5400 */
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||||
#define EF_MIPS_MACH_5900 0x00920000 /* MIPS R5900 */
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||||
#define EF_MIPS_MACH_5500 0x00980000 /* NEC VR5500 */
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||||
#define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra's RM9000 */
|
||||
#define EF_MIPS_MACH_LS2E 0x00a00000 /* ST Microelectronics Loongson 2E */
|
||||
#define EF_MIPS_MACH_LS2F 0x00a10000 /* ST Microelectronics Loongson 2F */
|
||||
#define EF_MIPS_MACH_LS3A 0x00a20000 /* ST Microelectronics Loongson 3A */
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||||
#define EF_MIPS_MACH 0x00ff0000 /* EF_MIPS_MACH_xxx selection mask */
|
||||
|
||||
|
||||
/* These constants define the different elf file types */
|
||||
#define ET_NONE 0
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||||
|
||||
@@ -363,3 +363,12 @@
|
||||
#define TARGET_NR_userfaultfd (TARGET_NR_Linux + 357)
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||||
#define TARGET_NR_membarrier (TARGET_NR_Linux + 358)
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||||
#define TARGET_NR_mlock2 (TARGET_NR_Linux + 359)
|
||||
#define TARGET_NR_copy_file_range (TARGET_NR_Linux + 360)
|
||||
#define TARGET_NR_preadv2 (TARGET_NR_Linux + 361)
|
||||
#define TARGET_NR_pwritev2 (TARGET_NR_Linux + 362)
|
||||
#define TARGET_NR_pkey_mprotect (TARGET_NR_Linux + 363)
|
||||
#define TARGET_NR_pkey_alloc (TARGET_NR_Linux + 364)
|
||||
#define TARGET_NR_pkey_free (TARGET_NR_Linux + 365)
|
||||
#define TARGET_NR_statx (TARGET_NR_Linux + 366)
|
||||
#define TARGET_NR_rseq (TARGET_NR_Linux + 367)
|
||||
#define TARGET_NR_io_pgetevents (TARGET_NR_Linux + 368)
|
||||
|
||||
@@ -327,6 +327,15 @@
|
||||
#define TARGET_NR_userfaultfd (TARGET_NR_Linux + 321)
|
||||
#define TARGET_NR_membarrier (TARGET_NR_Linux + 322)
|
||||
#define TARGET_NR_mlock2 (TARGET_NR_Linux + 323)
|
||||
#define TARGET_NR_copy_file_range (TARGET_NR_Linux + 324)
|
||||
#define TARGET_NR_preadv2 (TARGET_NR_Linux + 325)
|
||||
#define TARGET_NR_pwritev2 (TARGET_NR_Linux + 326)
|
||||
#define TARGET_NR_pkey_mprotect (TARGET_NR_Linux + 327)
|
||||
#define TARGET_NR_pkey_alloc (TARGET_NR_Linux + 328)
|
||||
#define TARGET_NR_pkey_free (TARGET_NR_Linux + 329)
|
||||
#define TARGET_NR_statx (TARGET_NR_Linux + 330)
|
||||
#define TARGET_NR_rseq (TARGET_NR_Linux + 331)
|
||||
#define TARGET_NR_io_pgetevents (TARGET_NR_Linux + 332)
|
||||
|
||||
#else
|
||||
/*
|
||||
@@ -653,4 +662,13 @@
|
||||
#define TARGET_NR_userfaultfd (TARGET_NR_Linux + 317)
|
||||
#define TARGET_NR_membarrier (TARGET_NR_Linux + 318)
|
||||
#define TARGET_NR_mlock2 (TARGET_NR_Linux + 319)
|
||||
#define TARGET_NR_copy_file_range (TARGET_NR_Linux + 320)
|
||||
#define TARGET_NR_preadv2 (TARGET_NR_Linux + 321)
|
||||
#define TARGET_NR_pwritev2 (TARGET_NR_Linux + 322)
|
||||
#define TARGET_NR_pkey_mprotect (TARGET_NR_Linux + 323)
|
||||
#define TARGET_NR_pkey_alloc (TARGET_NR_Linux + 324)
|
||||
#define TARGET_NR_pkey_free (TARGET_NR_Linux + 325)
|
||||
#define TARGET_NR_statx (TARGET_NR_Linux + 326)
|
||||
#define TARGET_NR_rseq (TARGET_NR_Linux + 327)
|
||||
#define TARGET_NR_io_pgetevents (TARGET_NR_Linux + 328)
|
||||
#endif
|
||||
|
||||
+13
-1
@@ -2304,7 +2304,19 @@ print_statfs(const struct syscallname *name,
|
||||
print_pointer(arg1, 1);
|
||||
print_syscall_epilogue(name);
|
||||
}
|
||||
#define print_statfs64 print_statfs
|
||||
#endif
|
||||
|
||||
#ifdef TARGET_NR_statfs64
|
||||
static void
|
||||
print_statfs64(const struct syscallname *name,
|
||||
abi_long arg0, abi_long arg1, abi_long arg2,
|
||||
abi_long arg3, abi_long arg4, abi_long arg5)
|
||||
{
|
||||
print_syscall_prologue(name);
|
||||
print_string(arg0, 0);
|
||||
print_pointer(arg1, 1);
|
||||
print_syscall_epilogue(name);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef TARGET_NR_symlink
|
||||
|
||||
@@ -7286,6 +7286,9 @@ static inline int target_to_host_mlockall_arg(int arg)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (defined(TARGET_NR_stat64) || defined(TARGET_NR_lstat64) || \
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||||
defined(TARGET_NR_fstat64) || defined(TARGET_NR_fstatat64) || \
|
||||
defined(TARGET_NR_newfstatat))
|
||||
static inline abi_long host_to_target_stat64(void *cpu_env,
|
||||
abi_ulong target_addr,
|
||||
struct stat *host_st)
|
||||
@@ -7348,6 +7351,7 @@ static inline abi_long host_to_target_stat64(void *cpu_env,
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* ??? Using host futex calls even when target atomic operations
|
||||
are not really atomic probably breaks things. However implementing
|
||||
@@ -7996,8 +8000,15 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
{
|
||||
CPUState *cpu = ENV_GET_CPU(cpu_env);
|
||||
abi_long ret;
|
||||
#if defined(TARGET_NR_stat) || defined(TARGET_NR_stat64) \
|
||||
|| defined(TARGET_NR_lstat) || defined(TARGET_NR_lstat64) \
|
||||
|| defined(TARGET_NR_fstat) || defined(TARGET_NR_fstat64)
|
||||
struct stat st;
|
||||
#endif
|
||||
#if defined(TARGET_NR_statfs) || defined(TARGET_NR_statfs64) \
|
||||
|| defined(TARGET_NR_fstatfs)
|
||||
struct statfs stfs;
|
||||
#endif
|
||||
void *p;
|
||||
|
||||
#if defined(DEBUG_ERESTARTSYS)
|
||||
@@ -8365,9 +8376,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
case TARGET_NR_oldstat:
|
||||
goto unimplemented;
|
||||
#endif
|
||||
#ifdef TARGET_NR_lseek
|
||||
case TARGET_NR_lseek:
|
||||
ret = get_errno(lseek(arg1, arg2, arg3));
|
||||
break;
|
||||
#endif
|
||||
#if defined(TARGET_NR_getxpid) && defined(TARGET_ALPHA)
|
||||
/* Alpha specific */
|
||||
case TARGET_NR_getxpid:
|
||||
@@ -9251,6 +9264,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
ret = get_errno(sethostname(p, arg2));
|
||||
unlock_user(p, arg1, 0);
|
||||
break;
|
||||
#ifdef TARGET_NR_setrlimit
|
||||
case TARGET_NR_setrlimit:
|
||||
{
|
||||
int resource = target_to_host_resource(arg1);
|
||||
@@ -9264,6 +9278,8 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
ret = get_errno(setrlimit(resource, &rlim));
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
#ifdef TARGET_NR_getrlimit
|
||||
case TARGET_NR_getrlimit:
|
||||
{
|
||||
int resource = target_to_host_resource(arg1);
|
||||
@@ -9280,6 +9296,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
}
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
case TARGET_NR_getrusage:
|
||||
{
|
||||
struct rusage rusage;
|
||||
@@ -9644,15 +9661,19 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
ret = get_errno(munlockall());
|
||||
break;
|
||||
#endif
|
||||
#ifdef TARGET_NR_truncate
|
||||
case TARGET_NR_truncate:
|
||||
if (!(p = lock_user_string(arg1)))
|
||||
goto efault;
|
||||
ret = get_errno(truncate(p, arg2));
|
||||
unlock_user(p, arg1, 0);
|
||||
break;
|
||||
#endif
|
||||
#ifdef TARGET_NR_ftruncate
|
||||
case TARGET_NR_ftruncate:
|
||||
ret = get_errno(ftruncate(arg1, arg2));
|
||||
break;
|
||||
#endif
|
||||
case TARGET_NR_fchmod:
|
||||
ret = get_errno(fchmod(arg1, arg2));
|
||||
break;
|
||||
@@ -9688,6 +9709,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
case TARGET_NR_profil:
|
||||
goto unimplemented;
|
||||
#endif
|
||||
#ifdef TARGET_NR_statfs
|
||||
case TARGET_NR_statfs:
|
||||
if (!(p = lock_user_string(arg1)))
|
||||
goto efault;
|
||||
@@ -9719,9 +9741,12 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
unlock_user_struct(target_stfs, arg2, 1);
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
#ifdef TARGET_NR_fstatfs
|
||||
case TARGET_NR_fstatfs:
|
||||
ret = get_errno(fstatfs(arg1, &stfs));
|
||||
goto convert_statfs;
|
||||
#endif
|
||||
#ifdef TARGET_NR_statfs64
|
||||
case TARGET_NR_statfs64:
|
||||
if (!(p = lock_user_string(arg1)))
|
||||
@@ -9969,6 +9994,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
unlock_user(p, arg1, 0);
|
||||
goto do_stat;
|
||||
#endif
|
||||
#ifdef TARGET_NR_fstat
|
||||
case TARGET_NR_fstat:
|
||||
{
|
||||
ret = get_errno(fstat(arg1, &st));
|
||||
@@ -9998,6 +10024,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
}
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
#ifdef TARGET_NR_olduname
|
||||
case TARGET_NR_olduname:
|
||||
goto unimplemented;
|
||||
@@ -11004,6 +11031,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
break;
|
||||
|
||||
#ifdef CONFIG_SENDFILE
|
||||
#ifdef TARGET_NR_sendfile
|
||||
case TARGET_NR_sendfile:
|
||||
{
|
||||
off_t *offp = NULL;
|
||||
@@ -11024,6 +11052,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
|
||||
}
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#ifdef TARGET_NR_sendfile64
|
||||
case TARGET_NR_sendfile64:
|
||||
{
|
||||
|
||||
+11
-2
@@ -2693,8 +2693,17 @@ The binary format is detected automatically.
|
||||
@command{qemu-microblaze} TODO.
|
||||
|
||||
@cindex user mode (MIPS)
|
||||
@command{qemu-mips} TODO.
|
||||
@command{qemu-mipsel} TODO.
|
||||
@command{qemu-mips} executes 32-bit big endian MIPS binaries (MIPS O32 ABI).
|
||||
|
||||
@command{qemu-mipsel} executes 32-bit little endian MIPS binaries (MIPS O32 ABI).
|
||||
|
||||
@command{qemu-mips64} executes 64-bit big endian MIPS binaries (MIPS N64 ABI).
|
||||
|
||||
@command{qemu-mips64el} executes 64-bit little endian MIPS binaries (MIPS N64 ABI).
|
||||
|
||||
@command{qemu-mipsn32} executes 32-bit big endian MIPS binaries (MIPS N32 ABI).
|
||||
|
||||
@command{qemu-mipsn32el} executes 32-bit little endian MIPS binaries (MIPS N32 ABI).
|
||||
|
||||
@cindex user mode (NiosII)
|
||||
@command{qemu-nios2} TODO.
|
||||
|
||||
+89
-69
@@ -323,6 +323,7 @@ struct CPUMIPSState {
|
||||
target_ulong CP0_BadVAddr;
|
||||
uint32_t CP0_BadInstr;
|
||||
uint32_t CP0_BadInstrP;
|
||||
uint32_t CP0_BadInstrX;
|
||||
int32_t CP0_Count;
|
||||
target_ulong CP0_EntryHi;
|
||||
#define CP0EnHi_EHINV 10
|
||||
@@ -388,26 +389,27 @@ struct CPUMIPSState {
|
||||
target_ulong CP0_CMGCRBase;
|
||||
int32_t CP0_Config0;
|
||||
#define CP0C0_M 31
|
||||
#define CP0C0_K23 28
|
||||
#define CP0C0_KU 25
|
||||
#define CP0C0_K23 28 /* 30..28 */
|
||||
#define CP0C0_KU 25 /* 27..25 */
|
||||
#define CP0C0_MDU 20
|
||||
#define CP0C0_MM 18
|
||||
#define CP0C0_BM 16
|
||||
#define CP0C0_Impl 16 /* 24..16 */
|
||||
#define CP0C0_BE 15
|
||||
#define CP0C0_AT 13
|
||||
#define CP0C0_AR 10
|
||||
#define CP0C0_MT 7
|
||||
#define CP0C0_AT 13 /* 14..13 */
|
||||
#define CP0C0_AR 10 /* 12..10 */
|
||||
#define CP0C0_MT 7 /* 9..7 */
|
||||
#define CP0C0_VI 3
|
||||
#define CP0C0_K0 0
|
||||
#define CP0C0_K0 0 /* 2..0 */
|
||||
int32_t CP0_Config1;
|
||||
#define CP0C1_M 31
|
||||
#define CP0C1_MMU 25
|
||||
#define CP0C1_IS 22
|
||||
#define CP0C1_IL 19
|
||||
#define CP0C1_IA 16
|
||||
#define CP0C1_DS 13
|
||||
#define CP0C1_DL 10
|
||||
#define CP0C1_DA 7
|
||||
#define CP0C1_MMU 25 /* 30..25 */
|
||||
#define CP0C1_IS 22 /* 24..22 */
|
||||
#define CP0C1_IL 19 /* 21..19 */
|
||||
#define CP0C1_IA 16 /* 18..16 */
|
||||
#define CP0C1_DS 13 /* 15..13 */
|
||||
#define CP0C1_DL 10 /* 12..10 */
|
||||
#define CP0C1_DA 7 /* 9..7 */
|
||||
#define CP0C1_C2 6
|
||||
#define CP0C1_MD 5
|
||||
#define CP0C1_PC 4
|
||||
@@ -417,67 +419,85 @@ struct CPUMIPSState {
|
||||
#define CP0C1_FP 0
|
||||
int32_t CP0_Config2;
|
||||
#define CP0C2_M 31
|
||||
#define CP0C2_TU 28
|
||||
#define CP0C2_TS 24
|
||||
#define CP0C2_TL 20
|
||||
#define CP0C2_TA 16
|
||||
#define CP0C2_SU 12
|
||||
#define CP0C2_SS 8
|
||||
#define CP0C2_SL 4
|
||||
#define CP0C2_SA 0
|
||||
#define CP0C2_TU 28 /* 30..28 */
|
||||
#define CP0C2_TS 24 /* 27..24 */
|
||||
#define CP0C2_TL 20 /* 23..20 */
|
||||
#define CP0C2_TA 16 /* 19..16 */
|
||||
#define CP0C2_SU 12 /* 15..12 */
|
||||
#define CP0C2_SS 8 /* 11..8 */
|
||||
#define CP0C2_SL 4 /* 7..4 */
|
||||
#define CP0C2_SA 0 /* 3..0 */
|
||||
int32_t CP0_Config3;
|
||||
#define CP0C3_M 31
|
||||
#define CP0C3_BPG 30
|
||||
#define CP0C3_CMGCR 29
|
||||
#define CP0C3_MSAP 28
|
||||
#define CP0C3_BP 27
|
||||
#define CP0C3_BI 26
|
||||
#define CP0C3_SC 25
|
||||
#define CP0C3_IPLW 21
|
||||
#define CP0C3_MMAR 18
|
||||
#define CP0C3_MCU 17
|
||||
#define CP0C3_ISA_ON_EXC 16
|
||||
#define CP0C3_ISA 14
|
||||
#define CP0C3_ULRI 13
|
||||
#define CP0C3_RXI 12
|
||||
#define CP0C3_DSP2P 11
|
||||
#define CP0C3_DSPP 10
|
||||
#define CP0C3_LPA 7
|
||||
#define CP0C3_VEIC 6
|
||||
#define CP0C3_VInt 5
|
||||
#define CP0C3_SP 4
|
||||
#define CP0C3_CDMM 3
|
||||
#define CP0C3_MT 2
|
||||
#define CP0C3_SM 1
|
||||
#define CP0C3_TL 0
|
||||
#define CP0C3_M 31
|
||||
#define CP0C3_BPG 30
|
||||
#define CP0C3_CMGCR 29
|
||||
#define CP0C3_MSAP 28
|
||||
#define CP0C3_BP 27
|
||||
#define CP0C3_BI 26
|
||||
#define CP0C3_SC 25
|
||||
#define CP0C3_PW 24
|
||||
#define CP0C3_VZ 23
|
||||
#define CP0C3_IPLV 21 /* 22..21 */
|
||||
#define CP0C3_MMAR 18 /* 20..18 */
|
||||
#define CP0C3_MCU 17
|
||||
#define CP0C3_ISA_ON_EXC 16
|
||||
#define CP0C3_ISA 14 /* 15..14 */
|
||||
#define CP0C3_ULRI 13
|
||||
#define CP0C3_RXI 12
|
||||
#define CP0C3_DSP2P 11
|
||||
#define CP0C3_DSPP 10
|
||||
#define CP0C3_CTXTC 9
|
||||
#define CP0C3_ITL 8
|
||||
#define CP0C3_LPA 7
|
||||
#define CP0C3_VEIC 6
|
||||
#define CP0C3_VInt 5
|
||||
#define CP0C3_SP 4
|
||||
#define CP0C3_CDMM 3
|
||||
#define CP0C3_MT 2
|
||||
#define CP0C3_SM 1
|
||||
#define CP0C3_TL 0
|
||||
int32_t CP0_Config4;
|
||||
int32_t CP0_Config4_rw_bitmask;
|
||||
#define CP0C4_M 31
|
||||
#define CP0C4_IE 29
|
||||
#define CP0C4_AE 28
|
||||
#define CP0C4_KScrExist 16
|
||||
#define CP0C4_MMUExtDef 14
|
||||
#define CP0C4_FTLBPageSize 8
|
||||
#define CP0C4_FTLBWays 4
|
||||
#define CP0C4_FTLBSets 0
|
||||
#define CP0C4_MMUSizeExt 0
|
||||
#define CP0C4_M 31
|
||||
#define CP0C4_IE 29 /* 30..29 */
|
||||
#define CP0C4_AE 28
|
||||
#define CP0C4_VTLBSizeExt 24 /* 27..24 */
|
||||
#define CP0C4_KScrExist 16
|
||||
#define CP0C4_MMUExtDef 14
|
||||
#define CP0C4_FTLBPageSize 8 /* 12..8 */
|
||||
/* bit layout if MMUExtDef=1 */
|
||||
#define CP0C4_MMUSizeExt 0 /* 7..0 */
|
||||
/* bit layout if MMUExtDef=2 */
|
||||
#define CP0C4_FTLBWays 4 /* 7..4 */
|
||||
#define CP0C4_FTLBSets 0 /* 3..0 */
|
||||
int32_t CP0_Config5;
|
||||
int32_t CP0_Config5_rw_bitmask;
|
||||
#define CP0C5_M 31
|
||||
#define CP0C5_K 30
|
||||
#define CP0C5_CV 29
|
||||
#define CP0C5_EVA 28
|
||||
#define CP0C5_MSAEn 27
|
||||
#define CP0C5_XNP 13
|
||||
#define CP0C5_UFE 9
|
||||
#define CP0C5_FRE 8
|
||||
#define CP0C5_VP 7
|
||||
#define CP0C5_SBRI 6
|
||||
#define CP0C5_MVH 5
|
||||
#define CP0C5_LLB 4
|
||||
#define CP0C5_MRP 3
|
||||
#define CP0C5_UFR 2
|
||||
#define CP0C5_NFExists 0
|
||||
#define CP0C5_M 31
|
||||
#define CP0C5_K 30
|
||||
#define CP0C5_CV 29
|
||||
#define CP0C5_EVA 28
|
||||
#define CP0C5_MSAEn 27
|
||||
#define CP0C5_PMJ 23 /* 25..23 */
|
||||
#define CP0C5_WR2 22
|
||||
#define CP0C5_NMS 21
|
||||
#define CP0C5_ULS 20
|
||||
#define CP0C5_XPA 19
|
||||
#define CP0C5_CRCP 18
|
||||
#define CP0C5_MI 17
|
||||
#define CP0C5_GI 15 /* 16..15 */
|
||||
#define CP0C5_CA2 14
|
||||
#define CP0C5_XNP 13
|
||||
#define CP0C5_DEC 11
|
||||
#define CP0C5_L2C 10
|
||||
#define CP0C5_UFE 9
|
||||
#define CP0C5_FRE 8
|
||||
#define CP0C5_VP 7
|
||||
#define CP0C5_SBRI 6
|
||||
#define CP0C5_MVH 5
|
||||
#define CP0C5_LLB 4
|
||||
#define CP0C5_MRP 3
|
||||
#define CP0C5_UFR 2
|
||||
#define CP0C5_NFExists 0
|
||||
int32_t CP0_Config6;
|
||||
int32_t CP0_Config7;
|
||||
uint64_t CP0_MAAR[MIPS_MAAR_MAX];
|
||||
|
||||
@@ -502,7 +502,9 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
|
||||
break;
|
||||
}
|
||||
/* Raise exception */
|
||||
env->CP0_BadVAddr = address;
|
||||
if (!(env->hflags & MIPS_HFLAG_DM)) {
|
||||
env->CP0_BadVAddr = address;
|
||||
}
|
||||
env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
|
||||
((address >> 9) & 0x007ffff0);
|
||||
env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
|
||||
|
||||
@@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
|
||||
|
||||
const VMStateDescription vmstate_mips_cpu = {
|
||||
.name = "cpu",
|
||||
.version_id = 10,
|
||||
.minimum_version_id = 10,
|
||||
.version_id = 11,
|
||||
.minimum_version_id = 11,
|
||||
.post_load = cpu_post_load,
|
||||
.fields = (VMStateField[]) {
|
||||
/* Active TC */
|
||||
@@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu = {
|
||||
VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
|
||||
VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
|
||||
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
|
||||
VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
|
||||
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
|
||||
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
|
||||
|
||||
@@ -271,7 +271,9 @@ static inline hwaddr do_translate_address(CPUMIPSState *env,
|
||||
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
|
||||
{ \
|
||||
if (arg & almask) { \
|
||||
env->CP0_BadVAddr = arg; \
|
||||
if (!(env->hflags & MIPS_HFLAG_DM)) { \
|
||||
env->CP0_BadVAddr = arg; \
|
||||
} \
|
||||
do_raise_exception(env, EXCP_AdEL, GETPC()); \
|
||||
} \
|
||||
env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
|
||||
@@ -291,7 +293,9 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
|
||||
target_long tmp; \
|
||||
\
|
||||
if (arg2 & almask) { \
|
||||
env->CP0_BadVAddr = arg2; \
|
||||
if (!(env->hflags & MIPS_HFLAG_DM)) { \
|
||||
env->CP0_BadVAddr = arg2; \
|
||||
} \
|
||||
do_raise_exception(env, EXCP_AdES, GETPC()); \
|
||||
} \
|
||||
if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
|
||||
@@ -2437,7 +2441,9 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
|
||||
int error_code = 0;
|
||||
int excp;
|
||||
|
||||
env->CP0_BadVAddr = addr;
|
||||
if (!(env->hflags & MIPS_HFLAG_DM)) {
|
||||
env->CP0_BadVAddr = addr;
|
||||
}
|
||||
|
||||
if (access_type == MMU_DATA_STORE) {
|
||||
excp = EXCP_AdES;
|
||||
|
||||
+309
-65
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user