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Merge tag 'pull-ppc-20220718' of https://gitlab.com/danielhb/qemu into staging

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ppc patch queue for 2022-07-18:

This is the last ppc patch queue before the soft freeze. It contains new
TCG instructions and changes, a tricky bug fix in kvmppc_find_cpu_dt()
and other enhancements/fixes.

- tcg and target/ppc:
  - move instructions to decodetree
  - check for bad Radix configs
  - ISA 3.00 tlbie[l]
  - fix gen_*_exception error codes
  - check fortb_env != 0 when printing TBU/TBL/DECR
- fix kvmppc_find_cpu_dt() returning the wrong CPU DT path when there's a
'clock-frequency' property in the root node
- spapr, e500: pass a random seed in /chosen/rng-seed
- all boards: allocate IRQ lines with qdev_init_gpio_in()

# gpg: Signature made Mon 18 Jul 2022 18:19:58 BST
# gpg:                using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28  3819 3CD9 CA96 DE03 3164

* tag 'pull-ppc-20220718' of https://gitlab.com/danielhb/qemu: (30 commits)
  target/ppc: Check page dir/table base alignment
  target/ppc: Improve Radix xlate level validation
  ppc: Check partition and process table alignment
  target/ppc: check tb_env != 0 before printing TBU/TBL/DECR
  target/ppc: Implement slbiag
  target/ppc: Move slbsync to decodetree
  target/ppc: Move slbfee to decodetree
  target/ppc: Move slbmfee to decodetree
  target/ppc: Move slbmfev to decodetree
  target/ppc: Move slbmte to decodetree
  target/ppc: Move slbia to decodetree
  target/ppc: Move slbieg to decodetree
  target/ppc: Move slbie to decodetree
  target/ppc: add macros to check privilege level
  target/ppc: receive DisasContext explicitly in GEN_PRIV
  target/ppc: Implement ISA 3.00 tlbie[l]
  target/ppc: Move tlbie[l] to decode tree
  target/ppc: fix exception error code in spr_write_excp_vector
  target/ppc: fix PMU Group A register read/write exceptions
  target/ppc: fix exception error code in helper_{load, store}_dcr
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2022-07-18 19:27:25 +01:00
parent 7823789731 d2066bc50d
commit b8bb9bbf46
32 changed files with 850 additions and 473 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/intc/xics.c
+6 -4
View File
@@ -301,23 +301,25 @@ void icp_reset(ICPState *icp)
static void icp_realize(DeviceState *dev, Error **errp)
{
ICPState *icp = ICP(dev);
PowerPCCPU *cpu;
CPUPPCState *env;
Error *err = NULL;
assert(icp->xics);
assert(icp->cs);
env = &POWERPC_CPU(icp->cs)->env;
cpu = POWERPC_CPU(icp->cs);
env = &cpu->env;
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_POWER7:
icp->output = env->irq_inputs[POWER7_INPUT_INT];
icp->output = qdev_get_gpio_in(DEVICE(cpu), POWER7_INPUT_INT);
break;
case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
icp->output = env->irq_inputs[POWER9_INPUT_INT];
icp->output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT);
break;
case PPC_FLAGS_INPUT_970:
icp->output = env->irq_inputs[PPC970_INPUT_INT];
icp->output = qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_INT);
break;
default:
hw/intc/xive.c
+2 -2
View File
@@ -695,8 +695,8 @@ static void xive_tctx_realize(DeviceState *dev, Error **errp)
env = &cpu->env;
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_POWER9:
tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT];
tctx->os_output = env->irq_inputs[POWER9_INPUT_INT];
tctx->hv_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_HINT);
tctx->os_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT);
break;
default:
hw/ppc/e500.c
+9 -4
View File
@@ -17,6 +17,7 @@
#include "qemu/osdep.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qemu/guest-random.h"
#include "qapi/error.h"
#include "e500.h"
#include "e500-ccsr.h"
@@ -346,6 +347,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
};
const char *dtb_file = machine->dtb;
const char *toplevel_compat = machine->dt_compatible;
uint8_t rng_seed[32];
if (dtb_file) {
char *filename;
@@ -403,6 +405,9 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
if (ret < 0)
fprintf(stderr, "couldn't set /chosen/bootargs\n");
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
if (kvm_enabled()) {
/* Read out host's frequencies */
clock_freq = kvmppc_get_clockfreq();
@@ -861,7 +866,6 @@ void ppce500_init(MachineState *machine)
for (i = 0; i < smp_cpus; i++) {
PowerPCCPU *cpu;
CPUState *cs;
qemu_irq *input;
cpu = POWERPC_CPU(object_new(machine->cpu_type));
env = &cpu->env;
@@ -885,9 +889,10 @@ void ppce500_init(MachineState *machine)
firstenv = env;
}
input = (qemu_irq *)env->irq_inputs;
irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
irqs[i].irq[OPENPIC_OUTPUT_INT] =
qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_INT);
irqs[i].irq[OPENPIC_OUTPUT_CINT] =
qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_CINT);
env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
hw/ppc/mac_newworld.c
+8 -8
View File
@@ -262,30 +262,30 @@ static void ppc_core99_init(MachineState *machine)
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT);
openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT);
openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_MCP);
/* Not connected ? */
openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
/* Check this */
openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_HRESET);
break;
#if defined(TARGET_PPC64)
case PPC_FLAGS_INPUT_970:
openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_INT);
openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_INT);
openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_MCP);
/* Not connected ? */
openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
/* Check this */
openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_HRESET);
break;
#endif /* defined(TARGET_PPC64) */
default:
hw/ppc/mac_oldworld.c
+1 -1
View File
@@ -271,7 +271,7 @@ static void ppc_heathrow_init(MachineState *machine)
case PPC_FLAGS_INPUT_6xx:
/* XXX: we register only 1 output pin for heathrow PIC */
qdev_connect_gpio_out(pic_dev, 0,
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT));
break;
default:
error_report("Bus model not supported on OldWorld Mac machine");
hw/ppc/pegasos2.c
+1 -1
View File
@@ -155,7 +155,7 @@ static void pegasos2_init(MachineState *machine)
/* Marvell Discovery II system controller */
pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]));
qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT)));
pci_bus = mv64361_get_pci_bus(pm->mv, 1);
/* VIA VT8231 South Bridge (multifunction PCI device) */
hw/ppc/ppc.c
+6 -24
View File
@@ -154,10 +154,7 @@ static void ppc6xx_set_irq(void *opaque, int pin, int level)
void ppc6xx_irq_init(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
PPC6xx_INPUT_NB);
qdev_init_gpio_in(DEVICE(cpu), ppc6xx_set_irq, PPC6xx_INPUT_NB);
}
#if defined(TARGET_PPC64)
@@ -234,10 +231,7 @@ static void ppc970_set_irq(void *opaque, int pin, int level)
void ppc970_irq_init(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu,
PPC970_INPUT_NB);
qdev_init_gpio_in(DEVICE(cpu), ppc970_set_irq, PPC970_INPUT_NB);
}
/* POWER7 internal IRQ controller */
@@ -260,10 +254,7 @@ static void power7_set_irq(void *opaque, int pin, int level)
void ppcPOWER7_irq_init(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
POWER7_INPUT_NB);
qdev_init_gpio_in(DEVICE(cpu), power7_set_irq, POWER7_INPUT_NB);
}
/* POWER9 internal IRQ controller */
@@ -292,10 +283,7 @@ static void power9_set_irq(void *opaque, int pin, int level)
void ppcPOWER9_irq_init(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
env->irq_inputs = (void **)qemu_allocate_irqs(&power9_set_irq, cpu,
POWER9_INPUT_NB);
qdev_init_gpio_in(DEVICE(cpu), power9_set_irq, POWER9_INPUT_NB);
}
#endif /* defined(TARGET_PPC64) */
@@ -431,10 +419,7 @@ static void ppc40x_set_irq(void *opaque, int pin, int level)
void ppc40x_irq_init(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
cpu, PPC40x_INPUT_NB);
qdev_init_gpio_in(DEVICE(cpu), ppc40x_set_irq, PPC40x_INPUT_NB);
}
/* PowerPC E500 internal IRQ controller */
@@ -489,10 +474,7 @@ static void ppce500_set_irq(void *opaque, int pin, int level)
void ppce500_irq_init(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
cpu, PPCE500_INPUT_NB);
qdev_init_gpio_in(DEVICE(cpu), ppce500_set_irq, PPCE500_INPUT_NB);
}
/* Enable or Disable the E500 EPR capability */
hw/ppc/ppc405_uc.c
+2 -2
View File
@@ -1470,9 +1470,9 @@ PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
sysbus_realize_and_unref(uicsbd, &error_fatal);
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
*uicdevp = uicdev;
hw/ppc/ppc440_bamboo.c
+2 -2
View File
@@ -200,9 +200,9 @@ static void bamboo_init(MachineState *machine)
sysbus_realize_and_unref(uicsbd, &error_fatal);
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
memset(ram_bases, 0, sizeof(ram_bases));
hw/ppc/prep.c
+1 -1
View File
@@ -275,7 +275,7 @@ static void ibm_40p_init(MachineState *machine)
/* PCI -> ISA bridge */
i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
qdev_connect_gpio_out(i82378_dev, 0,
cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT));
sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
hw/ppc/prep_systemio.c
+1 -1
View File
@@ -262,7 +262,7 @@ static void prep_systemio_realize(DeviceState *dev, Error **errp)
qemu_set_irq(s->non_contiguous_io_map_irq,
s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS);
cpu = POWERPC_CPU(first_cpu);
s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
s->softreset_irq = qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_HRESET);
isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s,
"systemio800");
hw/ppc/sam460ex.c
+2 -2
View File
@@ -334,9 +334,9 @@ static void sam460ex_init(MachineState *machine)
if (i == 0) {
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
} else {
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(uic[0], input_ints[i]));
hw/ppc/spapr.c
+10
View File
@@ -27,6 +27,7 @@
#include "qemu/osdep.h"
#include "qemu/datadir.h"
#include "qemu/memalign.h"
#include "qemu/guest-random.h"
#include "qapi/error.h"
#include "qapi/qapi-events-machine.h"
#include "qapi/qapi-events-qdev.h"
@@ -1014,6 +1015,7 @@ static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset)
{
MachineState *machine = MACHINE(spapr);
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
uint8_t rng_seed[32];
int chosen;
_FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
@@ -1091,6 +1093,9 @@ static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset)
spapr_dt_ov5_platform_support(spapr, fdt, chosen);
}
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
_FDT(fdt_setprop(fdt, chosen, "rng-seed", rng_seed, sizeof(rng_seed)));
_FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5"));
}
@@ -1331,6 +1336,11 @@ static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
patb = spapr->nested_ptcr & PTCR_PATB;
pats = spapr->nested_ptcr & PTCR_PATS;
/* Check if partition table is properly aligned */
if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
return false;
}
/* Calculate number of entries */
pats = 1ull << (pats + 12 - 4);
if (pats <= lpid) {
hw/ppc/spapr_hcall.c
+9
View File
@@ -920,6 +920,7 @@ static target_ulong h_register_process_table(PowerPCCPU *cpu,
target_ulong page_size = args[2];
target_ulong table_size = args[3];
target_ulong update_lpcr = 0;
target_ulong table_byte_size;
uint64_t cproc;
if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */
@@ -927,6 +928,14 @@ static target_ulong h_register_process_table(PowerPCCPU *cpu,
}
if (flags & FLAG_MODIFY) {
if (flags & FLAG_REGISTER) {
/* Check process table alignment */
table_byte_size = 1ULL << (table_size + 12);
if (proc_tbl & (table_byte_size - 1)) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: process table not properly aligned: proc_tbl 0x"
TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n",
__func__, proc_tbl, table_byte_size);
}
if (flags & FLAG_RADIX) { /* Register new RADIX process table */
if (proc_tbl & 0xfff || proc_tbl >> 60) {
return H_P2;
hw/ppc/virtex_ml507.c
+5 -5
View File
@@ -111,9 +111,9 @@ static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
sysbus_realize_and_unref(uicsbd, &error_fatal);
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* This board doesn't wire anything up to the inputs of the UIC. */
return cpu;
@@ -213,7 +213,7 @@ static void virtex_init(MachineState *machine)
CPUPPCState *env;
hwaddr ram_base = 0;
DriveInfo *dinfo;
qemu_irq irq[32], *cpu_irq;
qemu_irq irq[32], cpu_irq;
int kernel_size;
int i;
@@ -236,12 +236,12 @@ static void virtex_init(MachineState *machine)
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
cpu_irq = qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT);
dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr", 0);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
}
target/ppc/cpu.h
+2 -5
View File
@@ -1184,7 +1184,6 @@ struct CPUArchState {
* by recent Book3s compatible CPUs (POWER7 and newer).
*/
uint32_t irq_input_state;
void **irq_inputs;
target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
target_ulong excp_prefix;
@@ -2215,8 +2214,6 @@ enum {
PPC_DCR = 0x1000000000000000ULL,
/* DCR extended accesse */
PPC_DCRX = 0x2000000000000000ULL,
/* user-mode DCR access, implemented in PowerPC 460 */
PPC_DCRUX = 0x4000000000000000ULL,
/* popcntw and popcntd instructions */
PPC_POPCNTWD = 0x8000000000000000ULL,
@@ -2240,8 +2237,8 @@ enum {
| PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
| PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
| PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
| PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
| PPC_POPCNTWD | PPC_CILDST)
| PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_POPCNTWD \
| PPC_CILDST)
/* extended type values */
target/ppc/cpu_init.c
+10 -17
View File
@@ -6373,7 +6373,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBSYNC |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD |
@@ -6591,7 +6591,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBSYNC |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD |
@@ -6678,7 +6678,6 @@ static void init_ppc_proc(PowerPCCPU *cpu)
#if !defined(CONFIG_USER_ONLY)
int i;
env->irq_inputs = NULL;
/* Set all exception vectors to an invalid address */
for (i = 0; i < POWERPC_EXCP_NB; i++) {
env->excp_vectors[i] = (target_ulong)(-1ULL);
@@ -6808,10 +6807,6 @@ static void init_ppc_proc(PowerPCCPU *cpu)
/* Pre-compute some useful values */
env->tlb_per_way = env->nb_tlb / env->nb_ways;
}
if (env->irq_inputs == NULL) {
warn_report("no internal IRQ controller registered."
" Attempt QEMU to crash very soon !");
}
#endif
if (env->check_pow == NULL) {
warn_report("no power management check handler registered."
@@ -7476,17 +7471,15 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
"%08x iidx %d didx %d\n",
env->msr, env->spr[SPR_HID0], env->hflags,
cpu_mmu_index(env, true), cpu_mmu_index(env, false));
#if !defined(NO_TIMER_DUMP)
qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
#if !defined(CONFIG_USER_ONLY)
" DECR " TARGET_FMT_lu
#endif
"\n",
cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
#if !defined(CONFIG_USER_ONLY)
, cpu_ppc_load_decr(env)
#endif
);
if (env->tb_env) {
qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
" DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
}
#else
qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
cpu_ppc_load_tbl(env));
#endif
for (i = 0; i < 32; i++) {
if ((i & (RGPL - 1)) == 0) {
target/ppc/helper.h
+11 -8
View File
@@ -674,13 +674,16 @@ DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_3(SLBIAG, TCG_CALL_NO_RWG, void, env, tl, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_NO_RWG, void, env, tl, tl)
@@ -694,10 +697,10 @@ DEF_HELPER_2(book3s_msgclr, void, env, tl)
DEF_HELPER_4(dlmzb, tl, env, tl, tl, i32)
#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_2(rac, tl, env, tl)
#endif
DEF_HELPER_2(load_dcr, tl, env, tl)
DEF_HELPER_3(store_dcr, void, env, tl, tl)
#endif
DEF_HELPER_2(load_dump_spr, void, env, i32)
DEF_HELPER_2(store_dump_spr, void, env, i32)
target/ppc/insn32.decode
+34
View File
@@ -146,6 +146,15 @@
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
&X_ih ih:uint8_t
@X_ih ...... .. ih:3 ..... ..... .......... . &X_ih
&X_rb rb
@X_rb ...... ..... ..... rb:5 .......... . &X_rb
&X_rs_l rs l:bool
@X_rs_l ...... rs:5 .... l:1 ..... .......... . &X_rs_l
&X_uim5 xt uim:uint8_t
@X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt=%x_xt
@@ -856,3 +865,28 @@ VMODSD 000100 ..... ..... ..... 11111001011 @VX
VMODUD 000100 ..... ..... ..... 11011001011 @VX
VMODSQ 000100 ..... ..... ..... 11100001011 @VX
VMODUQ 000100 ..... ..... ..... 11000001011 @VX
## SLB Management Instructions
SLBIE 011111 ----- ----- ..... 0110110010 - @X_rb
SLBIEG 011111 ..... ----- ..... 0111010010 - @X_tb
SLBIA 011111 --... ----- ----- 0111110010 - @X_ih
SLBIAG 011111 ..... ----. ----- 1101010010 - @X_rs_l
SLBMTE 011111 ..... ----- ..... 0110010010 - @X_tb
SLBMFEV 011111 ..... ----- ..... 1101010011 - @X_tb
SLBMFEE 011111 ..... ----- ..... 1110010011 - @X_tb
SLBFEE 011111 ..... ----- ..... 1111010011 1 @X_tb
SLBSYNC 011111 ----- ----- ----- 0101010010 -
## TLB Management Instructions
&X_tlbie rb rs ric prs:bool r:bool
@X_tlbie ...... rs:5 - ric:2 prs:1 r:1 rb:5 .......... - &X_tlbie
TLBIE 011111 ..... - .. . . ..... 0100110010 - @X_tlbie
TLBIEL 011111 ..... - .. . . ..... 0100010010 - @X_tlbie
target/ppc/kvm.c
+6
View File
@@ -1877,6 +1877,12 @@ static int kvmppc_find_cpu_dt(char *buf, int buf_len)
buf[0] = '\0';
while ((dirp = readdir(dp)) != NULL) {
FILE *f;
/* Don't accidentally read from the current and parent directories */
if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) {
continue;
}
snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
dirp->d_name);
f = fopen(buf, "r");

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