mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
ARM VFP support (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1309 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
@@ -15,6 +15,7 @@ version 0.6.2:
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- PC parallel port support (Mark Jonckheere)
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- initial SPARC64 support (Blue Swirl)
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- armv5te user mode support (Paul Brook)
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- ARM VFP support (Paul Brook)
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version 0.6.1:
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@@ -259,6 +259,10 @@ ifeq ($(TARGET_BASE_ARCH), sparc)
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LIBOBJS+= op_helper.o helper.o
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endif
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ifeq ($(TARGET_BASE_ARCH), arm)
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LIBOBJS+= op_helper.o
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endif
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# NOTE: the disassembler code is only needed for debugging
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LIBOBJS+=disas.o
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ifeq ($(findstring i386, $(TARGET_ARCH) $(ARCH)),i386)
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+3
-1
@@ -346,7 +346,8 @@ int cpu_exec(CPUState *env1)
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cs_base = env->segs[R_CS].base;
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pc = cs_base + env->eip;
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#elif defined(TARGET_ARM)
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flags = env->thumb;
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flags = env->thumb | (env->vfp.vec_len << 1)
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| (env->vfp.vec_stride << 4);
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cs_base = 0;
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pc = env->regs[15];
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#elif defined(TARGET_SPARC)
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@@ -619,6 +620,7 @@ int cpu_exec(CPUState *env1)
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#endif
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#elif defined(TARGET_ARM)
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env->cpsr = compute_cpsr();
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/* XXX: Save/restore host fpu exception state?. */
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#elif defined(TARGET_SPARC)
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#elif defined(TARGET_PPC)
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#else
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@@ -29,6 +29,14 @@
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#define EXCP_PREFETCH_ABORT 3
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#define EXCP_DATA_ABORT 4
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/* We currently assume float and double are IEEE single and double
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precision respectively.
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Doing runtime conversions is tricky because VFP registers may contain
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integer values (eg. as the result of a FTOSI instruction).
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A double precision register load/store must also load/store the
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corresponding single precision pair, although it is undefined how
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these overlap. */
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typedef struct CPUARMState {
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uint32_t regs[16];
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uint32_t cpsr;
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@@ -50,6 +58,7 @@ typedef struct CPUARMState {
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int interrupt_request;
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struct TranslationBlock *current_tb;
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int user_mode_only;
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uint32_t address;
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/* in order to avoid passing too many arguments to the memory
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write helpers, we store some rarely used information in the CPU
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@@ -58,6 +67,25 @@ typedef struct CPUARMState {
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written */
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unsigned long mem_write_vaddr; /* target virtual addr at which the
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memory was written */
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/* VFP coprocessor state. */
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struct {
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union {
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float s[32];
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double d[16];
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} regs;
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/* We store these fpcsr fields separately for convenience. */
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int vec_len;
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int vec_stride;
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uint32_t fpscr;
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/* Temporary variables if we don't have spare fp regs. */
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float tmp0s, tmp1s;
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double tmp0d, tmp1d;
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} vfp;
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/* user data */
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void *opaque;
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} CPUARMState;
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+28
-4
@@ -24,13 +24,16 @@ register uint32_t T0 asm(AREG1);
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register uint32_t T1 asm(AREG2);
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register uint32_t T2 asm(AREG3);
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/* TODO: Put these in FP regs on targets that have such things. */
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/* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */
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#define FT0s env->vfp.tmp0s
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#define FT1s env->vfp.tmp1s
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#define FT0d env->vfp.tmp0d
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#define FT1d env->vfp.tmp1d
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#include "cpu.h"
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#include "exec-all.h"
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void cpu_lock(void);
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void cpu_unlock(void);
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void cpu_loop_exit(void);
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/* Implemented CPSR bits. */
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#define CACHED_CPSR_BITS 0xf8000000
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static inline int compute_cpsr(void)
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@@ -51,3 +54,24 @@ static inline void regs_to_env(void)
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int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu);
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/* In op_helper.c */
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void cpu_lock(void);
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void cpu_unlock(void);
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void cpu_loop_exit(void);
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void raise_exception(int);
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void do_vfp_abss(void);
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void do_vfp_absd(void);
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void do_vfp_negs(void);
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void do_vfp_negd(void);
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void do_vfp_sqrts(void);
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void do_vfp_sqrtd(void);
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void do_vfp_cmps(void);
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void do_vfp_cmpd(void);
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void do_vfp_cmpes(void);
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void do_vfp_cmped(void);
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void do_vfp_set_fpscr(void);
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void do_vfp_get_fpscr(void);
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+249
-6
@@ -2,6 +2,7 @@
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* ARM micro operations
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2005 CodeSourcery, LLC
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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@@ -857,17 +858,259 @@ void OPPROTO op_undef_insn(void)
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cpu_loop_exit();
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}
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/* thread support */
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/* VFP support. We follow the convention used for VFP instrunctions:
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Single precition routines have a "s" suffix, double precision a
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"d" suffix. */
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
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#define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void)
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void cpu_lock(void)
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#define VFP_BINOP(name, op) \
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VFP_OP(name, s) \
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{ \
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FT0s = FT0s op FT1s; \
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} \
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VFP_OP(name, d) \
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{ \
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FT0d = FT0d op FT1d; \
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}
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VFP_BINOP(add, +)
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VFP_BINOP(sub, -)
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VFP_BINOP(mul, *)
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VFP_BINOP(div, /)
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#undef VFP_BINOP
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#define VFP_HELPER(name) \
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VFP_OP(name, s) \
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{ \
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do_vfp_##name##s(); \
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} \
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VFP_OP(name, d) \
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{ \
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do_vfp_##name##d(); \
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}
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VFP_HELPER(abs)
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VFP_HELPER(sqrt)
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VFP_HELPER(cmp)
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VFP_HELPER(cmpe)
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#undef VFP_HELPER
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/* XXX: Will this do the right thing for NANs. Should invert the signbit
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without looking at the rest of the value. */
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VFP_OP(neg, s)
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{
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spin_lock(&global_cpu_lock);
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FT0s = -FT0s;
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}
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void cpu_unlock(void)
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VFP_OP(neg, d)
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{
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spin_unlock(&global_cpu_lock);
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FT0d = -FT0d;
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}
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VFP_OP(F1_ld0, s)
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{
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FT1s = 0.0f;
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}
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VFP_OP(F1_ld0, d)
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{
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FT1d = 0.0;
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}
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/* Helper routines to perform bitwise copies between float and int. */
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static inline float vfp_itos(uint32_t i)
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{
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union {
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uint32_t i;
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float s;
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} v;
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v.i = i;
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return v.s;
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}
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static inline uint32_t vfp_stoi(float s)
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{
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union {
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uint32_t i;
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float s;
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} v;
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v.s = s;
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return v.i;
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}
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/* Integer to float conversion. */
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VFP_OP(uito, s)
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{
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FT0s = (float)(uint32_t)vfp_stoi(FT0s);
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}
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VFP_OP(uito, d)
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{
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FT0d = (double)(uint32_t)vfp_stoi(FT0s);
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}
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VFP_OP(sito, s)
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{
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FT0s = (float)(int32_t)vfp_stoi(FT0s);
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}
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VFP_OP(sito, d)
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{
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FT0d = (double)(int32_t)vfp_stoi(FT0s);
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}
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/* Float to integer conversion. */
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VFP_OP(toui, s)
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{
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FT0s = vfp_itos((uint32_t)FT0s);
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}
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VFP_OP(toui, d)
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{
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FT0s = vfp_itos((uint32_t)FT0d);
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}
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VFP_OP(tosi, s)
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{
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FT0s = vfp_itos((int32_t)FT0s);
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}
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VFP_OP(tosi, d)
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{
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FT0s = vfp_itos((int32_t)FT0d);
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}
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/* TODO: Set rounding mode properly. */
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VFP_OP(touiz, s)
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{
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FT0s = vfp_itos((uint32_t)FT0s);
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}
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VFP_OP(touiz, d)
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{
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FT0s = vfp_itos((uint32_t)FT0d);
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}
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VFP_OP(tosiz, s)
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{
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FT0s = vfp_itos((int32_t)FT0s);
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}
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VFP_OP(tosiz, d)
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{
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FT0s = vfp_itos((int32_t)FT0d);
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}
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/* floating point conversion */
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VFP_OP(fcvtd, s)
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{
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FT0d = (double)FT0s;
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}
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VFP_OP(fcvts, d)
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{
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FT0s = (float)FT0d;
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}
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/* Get and Put values from registers. */
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VFP_OP(getreg_F0, d)
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{
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FT0d = *(double *)((char *) env + PARAM1);
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}
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VFP_OP(getreg_F0, s)
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{
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FT0s = *(float *)((char *) env + PARAM1);
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}
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VFP_OP(getreg_F1, d)
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{
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FT1d = *(double *)((char *) env + PARAM1);
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}
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VFP_OP(getreg_F1, s)
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{
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FT1s = *(float *)((char *) env + PARAM1);
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}
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VFP_OP(setreg_F0, d)
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{
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*(double *)((char *) env + PARAM1) = FT0d;
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}
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VFP_OP(setreg_F0, s)
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{
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*(float *)((char *) env + PARAM1) = FT0s;
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}
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VFP_OP(foobar, d)
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{
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FT0d = env->vfp.regs.s[3];
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}
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void OPPROTO op_vfp_movl_T0_fpscr(void)
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{
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do_vfp_get_fpscr ();
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}
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void OPPROTO op_vfp_movl_T0_fpscr_flags(void)
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{
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T0 = env->vfp.fpscr & (0xf << 28);
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}
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void OPPROTO op_vfp_movl_fpscr_T0(void)
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{
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do_vfp_set_fpscr();
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}
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/* Move between FT0s to T0 */
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void OPPROTO op_vfp_mrs(void)
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{
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T0 = vfp_stoi(FT0s);
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}
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void OPPROTO op_vfp_msr(void)
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{
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FT0s = vfp_itos(T0);
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}
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/* Move between FT0d and {T0,T1} */
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void OPPROTO op_vfp_mrrd(void)
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{
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CPU_DoubleU u;
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u.d = FT0d;
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T0 = u.l.lower;
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T1 = u.l.upper;
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}
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void OPPROTO op_vfp_mdrr(void)
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{
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CPU_DoubleU u;
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u.l.lower = T0;
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u.l.upper = T1;
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FT0d = u.d;
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}
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/* Floating point load/store. Address is in T1 */
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void OPPROTO op_vfp_lds(void)
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{
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FT0s = ldfl((void *)T1);
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}
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void OPPROTO op_vfp_ldd(void)
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{
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FT0d = ldfq((void *)T1);
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}
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void OPPROTO op_vfp_sts(void)
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{
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stfl((void *)T1, FT0s);
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}
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void OPPROTO op_vfp_std(void)
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{
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stfq((void *)T1, FT0d);
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}
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|
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@@ -0,0 +1,229 @@
|
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/*
|
||||
* ARM helper routines
|
||||
*
|
||||
* Copyright (c) 2005 CodeSourcery, LLC
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <math.h>
|
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#include <fenv.h>
|
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#include "exec.h"
|
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|
||||
/* If the host doesn't define C99 math intrinsics then use the normal
|
||||
operators. This may generate excess exceptions, but it's probably
|
||||
near enough for most things. */
|
||||
#ifndef isless
|
||||
#define isless(x, y) (x < y)
|
||||
#endif
|
||||
#ifndef isgreater
|
||||
#define isgreater(x, y) (x > y)
|
||||
#endif
|
||||
#ifndef isunordered
|
||||
#define isunordered(x, y) (!((x < y) || (x >= y)))
|
||||
#endif
|
||||
|
||||
void raise_exception(int tt)
|
||||
{
|
||||
env->exception_index = tt;
|
||||
cpu_loop_exit();
|
||||
}
|
||||
|
||||
/* thread support */
|
||||
|
||||
spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
|
||||
|
||||
void cpu_lock(void)
|
||||
{
|
||||
spin_lock(&global_cpu_lock);
|
||||
}
|
||||
|
||||
void cpu_unlock(void)
|
||||
{
|
||||
spin_unlock(&global_cpu_lock);
|
||||
}
|
||||
|
||||
/* VFP support. */
|
||||
|
||||
void do_vfp_abss(void)
|
||||
{
|
||||
FT0s = fabsf(FT0s);
|
||||
}
|
||||
|
||||
void do_vfp_absd(void)
|
||||
{
|
||||
FT0d = fabs(FT0d);
|
||||
}
|
||||
|
||||
void do_vfp_sqrts(void)
|
||||
{
|
||||
FT0s = sqrtf(FT0s);
|
||||
}
|
||||
|
||||
void do_vfp_sqrtd(void)
|
||||
{
|
||||
FT0d = sqrt(FT0d);
|
||||
}
|
||||
|
||||
/* We use an == operator first to generate teh correct floating point
|
||||
exception. Subsequent comparisons use the exception-safe macros. */
|
||||
#define DO_VFP_cmp(p) \
|
||||
void do_vfp_cmp##p(void) \
|
||||
{ \
|
||||
uint32_t flags; \
|
||||
if (FT0##p == FT1##p) \
|
||||
flags = 0xc; \
|
||||
else if (isless (FT0##p, FT1##p)) \
|
||||
flags = 0x8; \
|
||||
else if (isgreater (FT0##p, FT1##p)) \
|
||||
flags = 0x2; \
|
||||
else /* unordered */ \
|
||||
flags = 0x3; \
|
||||
env->vfp.fpscr = (flags << 28) | (env->vfp.fpscr & 0x0fffffff); \
|
||||
FORCE_RET(); \
|
||||
}
|
||||
DO_VFP_cmp(s)
|
||||
DO_VFP_cmp(d)
|
||||
#undef DO_VFP_cmp
|
||||
|
||||
/* We use a > operator first to get FP exceptions right. */
|
||||
#define DO_VFP_cmpe(p) \
|
||||
void do_vfp_cmpe##p(void) \
|
||||
{ \
|
||||
uint32_t flags; \
|
||||
if (FT0##p > FT1##p) \
|
||||
flags = 0x2; \
|
||||
else if (isless (FT0##p, FT1##p)) \
|
||||
flags = 0x8; \
|
||||
else if (isunordered (FT0##p, FT1##p)) \
|
||||
flags = 0x3; \
|
||||
else /* equal */ \
|
||||
flags = 0xc; \
|
||||
env->vfp.fpscr = (flags << 28) | (env->vfp.fpscr & 0x0fffffff); \
|
||||
FORCE_RET(); \
|
||||
}
|
||||
DO_VFP_cmpe(s)
|
||||
DO_VFP_cmpe(d)
|
||||
#undef DO_VFP_cmpe
|
||||
|
||||
/* Convert host exception flags to vfp form. */
|
||||
int vfp_exceptbits_from_host(int host_bits)
|
||||
{
|
||||
int target_bits = 0;
|
||||
|
||||
#ifdef FE_INVALID
|
||||
if (host_bits & FE_INVALID)
|
||||
target_bits |= 1;
|
||||
#endif
|
||||
#ifdef FE_DIVBYZERO
|
||||
if (host_bits & FE_DIVBYZERO)
|
||||
target_bits |= 2;
|
||||
#endif
|
||||
#ifdef FE_OVERFLOW
|
||||
if (host_bits & FE_OVERFLOW)
|
||||
target_bits |= 4;
|
||||
#endif
|
||||
#ifdef FE_UNDERFLOW
|
||||
if (host_bits & FE_UNDERFLOW)
|
||||
target_bits |= 8;
|
||||
#endif
|
||||
#ifdef FE_INEXACT
|
||||
if (host_bits & FE_INEXACT)
|
||||
target_bits |= 0x10;
|
||||
#endif
|
||||
/* C doesn't define an inexact exception. */
|
||||
return target_bits;
|
||||
}
|
||||
|
||||
/* Convert vfp exception flags to target form. */
|
||||
int vfp_host_exceptbits_to_host(int target_bits)
|
||||
{
|
||||
int host_bits = 0;
|
||||
|
||||
#ifdef FE_INVALID
|
||||
if (target_bits & 1)
|
||||
host_bits |= FE_INVALID;
|
||||
#endif
|
||||
#ifdef FE_DIVBYZERO
|
||||
if (target_bits & 2)
|
||||
host_bits |= FE_DIVBYZERO;
|
||||
#endif
|
||||
#ifdef FE_OVERFLOW
|
||||
if (target_bits & 4)
|
||||
host_bits |= FE_OVERFLOW;
|
||||
#endif
|
||||
#ifdef FE_UNDERFLOW
|
||||
if (target_bits & 8)
|
||||
host_bits |= FE_UNDERFLOW;
|
||||
#endif
|
||||
#ifdef FE_INEXACT
|
||||
if (target_bits & 0x10)
|
||||
host_bits |= FE_INEXACT;
|
||||
#endif
|
||||
return host_bits;
|
||||
}
|
||||
|
||||
void do_vfp_set_fpscr(void)
|
||||
{
|
||||
int i;
|
||||
uint32_t changed;
|
||||
|
||||
changed = env->vfp.fpscr;
|
||||
env->vfp.fpscr = (T0 & 0xffc8ffff);
|
||||
env->vfp.vec_len = (T0 >> 16) & 7;
|
||||
env->vfp.vec_stride = (T0 >> 20) & 3;
|
||||
|
||||
changed ^= T0;
|
||||
if (changed & (3 << 22)) {
|
||||
i = (T0 >> 22) & 3;
|
||||
switch (i) {
|
||||
case 0:
|
||||
i = FE_TONEAREST;
|
||||
break;
|
||||
case 1:
|
||||
i = FE_UPWARD;
|
||||
break;
|
||||
case 2:
|
||||
i = FE_DOWNWARD;
|
||||
break;
|
||||
case 3:
|
||||
i = FE_TOWARDZERO;
|
||||
break;
|
||||
}
|
||||
fesetround (i);
|
||||
}
|
||||
|
||||
/* Clear host exception flags. */
|
||||
feclearexcept(FE_ALL_EXCEPT);
|
||||
|
||||
#ifdef feenableexcept
|
||||
if (changed & 0x1f00) {
|
||||
i = vfp_exceptbits_to_host((T0 >> 8) & 0x1f);
|
||||
feenableexcept (i);
|
||||
fedisableexcept (FE_ALL_EXCEPT & ~i);
|
||||
}
|
||||
#endif
|
||||
/* XXX: FZ and DN are not implemented. */
|
||||
}
|
||||
|
||||
void do_vfp_get_fpscr(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
T0 = (env->vfp.fpscr & 0xffc8ffff) | (env->vfp.vec_len << 16)
|
||||
| (env->vfp.vec_stride << 20);
|
||||
i = fetestexcept(FE_ALL_EXCEPT);
|
||||
T0 |= vfp_exceptbits_from_host(i);
|
||||
}
|
||||
+562
-3
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user