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hw/sh4: Coding style: Remove tabs

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Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <2d9b2c470ec022cc85a25b3e5de337b5e794f7f6.1635541329.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
BALATON Zoltan
2021-10-30 11:46:39 +02:00
committed by Philippe Mathieu-Daudé
parent dd61b91c08
commit b3793b8a91
6 changed files with 1224 additions and 1225 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/intc/sh_intc.c
+110 -110
View File
@@ -20,7 +20,7 @@
#define INTC_A7(x) ((x) & 0x1fffffff)
void sh_intc_toggle_source(struct intc_source *source,
int enable_adj, int assert_adj)
int enable_adj, int assert_adj)
{
int enable_changed = 0;
int pending_changed = 0;
@@ -54,22 +54,22 @@ void sh_intc_toggle_source(struct intc_source *source,
if (source->parent->pending == 0) {
cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
}
}
}
}
if (enable_changed || assert_adj || pending_changed) {
#ifdef DEBUG_INTC_SOURCES
printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
source->parent->pending,
source->asserted,
source->enable_count,
source->enable_max,
source->vect,
source->asserted ? "asserted " :
assert_adj ? "deasserted" : "",
enable_changed == 1 ? "enabled " :
enable_changed == -1 ? "disabled " : "",
source->pending ? "pending" : "");
source->parent->pending,
source->asserted,
source->enable_count,
source->enable_max,
source->vect,
source->asserted ? "asserted " :
assert_adj ? "deasserted" : "",
enable_changed == 1 ? "enabled " :
enable_changed == -1 ? "disabled " : "",
source->pending ? "pending" : "");
#endif
}
}
@@ -99,13 +99,13 @@ int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
for (i = 0; i < desc->nr_sources; i++) {
struct intc_source *source = desc->sources + i;
if (source->pending) {
if (source->pending) {
#ifdef DEBUG_INTC_SOURCES
printf("sh_intc: (%d) returning interrupt source 0x%x\n",
desc->pending, source->vect);
desc->pending, source->vect);
#endif
return source->vect;
}
}
}
abort();
@@ -119,16 +119,16 @@ int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
#define INTC_MODE_IS_PRIO 8
static unsigned int sh_intc_mode(unsigned long address,
unsigned long set_reg, unsigned long clr_reg)
unsigned long set_reg, unsigned long clr_reg)
{
if ((address != INTC_A7(set_reg)) &&
(address != INTC_A7(clr_reg)))
(address != INTC_A7(clr_reg)))
return INTC_MODE_NONE;
if (set_reg && clr_reg) {
if (address == INTC_A7(set_reg))
return INTC_MODE_DUAL_SET;
else
else
return INTC_MODE_DUAL_CLR;
}
@@ -139,12 +139,12 @@ static unsigned int sh_intc_mode(unsigned long address,
}
static void sh_intc_locate(struct intc_desc *desc,
unsigned long address,
unsigned long **datap,
intc_enum **enums,
unsigned int *first,
unsigned int *width,
unsigned int *modep)
unsigned long address,
unsigned long **datap,
intc_enum **enums,
unsigned int *first,
unsigned int *width,
unsigned int *modep)
{
unsigned int i, mode;
@@ -152,54 +152,54 @@ static void sh_intc_locate(struct intc_desc *desc,
if (desc->mask_regs) {
for (i = 0; i < desc->nr_mask_regs; i++) {
struct intc_mask_reg *mr = desc->mask_regs + i;
struct intc_mask_reg *mr = desc->mask_regs + i;
mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
if (mode == INTC_MODE_NONE)
mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
if (mode == INTC_MODE_NONE)
continue;
*modep = mode;
*datap = &mr->value;
*enums = mr->enum_ids;
*first = mr->reg_width - 1;
*width = 1;
return;
}
*modep = mode;
*datap = &mr->value;
*enums = mr->enum_ids;
*first = mr->reg_width - 1;
*width = 1;
return;
}
}
if (desc->prio_regs) {
for (i = 0; i < desc->nr_prio_regs; i++) {
struct intc_prio_reg *pr = desc->prio_regs + i;
struct intc_prio_reg *pr = desc->prio_regs + i;
mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
if (mode == INTC_MODE_NONE)
mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
if (mode == INTC_MODE_NONE)
continue;
*modep = mode | INTC_MODE_IS_PRIO;
*datap = &pr->value;
*enums = pr->enum_ids;
*first = (pr->reg_width / pr->field_width) - 1;
*width = pr->field_width;
return;
}
*modep = mode | INTC_MODE_IS_PRIO;
*datap = &pr->value;
*enums = pr->enum_ids;
*first = (pr->reg_width / pr->field_width) - 1;
*width = pr->field_width;
return;
}
}
abort();
}
static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
int enable, int is_group)
int enable, int is_group)
{
struct intc_source *source = desc->sources + id;
if (!id)
return;
return;
if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
#ifdef DEBUG_INTC_SOURCES
printf("sh_intc: reserved interrupt source %d modified\n", id);
#endif
return;
return;
}
if (source->vect)
@@ -237,7 +237,7 @@ static uint64_t sh_intc_read(void *opaque, hwaddr offset,
#endif
sh_intc_locate(desc, (unsigned long)offset, &valuep,
&enum_ids, &first, &width, &mode);
&enum_ids, &first, &width, &mode);
return *valuep;
}
@@ -258,7 +258,7 @@ static void sh_intc_write(void *opaque, hwaddr offset,
#endif
sh_intc_locate(desc, (unsigned long)offset, &valuep,
&enum_ids, &first, &width, &mode);
&enum_ids, &first, &width, &mode);
switch (mode) {
case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
@@ -270,11 +270,11 @@ static void sh_intc_write(void *opaque, hwaddr offset,
for (k = 0; k <= first; k++) {
mask = ((1 << width) - 1) << ((first - k) * width);
if ((*valuep & mask) == (value & mask))
if ((*valuep & mask) == (value & mask))
continue;
#if 0
printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
k, first, enum_ids[k], (unsigned int)mask);
printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
k, first, enum_ids[k], (unsigned int)mask);
#endif
sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
}
@@ -301,11 +301,11 @@ struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
}
static unsigned int sh_intc_register(MemoryRegion *sysmem,
struct intc_desc *desc,
const unsigned long address,
const char *type,
const char *action,
const unsigned int index)
struct intc_desc *desc,
const unsigned long address,
const char *type,
const char *action,
const unsigned int index)
{
char name[60];
MemoryRegion *iomem, *iomem_p4, *iomem_a7;
@@ -333,74 +333,74 @@ static unsigned int sh_intc_register(MemoryRegion *sysmem,
}
static void sh_intc_register_source(struct intc_desc *desc,
intc_enum source,
struct intc_group *groups,
int nr_groups)
intc_enum source,
struct intc_group *groups,
int nr_groups)
{
unsigned int i, k;
struct intc_source *s;
if (desc->mask_regs) {
for (i = 0; i < desc->nr_mask_regs; i++) {
struct intc_mask_reg *mr = desc->mask_regs + i;
struct intc_mask_reg *mr = desc->mask_regs + i;
for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
if (mr->enum_ids[k] != source)
continue;
s = sh_intc_source(desc, mr->enum_ids[k]);
if (s)
s = sh_intc_source(desc, mr->enum_ids[k]);
if (s)
s->enable_max++;
}
}
}
}
}
if (desc->prio_regs) {
for (i = 0; i < desc->nr_prio_regs; i++) {
struct intc_prio_reg *pr = desc->prio_regs + i;
struct intc_prio_reg *pr = desc->prio_regs + i;
for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
if (pr->enum_ids[k] != source)
continue;
s = sh_intc_source(desc, pr->enum_ids[k]);
if (s)
s = sh_intc_source(desc, pr->enum_ids[k]);
if (s)
s->enable_max++;
}
}
}
}
}
if (groups) {
for (i = 0; i < nr_groups; i++) {
struct intc_group *gr = groups + i;
struct intc_group *gr = groups + i;
for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
if (gr->enum_ids[k] != source)
continue;
s = sh_intc_source(desc, gr->enum_ids[k]);
if (s)
s = sh_intc_source(desc, gr->enum_ids[k]);
if (s)
s->enable_max++;
}
}
}
}
}
}
void sh_intc_register_sources(struct intc_desc *desc,
struct intc_vect *vectors,
int nr_vectors,
struct intc_group *groups,
int nr_groups)
struct intc_vect *vectors,
int nr_vectors,
struct intc_group *groups,
int nr_groups)
{
unsigned int i, k;
struct intc_source *s;
for (i = 0; i < nr_vectors; i++) {
struct intc_vect *vect = vectors + i;
struct intc_vect *vect = vectors + i;
sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
s = sh_intc_source(desc, vect->enum_id);
sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
s = sh_intc_source(desc, vect->enum_id);
if (s) {
s->vect = vect->vect;
@@ -413,34 +413,34 @@ void sh_intc_register_sources(struct intc_desc *desc,
if (groups) {
for (i = 0; i < nr_groups; i++) {
struct intc_group *gr = groups + i;
struct intc_group *gr = groups + i;
s = sh_intc_source(desc, gr->enum_id);
s->next_enum_id = gr->enum_ids[0];
s = sh_intc_source(desc, gr->enum_id);
s->next_enum_id = gr->enum_ids[0];
for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
if (!gr->enum_ids[k])
continue;
s = sh_intc_source(desc, gr->enum_ids[k - 1]);
s->next_enum_id = gr->enum_ids[k];
}
s = sh_intc_source(desc, gr->enum_ids[k - 1]);
s->next_enum_id = gr->enum_ids[k];
}
#ifdef DEBUG_INTC_SOURCES
printf("sh_intc: registered group %d (%d/%d)\n",
gr->enum_id, s->enable_count, s->enable_max);
printf("sh_intc: registered group %d (%d/%d)\n",
gr->enum_id, s->enable_count, s->enable_max);
#endif
}
}
}
}
int sh_intc_init(MemoryRegion *sysmem,
struct intc_desc *desc,
int nr_sources,
struct intc_mask_reg *mask_regs,
int nr_mask_regs,
struct intc_prio_reg *prio_regs,
int nr_prio_regs)
struct intc_desc *desc,
int nr_sources,
struct intc_mask_reg *mask_regs,
int nr_mask_regs,
struct intc_prio_reg *prio_regs,
int nr_prio_regs)
{
unsigned int i, j;
@@ -474,24 +474,24 @@ int sh_intc_init(MemoryRegion *sysmem,
reg_struct->action##_reg, #type, #action, j
if (desc->mask_regs) {
for (i = 0; i < desc->nr_mask_regs; i++) {
struct intc_mask_reg *mr = desc->mask_regs + i;
struct intc_mask_reg *mr = desc->mask_regs + i;
j += sh_intc_register(sysmem, desc,
INT_REG_PARAMS(mr, mask, set, j));
j += sh_intc_register(sysmem, desc,
INT_REG_PARAMS(mr, mask, clr, j));
}
}
}
if (desc->prio_regs) {
for (i = 0; i < desc->nr_prio_regs; i++) {
struct intc_prio_reg *pr = desc->prio_regs + i;
struct intc_prio_reg *pr = desc->prio_regs + i;
j += sh_intc_register(sysmem, desc,
INT_REG_PARAMS(pr, prio, set, j));
j += sh_intc_register(sysmem, desc,
INT_REG_PARAMS(pr, prio, clr, j));
}
}
}
#undef INT_REG_PARAMS
@@ -505,10 +505,10 @@ void sh_intc_set_irl(void *opaque, int n, int level)
struct intc_source *s = opaque;
int i, irl = level ^ 15;
for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
if (i == irl)
sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
else
if (s->asserted)
sh_intc_toggle_source(s, 0, -1);
if (i == irl)
sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
else
if (s->asserted)
sh_intc_toggle_source(s, 0, -1);
}
}
hw/sh4/r2d.c
+17 -17
View File
@@ -56,10 +56,10 @@
#define LINUX_LOAD_OFFSET 0x0800000
#define INITRD_LOAD_OFFSET 0x1800000
#define PA_IRLMSK 0x00
#define PA_POWOFF 0x30
#define PA_VERREG 0x32
#define PA_OUTPORT 0x36
#define PA_IRLMSK 0x00
#define PA_POWOFF 0x30
#define PA_VERREG 0x32
#define PA_OUTPORT 0x36
typedef struct {
uint16_t bcr;
@@ -96,19 +96,19 @@ enum r2d_fpga_irq {
};
static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
[CF_IDE] = { 1, 1<<9 },
[CF_CD] = { 2, 1<<8 },
[PCI_INTA] = { 9, 1<<14 },
[PCI_INTB] = { 10, 1<<13 },
[PCI_INTC] = { 3, 1<<12 },
[PCI_INTD] = { 0, 1<<11 },
[SM501] = { 4, 1<<10 },
[KEY] = { 5, 1<<6 },
[RTC_A] = { 6, 1<<5 },
[RTC_T] = { 7, 1<<4 },
[SDCARD] = { 8, 1<<7 },
[EXT] = { 11, 1<<0 },
[TP] = { 12, 1<<15 },
[CF_IDE] = { 1, 1<<9 },
[CF_CD] = { 2, 1<<8 },
[PCI_INTA] = { 9, 1<<14 },
[PCI_INTB] = { 10, 1<<13 },
[PCI_INTC] = { 3, 1<<12 },
[PCI_INTD] = { 0, 1<<11 },
[SM501] = { 4, 1<<10 },
[KEY] = { 5, 1<<6 },
[RTC_A] = { 6, 1<<5 },
[RTC_T] = { 7, 1<<4 },
[SDCARD] = { 8, 1<<7 },
[EXT] = { 11, 1<<0 },
[TP] = { 12, 1<<15 },
};
static void update_irl(r2d_fpga_t *fpga)
hw/sh4/sh7750.c
+254 -255
View File
File diff suppressed because it is too large Load Diff
hw/sh4/sh7750_regnames.c
+72 -72
View File
@@ -12,76 +12,76 @@ typedef struct {
static regname_t regnames[] = {
REGNAME(SH7750_PTEH_A7)
REGNAME(SH7750_PTEL_A7)
REGNAME(SH7750_PTEA_A7)
REGNAME(SH7750_TTB_A7)
REGNAME(SH7750_TEA_A7)
REGNAME(SH7750_MMUCR_A7)
REGNAME(SH7750_CCR_A7)
REGNAME(SH7750_QACR0_A7)
REGNAME(SH7750_QACR1_A7)
REGNAME(SH7750_TRA_A7)
REGNAME(SH7750_EXPEVT_A7)
REGNAME(SH7750_INTEVT_A7)
REGNAME(SH7750_STBCR_A7)
REGNAME(SH7750_STBCR2_A7)
REGNAME(SH7750_FRQCR_A7)
REGNAME(SH7750_WTCNT_A7)
REGNAME(SH7750_WTCSR_A7)
REGNAME(SH7750_R64CNT_A7)
REGNAME(SH7750_RSECCNT_A7)
REGNAME(SH7750_RMINCNT_A7)
REGNAME(SH7750_RHRCNT_A7)
REGNAME(SH7750_RWKCNT_A7)
REGNAME(SH7750_RDAYCNT_A7)
REGNAME(SH7750_RMONCNT_A7)
REGNAME(SH7750_RYRCNT_A7)
REGNAME(SH7750_RSECAR_A7)
REGNAME(SH7750_RMINAR_A7)
REGNAME(SH7750_RHRAR_A7)
REGNAME(SH7750_RWKAR_A7)
REGNAME(SH7750_RDAYAR_A7)
REGNAME(SH7750_RMONAR_A7)
REGNAME(SH7750_RCR1_A7)
REGNAME(SH7750_RCR2_A7)
REGNAME(SH7750_BCR1_A7)
REGNAME(SH7750_BCR2_A7)
REGNAME(SH7750_WCR1_A7)
REGNAME(SH7750_WCR2_A7)
REGNAME(SH7750_WCR3_A7)
REGNAME(SH7750_MCR_A7)
REGNAME(SH7750_PCR_A7)
REGNAME(SH7750_RTCSR_A7)
REGNAME(SH7750_RTCNT_A7)
REGNAME(SH7750_RTCOR_A7)
REGNAME(SH7750_RFCR_A7)
REGNAME(SH7750_SAR0_A7)
REGNAME(SH7750_SAR1_A7)
REGNAME(SH7750_SAR2_A7)
REGNAME(SH7750_SAR3_A7)
REGNAME(SH7750_DAR0_A7)
REGNAME(SH7750_DAR1_A7)
REGNAME(SH7750_DAR2_A7)
REGNAME(SH7750_DAR3_A7)
REGNAME(SH7750_DMATCR0_A7)
REGNAME(SH7750_DMATCR1_A7)
REGNAME(SH7750_DMATCR2_A7)
REGNAME(SH7750_DMATCR3_A7)
REGNAME(SH7750_CHCR0_A7)
REGNAME(SH7750_CHCR1_A7)
REGNAME(SH7750_CHCR2_A7)
REGNAME(SH7750_CHCR3_A7)
REGNAME(SH7750_DMAOR_A7)
REGNAME(SH7750_PCTRA_A7)
REGNAME(SH7750_PDTRA_A7)
REGNAME(SH7750_PCTRB_A7)
REGNAME(SH7750_PDTRB_A7)
REGNAME(SH7750_GPIOIC_A7)
REGNAME(SH7750_ICR_A7)
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
REGNAME(SH7750_SDMR2_A7)
REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, NULL}
REGNAME(SH7750_PTEL_A7)
REGNAME(SH7750_PTEA_A7)
REGNAME(SH7750_TTB_A7)
REGNAME(SH7750_TEA_A7)
REGNAME(SH7750_MMUCR_A7)
REGNAME(SH7750_CCR_A7)
REGNAME(SH7750_QACR0_A7)
REGNAME(SH7750_QACR1_A7)
REGNAME(SH7750_TRA_A7)
REGNAME(SH7750_EXPEVT_A7)
REGNAME(SH7750_INTEVT_A7)
REGNAME(SH7750_STBCR_A7)
REGNAME(SH7750_STBCR2_A7)
REGNAME(SH7750_FRQCR_A7)
REGNAME(SH7750_WTCNT_A7)
REGNAME(SH7750_WTCSR_A7)
REGNAME(SH7750_R64CNT_A7)
REGNAME(SH7750_RSECCNT_A7)
REGNAME(SH7750_RMINCNT_A7)
REGNAME(SH7750_RHRCNT_A7)
REGNAME(SH7750_RWKCNT_A7)
REGNAME(SH7750_RDAYCNT_A7)
REGNAME(SH7750_RMONCNT_A7)
REGNAME(SH7750_RYRCNT_A7)
REGNAME(SH7750_RSECAR_A7)
REGNAME(SH7750_RMINAR_A7)
REGNAME(SH7750_RHRAR_A7)
REGNAME(SH7750_RWKAR_A7)
REGNAME(SH7750_RDAYAR_A7)
REGNAME(SH7750_RMONAR_A7)
REGNAME(SH7750_RCR1_A7)
REGNAME(SH7750_RCR2_A7)
REGNAME(SH7750_BCR1_A7)
REGNAME(SH7750_BCR2_A7)
REGNAME(SH7750_WCR1_A7)
REGNAME(SH7750_WCR2_A7)
REGNAME(SH7750_WCR3_A7)
REGNAME(SH7750_MCR_A7)
REGNAME(SH7750_PCR_A7)
REGNAME(SH7750_RTCSR_A7)
REGNAME(SH7750_RTCNT_A7)
REGNAME(SH7750_RTCOR_A7)
REGNAME(SH7750_RFCR_A7)
REGNAME(SH7750_SAR0_A7)
REGNAME(SH7750_SAR1_A7)
REGNAME(SH7750_SAR2_A7)
REGNAME(SH7750_SAR3_A7)
REGNAME(SH7750_DAR0_A7)
REGNAME(SH7750_DAR1_A7)
REGNAME(SH7750_DAR2_A7)
REGNAME(SH7750_DAR3_A7)
REGNAME(SH7750_DMATCR0_A7)
REGNAME(SH7750_DMATCR1_A7)
REGNAME(SH7750_DMATCR2_A7)
REGNAME(SH7750_DMATCR3_A7)
REGNAME(SH7750_CHCR0_A7)
REGNAME(SH7750_CHCR1_A7)
REGNAME(SH7750_CHCR2_A7)
REGNAME(SH7750_CHCR3_A7)
REGNAME(SH7750_DMAOR_A7)
REGNAME(SH7750_PCTRA_A7)
REGNAME(SH7750_PDTRA_A7)
REGNAME(SH7750_PCTRB_A7)
REGNAME(SH7750_PDTRB_A7)
REGNAME(SH7750_GPIOIC_A7)
REGNAME(SH7750_ICR_A7)
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
REGNAME(SH7750_SDMR2_A7)
REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, NULL}
};
const char *regname(uint32_t addr)
@@ -89,8 +89,8 @@ const char *regname(uint32_t addr)
unsigned int i;
for (i = 0; regnames[i].regaddr != (uint32_t) - 1; i++) {
if (regnames[i].regaddr == addr)
return regnames[i].regname;
if (regnames[i].regaddr == addr)
return regnames[i].regname;
}
return "<unknown reg>";
hw/sh4/sh7750_regs.h
+761 -761
View File
File diff suppressed because it is too large Load Diff
include/hw/sh4/sh.h
+10 -10
View File
@@ -44,25 +44,25 @@ typedef struct {
uint16_t portbmask_trigger;
/* Return 0 if no action was taken */
int (*port_change_cb) (uint16_t porta, uint16_t portb,
uint16_t * periph_pdtra,
uint16_t * periph_portdira,
uint16_t * periph_pdtrb,
uint16_t * periph_portdirb);
uint16_t * periph_pdtra,
uint16_t * periph_portdira,
uint16_t * periph_pdtrb,
uint16_t * periph_portdirb);
} sh7750_io_device;
int sh7750_register_io_device(struct SH7750State *s,
sh7750_io_device * device);
sh7750_io_device * device);
/* sh_serial.c */
#define SH_SERIAL_FEAT_SCIF (1 << 0)
void sh_serial_init(MemoryRegion *sysmem,
hwaddr base, int feat,
uint32_t freq, Chardev *chr,
qemu_irq eri_source,
qemu_irq rxi_source,
qemu_irq txi_source,
qemu_irq tei_source,
qemu_irq bri_source);
qemu_irq eri_source,
qemu_irq rxi_source,
qemu_irq txi_source,
qemu_irq tei_source,
qemu_irq bri_source);
/* sh7750.c */
qemu_irq sh7750_irl(struct SH7750State *s);