Add OMAP MMC/SD host controller.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3097 c046a42c-6fe2-441c-8c8c-71466251a162

Makefile.target

@@ -463,7 +463,7 @@ VL_OBJS+= arm-semi.o
 VL_OBJS+= pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
 VL_OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o max111x.o max7310.o
 VL_OBJS+= spitz.o ads7846.o ide.o serial.o nand.o $(AUDIODRV) wm8750.o
-VL_OBJS+= omap.o omap_lcdc.o omap1_clk.o palm.o
+VL_OBJS+= omap.o omap_lcdc.o omap1_clk.o omap_mmc.o palm.o
 CPPFLAGS += -DHAS_AUDIO
 endif
 ifeq ($(TARGET_BASE_ARCH), sh4)

hw/omap.c

@@ -22,25 +22,25 @@
 #include "arm_pic.h"
 
 /* Should signal the TCMI */
-static uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
 {
     OMAP_16B_REG(addr);
     return 0;
 }
 
-static void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
                 uint32_t value)
 {
     OMAP_16B_REG(addr);
 }
 
-static uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
 {
     OMAP_32B_REG(addr);
     return 0;
 }
 
-static void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
                 uint32_t value)
 {
     OMAP_32B_REG(addr);
@@ -2816,6 +2816,7 @@ static void omap_mpu_reset(void *opaque)
     omap_uart_reset(mpu->uart1);
     omap_uart_reset(mpu->uart2);
     omap_uart_reset(mpu->uart3);
+    omap_mmc_reset(mpu->mmc);
     cpu_reset(mpu->env);
 }
 
@@ -2921,6 +2922,9 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
     omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
     omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
 
+    s->mmc = omap_mmc_init(0xfffb7800, s->irq[1][OMAP_INT_OQN],
+                    &s->drq[OMAP_DMA_MMC_TX], omap_findclk(s, "mmc_ck"));
+
     qemu_register_reset(omap_mpu_reset, s);
     s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
 

hw/omap.h

@@ -163,7 +163,7 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
 # define OMAP_INT_USB_W2FC		20
 # define OMAP_INT_1WIRE			21
 # define OMAP_INT_OS_TIMER		22
-# define OMAP_INT_MMC			23
+# define OMAP_INT_OQN			23
 # define OMAP_INT_GAUGE_32K		24
 # define OMAP_INT_RTC_TIMER		25
 # define OMAP_INT_RTC_ALARM		26
@@ -457,6 +457,12 @@ struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
                 struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
                 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
 
+/* omap_mmc.c */
+struct omap_mmc_s;
+struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
+                qemu_irq irq, qemu_irq dma[], omap_clk clk);
+void omap_mmc_reset(struct omap_mmc_s *s);
+
 # define cpu_is_omap310(cpu)		(cpu->mpu_model == omap310)
 # define cpu_is_omap1510(cpu)		(cpu->mpu_model == omap1510)
 # define cpu_is_omap15xx(cpu)		\
@@ -497,6 +503,8 @@ struct omap_mpu_state_s {
     struct omap_uart_s *uart1;
     struct omap_uart_s *uart2;
 
+    struct omap_mmc_s *mmc;
+
     /* MPU private TIPB peripherals */
     struct omap_intr_handler_s *ih[2];
 
@@ -566,6 +574,13 @@ struct omap_mpu_state_s {
 #  error TARGET_PHYS_ADDR_BITS undefined
 # endif
 
+uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
+void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
+                uint32_t value);
+uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
+void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
+                uint32_t value);
+
 # define OMAP_BAD_REG(paddr)		\
         printf("%s: Bad register " OMAP_FMT_plx "\n", __FUNCTION__, paddr)
 # define OMAP_RO_REG(paddr)		\