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Merge tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu into staging

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ppc patch queue for 2022-04-20

First batch of ppc patches for QEMU 7.1:

- skiboot firmware version bump
- pseries: add 2M DDW pagesize
- pseries: make virtual hypervisor code TCG only
- powernv: introduce GPIO lines for PSIHB device
- powernv: remove PCIE root bridge LSI
- target/ppc: alternative softfloat 128 bit integer support
- assorted fixes

# -----BEGIN PGP SIGNATURE-----
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# ZE10AP4wPeJQ3fxXb5ylVtL4qkJaLWy6VrJBQSKSb5YEA0fhegEA9ZufpnENQePU
# gZF0eFAQK/DbSnDyvRQVpGcJM0K1UgI=
# =nVRw
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 20 Apr 2022 02:48:14 PM PDT
# gpg:                using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: Can't check signature: No public key

* tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu: (23 commits)
  hw/ppc: change indentation to spaces from TABs
  target/ppc: Add two missing register callbacks on POWER10
  ppc/pnv: Remove LSI on the PCIE host bridge
  pcie: Don't try triggering a LSI when not defined
  ppc/vof: Fix uninitialized string tracing
  hw/ppc/ppc405_boards: Initialize g_autofree pointer
  target/ppc: implement xscvqp[su]qz
  target/ppc: implement xscv[su]qqp
  softfloat: add float128_to_int128
  softfloat: add float128_to_uint128
  softfloat: add int128_to_float128
  softfloat: add uint128_to_float128
  qemu/int128: add int128_urshift
  target/ppc: Improve KVM hypercall trace
  spapr: Move nested KVM hypercalls under a TCG only config.
  spapr: Move hypercall_register_softmmu
  ppc/pnv: Remove useless checks in set_irq handlers
  ppc/pnv: Remove PnvPsiClas::irq_set
  ppc/pnv: Remove PnvOCC::psi link
  ppc/pnv: Remove PnvLpcController::psi link
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2022-04-20 21:54:24 -07:00
parent 9c125d17e9 2d94af4b16
commit b1efff6bf0
32 changed files with 446 additions and 137 deletions
Download Patch File Download Diff File Expand all files Collapse all files
fpu/softfloat.c
+183
View File
@@ -3154,6 +3154,60 @@ static int64_t float128_to_int64_scalbn(float128 a, FloatRoundMode rmode,
return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s);
}
static Int128 float128_to_int128_scalbn(float128 a, FloatRoundMode rmode,
int scale, float_status *s)
{
int flags = 0;
Int128 r;
FloatParts128 p;
float128_unpack_canonical(&p, a, s);
switch (p.cls) {
case float_class_snan:
flags |= float_flag_invalid_snan;
/* fall through */
case float_class_qnan:
flags |= float_flag_invalid;
r = UINT128_MAX;
break;
case float_class_inf:
flags = float_flag_invalid | float_flag_invalid_cvti;
r = p.sign ? INT128_MIN : INT128_MAX;
break;
case float_class_zero:
return int128_zero();
case float_class_normal:
if (parts_round_to_int_normal(&p, rmode, scale, 128 - 2)) {
flags = float_flag_inexact;
}
if (p.exp < 127) {
int shift = 127 - p.exp;
r = int128_urshift(int128_make128(p.frac_lo, p.frac_hi), shift);
if (p.sign) {
r = int128_neg(r);
}
} else if (p.exp == 127 && p.sign && p.frac_lo == 0 &&
p.frac_hi == DECOMPOSED_IMPLICIT_BIT) {
r = INT128_MIN;
} else {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = p.sign ? INT128_MIN : INT128_MAX;
}
break;
default:
g_assert_not_reached();
}
float_raise(flags, s);
return r;
}
static int32_t floatx80_to_int32_scalbn(floatx80 a, FloatRoundMode rmode,
int scale, float_status *s)
{
@@ -3236,6 +3290,11 @@ int64_t float128_to_int64(float128 a, float_status *s)
return float128_to_int64_scalbn(a, s->float_rounding_mode, 0, s);
}
Int128 float128_to_int128(float128 a, float_status *s)
{
return float128_to_int128_scalbn(a, s->float_rounding_mode, 0, s);
}
int32_t floatx80_to_int32(floatx80 a, float_status *s)
{
return floatx80_to_int32_scalbn(a, s->float_rounding_mode, 0, s);
@@ -3301,6 +3360,11 @@ int64_t float128_to_int64_round_to_zero(float128 a, float_status *s)
return float128_to_int64_scalbn(a, float_round_to_zero, 0, s);
}
Int128 float128_to_int128_round_to_zero(float128 a, float_status *s)
{
return float128_to_int128_scalbn(a, float_round_to_zero, 0, s);
}
int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *s)
{
return floatx80_to_int32_scalbn(a, float_round_to_zero, 0, s);
@@ -3480,6 +3544,61 @@ static uint64_t float128_to_uint64_scalbn(float128 a, FloatRoundMode rmode,
return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s);
}
static Int128 float128_to_uint128_scalbn(float128 a, FloatRoundMode rmode,
int scale, float_status *s)
{
int flags = 0;
Int128 r;
FloatParts128 p;
float128_unpack_canonical(&p, a, s);
switch (p.cls) {
case float_class_snan:
flags |= float_flag_invalid_snan;
/* fall through */
case float_class_qnan:
flags |= float_flag_invalid;
r = UINT128_MAX;
break;
case float_class_inf:
flags = float_flag_invalid | float_flag_invalid_cvti;
r = p.sign ? int128_zero() : UINT128_MAX;
break;
case float_class_zero:
return int128_zero();
case float_class_normal:
if (parts_round_to_int_normal(&p, rmode, scale, 128 - 2)) {
flags = float_flag_inexact;
if (p.cls == float_class_zero) {
r = int128_zero();
break;
}
}
if (p.sign) {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = int128_zero();
} else if (p.exp <= 127) {
int shift = 127 - p.exp;
r = int128_urshift(int128_make128(p.frac_lo, p.frac_hi), shift);
} else {
flags = float_flag_invalid | float_flag_invalid_cvti;
r = UINT128_MAX;
}
break;
default:
g_assert_not_reached();
}
float_raise(flags, s);
return r;
}
uint8_t float16_to_uint8(float16 a, float_status *s)
{
return float16_to_uint8_scalbn(a, s->float_rounding_mode, 0, s);
@@ -3540,6 +3659,11 @@ uint64_t float128_to_uint64(float128 a, float_status *s)
return float128_to_uint64_scalbn(a, s->float_rounding_mode, 0, s);
}
Int128 float128_to_uint128(float128 a, float_status *s)
{
return float128_to_uint128_scalbn(a, s->float_rounding_mode, 0, s);
}
uint16_t float16_to_uint16_round_to_zero(float16 a, float_status *s)
{
return float16_to_uint16_scalbn(a, float_round_to_zero, 0, s);
@@ -3595,6 +3719,11 @@ uint64_t float128_to_uint64_round_to_zero(float128 a, float_status *s)
return float128_to_uint64_scalbn(a, float_round_to_zero, 0, s);
}
Int128 float128_to_uint128_round_to_zero(float128 a, float_status *s)
{
return float128_to_uint128_scalbn(a, float_round_to_zero, 0, s);
}
uint16_t bfloat16_to_uint16(bfloat16 a, float_status *s)
{
return bfloat16_to_uint16_scalbn(a, s->float_rounding_mode, 0, s);
@@ -3780,6 +3909,35 @@ bfloat16 int16_to_bfloat16(int16_t a, float_status *status)
return int64_to_bfloat16_scalbn(a, 0, status);
}
float128 int128_to_float128(Int128 a, float_status *status)
{
FloatParts128 p = { };
int shift;
if (int128_nz(a)) {
p.cls = float_class_normal;
if (!int128_nonneg(a)) {
p.sign = true;
a = int128_neg(a);
}
shift = clz64(int128_gethi(a));
if (shift == 64) {
shift += clz64(int128_getlo(a));
}
p.exp = 127 - shift;
a = int128_lshift(a, shift);
p.frac_hi = int128_gethi(a);
p.frac_lo = int128_getlo(a);
} else {
p.cls = float_class_zero;
}
return float128_round_pack_canonical(&p, status);
}
float128 int64_to_float128(int64_t a, float_status *status)
{
FloatParts128 p;
@@ -3969,6 +4127,31 @@ float128 uint64_to_float128(uint64_t a, float_status *status)
return float128_round_pack_canonical(&p, status);
}
float128 uint128_to_float128(Int128 a, float_status *status)
{
FloatParts128 p = { };
int shift;
if (int128_nz(a)) {
p.cls = float_class_normal;
shift = clz64(int128_gethi(a));
if (shift == 64) {
shift += clz64(int128_getlo(a));
}
p.exp = 127 - shift;
a = int128_lshift(a, shift);
p.frac_hi = int128_gethi(a);
p.frac_lo = int128_getlo(a);
} else {
p.cls = float_class_zero;
}
return float128_round_pack_canonical(&p, status);
}
/*
* Minimum and maximum
*/
hw/pci-host/pnv_phb3.c
+1
View File
@@ -1161,6 +1161,7 @@ static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp)
error_propagate(errp, local_err);
return;
}
pci_config_set_interrupt_pin(pci->config, 0);
}
static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data)
hw/pci-host/pnv_phb4.c
+1
View File
@@ -1771,6 +1771,7 @@ static void pnv_phb4_root_port_reset(DeviceState *dev)
pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
pci_config_set_interrupt_pin(conf, 0);
}
static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
hw/pci/pcie.c
+3 -2
View File
@@ -353,7 +353,7 @@ static void hotplug_event_notify(PCIDevice *dev)
msix_notify(dev, pcie_cap_flags_get_vector(dev));
} else if (msi_enabled(dev)) {
msi_notify(dev, pcie_cap_flags_get_vector(dev));
} else {
} else if (pci_intx(dev) != -1) {
pci_set_irq(dev, dev->exp.hpev_notified);
}
}
@@ -361,7 +361,8 @@ static void hotplug_event_notify(PCIDevice *dev)
static void hotplug_event_clear(PCIDevice *dev)
{
hotplug_event_update_event_status(dev);
if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
if (!msix_enabled(dev) && !msi_enabled(dev) && pci_intx(dev) != -1 &&
!dev->exp.hpev_notified) {
pci_irq_deassert(dev);
}
}
hw/pci/pcie_aer.c
+1 -1
View File
@@ -290,7 +290,7 @@ static void pcie_aer_root_notify(PCIDevice *dev)
msix_notify(dev, pcie_aer_root_get_vector(dev));
} else if (msi_enabled(dev)) {
msi_notify(dev, pcie_aer_root_get_vector(dev));
} else {
} else if (pci_intx(dev) != -1) {
pci_irq_assert(dev);
}
}
hw/ppc/pnv.c
+18 -12
View File
@@ -614,24 +614,36 @@ static void pnv_reset(MachineState *machine)
static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
return pnv_lpc_isa_create(&chip8->lpc, true, errp);
}
static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
return pnv_lpc_isa_create(&chip8->lpc, false, errp);
}
static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
return pnv_lpc_isa_create(&chip9->lpc, false, errp);
}
static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
{
Pnv10Chip *chip10 = PNV10_CHIP(chip);
qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
return pnv_lpc_isa_create(&chip10->lpc, false, errp);
}
@@ -1222,8 +1234,6 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
&PNV_PSI(psi8)->xscom_regs);
/* Create LPC controller */
object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi),
&error_abort);
qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
@@ -1243,12 +1253,12 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
}
/* Create the simplified OCC model */
object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi),
&error_abort);
if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
@@ -1507,8 +1517,6 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
&PNV_PSI(psi9)->xscom_regs);
/* LPC */
object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi),
&error_abort);
if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
return;
}
@@ -1520,12 +1528,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
(uint64_t) PNV9_LPCM_BASE(chip));
/* Create the simplified OCC model */
object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi),
&error_abort);
if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
@@ -1712,8 +1720,6 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
&PNV_PSI(&chip10->psi)->xscom_regs);
/* LPC */
object_property_set_link(OBJECT(&chip10->lpc), "psi",
OBJECT(&chip10->psi), &error_abort);
if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
return;
}
@@ -1725,13 +1731,13 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
(uint64_t) PNV10_LPCM_BASE(chip));
/* Create the simplified OCC model */
object_property_set_link(OBJECT(&chip10->occ), "psi", OBJECT(&chip10->psi),
&error_abort);
if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
&chip10->occ.xscom_regs);
qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(),
hw/ppc/pnv_lpc.c
+4 -15
View File
@@ -422,7 +422,6 @@ static const MemoryRegionOps pnv_lpc_mmio_ops = {
static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
{
bool lpc_to_opb_irq = false;
PnvLpcClass *plc = PNV_LPC_GET_CLASS(lpc);
/* Update LPC controller to OPB line */
if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
@@ -445,7 +444,7 @@ static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
/* Reflect the interrupt */
pnv_psi_irq_set(lpc->psi, plc->psi_irq, lpc->opb_irq_stat != 0);
qemu_set_irq(lpc->psi_irq, lpc->opb_irq_stat != 0);
}
static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
@@ -637,8 +636,6 @@ static void pnv_lpc_power8_class_init(ObjectClass *klass, void *data)
xdc->dt_xscom = pnv_lpc_dt_xscom;
plc->psi_irq = PSIHB_IRQ_LPC_I2C;
device_class_set_parent_realize(dc, pnv_lpc_power8_realize,
&plc->parent_realize);
}
@@ -677,8 +674,6 @@ static void pnv_lpc_power9_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV LPC Controller POWER9";
plc->psi_irq = PSIHB9_IRQ_LPCHC;
device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
&plc->parent_realize);
}
@@ -706,8 +701,6 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
{
PnvLpcController *lpc = PNV_LPC(dev);
assert(lpc->psi);
/* Reg inits */
lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
@@ -746,12 +739,9 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
"lpc-hc", LPC_HC_REGS_OPB_SIZE);
memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
&lpc->lpc_hc_regs);
}
static Property pnv_lpc_properties[] = {
DEFINE_PROP_LINK("psi", PnvLpcController, psi, TYPE_PNV_PSI, PnvPsi *),
DEFINE_PROP_END_OF_LIST(),
};
qdev_init_gpio_out(DEVICE(dev), &lpc->psi_irq, 1);
}
static void pnv_lpc_class_init(ObjectClass *klass, void *data)
{
@@ -759,7 +749,6 @@ static void pnv_lpc_class_init(ObjectClass *klass, void *data)
dc->realize = pnv_lpc_realize;
dc->desc = "PowerNV LPC Controller";
device_class_set_props(dc, pnv_lpc_properties);
dc->user_creatable = false;
}
@@ -803,7 +792,7 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
}
if (pnv->cpld_irqstate != old_state) {
pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0);
qemu_set_irq(lpc->psi_irq, pnv->cpld_irqstate != 0);
}
}
hw/ppc/pnv_occ.c
+4 -12
View File
@@ -21,6 +21,7 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_xscom.h"
@@ -51,13 +52,12 @@
static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
{
bool irq_state;
PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
val &= 0xffff000000000000ull;
occ->occmisc = val;
irq_state = !!(val >> 63);
pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
qemu_set_irq(occ->psi_irq, irq_state);
}
static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
@@ -168,7 +168,6 @@ static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
poc->xscom_size = PNV_XSCOM_OCC_SIZE;
poc->xscom_ops = &pnv_occ_power8_xscom_ops;
poc->psi_irq = PSIHB_IRQ_OCC;
}
static const TypeInfo pnv_occ_power8_type_info = {
@@ -241,7 +240,6 @@ static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV OCC Controller (POWER9)";
poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
poc->xscom_ops = &pnv_occ_power9_xscom_ops;
poc->psi_irq = PSIHB9_IRQ_OCC;
}
static const TypeInfo pnv_occ_power9_type_info = {
@@ -269,8 +267,6 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
PnvOCC *occ = PNV_OCC(dev);
PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
assert(occ->psi);
occ->occmisc = 0;
/* XScom region for OCC registers */
@@ -281,12 +277,9 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops,
occ, "occ-common-area",
PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
}
static Property pnv_occ_properties[] = {
DEFINE_PROP_LINK("psi", PnvOCC, psi, TYPE_PNV_PSI, PnvPsi *),
DEFINE_PROP_END_OF_LIST(),
};
qdev_init_gpio_out(DEVICE(dev), &occ->psi_irq, 1);
}
static void pnv_occ_class_init(ObjectClass *klass, void *data)
{
@@ -294,7 +287,6 @@ static void pnv_occ_class_init(ObjectClass *klass, void *data)
dc->realize = pnv_occ_realize;
dc->desc = "PowerNV OCC Controller";
device_class_set_props(dc, pnv_occ_properties);
dc->user_creatable = false;
}
hw/ppc/pnv_psi.c
+11 -25
View File
@@ -184,8 +184,7 @@ static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
/*
* FSP and PSI interrupts are muxed under the same number.
*/
static const uint32_t xivr_regs[] = {
[PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP,
static const uint32_t xivr_regs[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP,
[PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC,
[PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI,
@@ -194,8 +193,7 @@ static const uint32_t xivr_regs[] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT,
};
static const uint32_t stat_regs[] = {
[PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR,
static const uint32_t stat_regs[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR,
[PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT,
[PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT,
@@ -204,8 +202,7 @@ static const uint32_t stat_regs[] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT,
};
static const uint64_t stat_bits[] = {
[PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ,
static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ,
[PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC,
[PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI,
@@ -214,23 +211,14 @@ static const uint64_t stat_bits[] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT,
};
void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
{
PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
}
static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
static void pnv_psi_power8_set_irq(void *opaque, int irq, int state)
{
PnvPsi *psi = opaque;
uint32_t xivr_reg;
uint32_t stat_reg;
uint32_t src;
bool masked;
if (irq > PSIHB_IRQ_EXTERNAL) {
qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
return;
}
xivr_reg = xivr_regs[irq];
stat_reg = stat_regs[irq];
@@ -515,6 +503,8 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
ics_set_irq_type(ics, i, true);
}
qdev_init_gpio_in(dev, pnv_psi_power8_set_irq, ics->nr_irqs);
psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
/* XSCOM region for PSI registers */
@@ -576,7 +566,6 @@ static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB_BAR_MASK;
ppc->irq_set = pnv_psi_power8_irq_set;
ppc->compat = compat;
ppc->compat_size = sizeof(compat);
}
@@ -814,15 +803,11 @@ static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
}
};
static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
static void pnv_psi_power9_set_irq(void *opaque, int irq, int state)
{
PnvPsi *psi = opaque;
uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
if (irq > PSIHB9_NUM_IRQS) {
qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
return;
}
if (irq_method & PSIHB9_IRQ_METHOD) {
qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
return;
@@ -876,6 +861,8 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
qdev_init_gpio_in(dev, pnv_psi_power9_set_irq, xsrc->nr_irqs);
/* XSCOM region for PSI registers */
pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
@@ -901,7 +888,6 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB9_BAR_MASK;
ppc->irq_set = pnv_psi_power9_irq_set;
ppc->compat = compat;
ppc->compat_size = sizeof(compat);
hw/ppc/ppc405_boards.c
+2 -2
View File
@@ -261,13 +261,13 @@ static void ref405ep_init(MachineState *machine)
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
g_autofree char *filename;
g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
machine->firmware);
long bios_size;
memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
&error_fatal);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
if (!filename) {
error_report("Could not find firmware '%s'", machine->firmware);
exit(1);
hw/ppc/ppc440_bamboo.c
+3 -3
View File
@@ -3,9 +3,9 @@
*
* Copyright 2007 IBM Corporation.
* Authors:
* Jerone Young <jyoung5@us.ibm.com>
* Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
* Hollis Blanchard <hollisb@us.ibm.com>
* Jerone Young <jyoung5@us.ibm.com>
* Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
* Hollis Blanchard <hollisb@us.ibm.com>
*
* This work is licensed under the GNU GPL license version 2 or later.
*
hw/ppc/spapr_hcall.c
+44 -30
View File
@@ -1473,32 +1473,7 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
return H_FUNCTION;
}
#ifndef CONFIG_TCG
static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
g_assert_not_reached();
}
static void hypercall_register_softmmu(void)
{
/* hcall-pft */
spapr_register_hypercall(H_ENTER, h_softmmu);
spapr_register_hypercall(H_REMOVE, h_softmmu);
spapr_register_hypercall(H_PROTECT, h_softmmu);
spapr_register_hypercall(H_READ, h_softmmu);
/* hcall-bulk */
spapr_register_hypercall(H_BULK_REMOVE, h_softmmu);
}
#else
static void hypercall_register_softmmu(void)
{
/* DO NOTHING */
}
#endif
/* TCG only */
#ifdef CONFIG_TCG
#define PRTS_MASK 0x1f
static target_ulong h_set_ptbl(PowerPCCPU *cpu,
@@ -1825,6 +1800,48 @@ out_restore_l1:
spapr_cpu->nested_host_state = NULL;
}
static void hypercall_register_nested(void)
{
spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
}
static void hypercall_register_softmmu(void)
{
/* DO NOTHING */
}
#else
void spapr_exit_nested(PowerPCCPU *cpu, int excp)
{
g_assert_not_reached();
}
static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
g_assert_not_reached();
}
static void hypercall_register_nested(void)
{
/* DO NOTHING */
}
static void hypercall_register_softmmu(void)
{
/* hcall-pft */
spapr_register_hypercall(H_ENTER, h_softmmu);
spapr_register_hypercall(H_REMOVE, h_softmmu);
spapr_register_hypercall(H_PROTECT, h_softmmu);
spapr_register_hypercall(H_READ, h_softmmu);
/* hcall-bulk */
spapr_register_hypercall(H_BULK_REMOVE, h_softmmu);
}
#endif
static void hypercall_register_types(void)
{
hypercall_register_softmmu();
@@ -1881,10 +1898,7 @@ static void hypercall_register_types(void)
spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt);
spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
hypercall_register_nested();
}
type_init(hypercall_register_types)
hw/ppc/spapr_rtas.c
+9 -9
View File
@@ -474,16 +474,16 @@ static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu,
if (spapr->fwnmi_machine_check_interlock != cpu->vcpu_id) {
/*
* The vCPU that hit the NMI should invoke "ibm,nmi-interlock"
* The vCPU that hit the NMI should invoke "ibm,nmi-interlock"
* This should be PARAM_ERROR, but Linux calls "ibm,nmi-interlock"
* for system reset interrupts, despite them not being interlocked.
* PowerVM silently ignores this and returns success here. Returning
* failure causes Linux to print the error "FWNMI: nmi-interlock
* failed: -3", although no other apparent ill effects, this is a
* regression for the user when enabling FWNMI. So for now, match
* PowerVM. When most Linux clients are fixed, this could be
* changed.
*/
* for system reset interrupts, despite them not being interlocked.
* PowerVM silently ignores this and returns success here. Returning
* failure causes Linux to print the error "FWNMI: nmi-interlock
* failed: -3", although no other apparent ill effects, this is a
* regression for the user when enabling FWNMI. So for now, match
* PowerVM. When most Linux clients are fixed, this could be
* changed.
*/
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
return;
}
hw/ppc/spapr_rtas_ddw.c
+1
View File
@@ -72,6 +72,7 @@ static uint32_t spapr_page_mask_to_query_mask(uint64_t page_mask)
const struct { int shift; uint32_t mask; } masks[] = {
{ 12, RTAS_DDW_PGSIZE_4K },
{ 16, RTAS_DDW_PGSIZE_64K },
{ 21, RTAS_DDW_PGSIZE_2M },
{ 24, RTAS_DDW_PGSIZE_16M },
{ 25, RTAS_DDW_PGSIZE_32M },
{ 26, RTAS_DDW_PGSIZE_64M },
hw/ppc/vof.c
+1 -1
View File
@@ -293,7 +293,7 @@ static uint32_t vof_setprop(MachineState *ms, void *fdt, Vof *vof,
uint32_t nodeph, uint32_t pname,
uint32_t valaddr, uint32_t vallen)
{
char propname[OF_PROPNAME_LEN_MAX + 1];
char propname[OF_PROPNAME_LEN_MAX + 1] = "";
uint32_t ret = PROM_ERROR;
int offset, rc;
char trval[64] = "";
include/fpu/softfloat.h
+7
View File
@@ -95,6 +95,7 @@ typedef enum {
#include "fpu/softfloat-types.h"
#include "fpu/softfloat-helpers.h"
#include "qemu/int128.h"
/*----------------------------------------------------------------------------
| Routine to raise any or all of the software IEC/IEEE floating-point
@@ -182,7 +183,9 @@ floatx80 int64_to_floatx80(int64_t, float_status *status);
float128 int32_to_float128(int32_t, float_status *status);
float128 int64_to_float128(int64_t, float_status *status);
float128 int128_to_float128(Int128, float_status *status);
float128 uint64_to_float128(uint64_t, float_status *status);
float128 uint128_to_float128(Int128, float_status *status);
/*----------------------------------------------------------------------------
| Software half-precision conversion routines.
@@ -1201,9 +1204,13 @@ floatx80 floatx80_default_nan(float_status *status);
int32_t float128_to_int32(float128, float_status *status);
int32_t float128_to_int32_round_to_zero(float128, float_status *status);
int64_t float128_to_int64(float128, float_status *status);
Int128 float128_to_int128(float128, float_status *status);
int64_t float128_to_int64_round_to_zero(float128, float_status *status);
Int128 float128_to_int128_round_to_zero(float128, float_status *status);
uint64_t float128_to_uint64(float128, float_status *status);
Int128 float128_to_uint128(float128, float_status *status);
uint64_t float128_to_uint64_round_to_zero(float128, float_status *status);
Int128 float128_to_uint128_round_to_zero(float128, float_status *status);
uint32_t float128_to_uint32(float128, float_status *status);
uint32_t float128_to_uint32_round_to_zero(float128, float_status *status);
float32 float128_to_float32(float128, float_status *status);
include/hw/ppc/pnv_lpc.h
+2 -6
View File
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV LPC controller
*
* Copyright (c) 2016, IBM Corporation.
* Copyright (c) 2016-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -20,7 +20,6 @@
#ifndef PPC_PNV_LPC_H
#define PPC_PNV_LPC_H
#include "hw/ppc/pnv_psi.h"
#include "qom/object.h"
#define TYPE_PNV_LPC "pnv-lpc"
@@ -84,15 +83,12 @@ struct PnvLpcController {
MemoryRegion xscom_regs;
/* PSI to generate interrupts */
PnvPsi *psi;
qemu_irq psi_irq;
};
struct PnvLpcClass {
DeviceClass parent_class;
int psi_irq;
DeviceRealize parent_realize;
};
include/hw/ppc/pnv_occ.h
+2 -5
View File
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV Emulation of a few OCC related registers
*
* Copyright (c) 2015-2017, IBM Corporation.
* Copyright (c) 2015-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -20,7 +20,6 @@
#ifndef PPC_PNV_OCC_H
#define PPC_PNV_OCC_H
#include "hw/ppc/pnv_psi.h"
#include "qom/object.h"
#define TYPE_PNV_OCC "pnv-occ"
@@ -44,19 +43,17 @@ struct PnvOCC {
/* OCC Misc interrupt */
uint64_t occmisc;
PnvPsi *psi;
qemu_irq psi_irq;
MemoryRegion xscom_regs;
MemoryRegion sram_regs;
};
struct PnvOCCClass {
DeviceClass parent_class;
int xscom_size;
const MemoryRegionOps *xscom_ops;
int psi_irq;
};
#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
include/hw/ppc/pnv_psi.h
+1 -6
View File
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV Processor Service Interface (PSI) model
*
* Copyright (c) 2015-2017, IBM Corporation.
* Copyright (c) 2015-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -79,13 +79,10 @@ struct PnvPsiClass {
uint64_t bar_mask;
const char *compat;
int compat_size;
void (*irq_set)(PnvPsi *psi, int, bool state);
};
/* The PSI and FSP interrupts are muxed on the same IRQ number */
typedef enum PnvPsiIrq {
PSIHB_IRQ_PSI, /* internal use only */
PSIHB_IRQ_FSP, /* internal use only */
PSIHB_IRQ_OCC,
PSIHB_IRQ_FSI,
@@ -96,8 +93,6 @@ typedef enum PnvPsiIrq {
#define PSI_NUM_INTERRUPTS 6
void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
/* P9 PSI Interrupts */
#define PSIHB9_IRQ_PSI 0
#define PSIHB9_IRQ_OCC 1
include/hw/ppc/ppc.h
+5 -5
View File
@@ -99,11 +99,11 @@ enum {
ARCH_MAC99_U3,
};
#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)

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