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Merge tag 'pull-request-2022-11-08' of https://gitlab.com/thuth/qemu into staging

Browse Source 
* Last minute s390x fixes before the hard freeze
* Whiste space clean-up in ui/, display/ and hw/usb/

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# gpg: Signature made Tue 08 Nov 2022 06:29:33 EST
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2022-11-08' of https://gitlab.com/thuth/qemu:
  hw/usb: fix tab indentation
  hw/display: fix tab indentation
  ui: fix tab indentation
  s390x/s390-virtio-ccw: Switch off zPCI enhancements on older machines
  Revert "s390x/s390-virtio-ccw: add zpcii-disable machine property"

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
2022-11-08 11:34:06 -05:00
parent 3ba5fe46ea 6c10e08a4f
commit ade760a2f6
22 changed files with 7372 additions and 7404 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/display/blizzard.c
+176 -176
View File
File diff suppressed because it is too large Load Diff
hw/display/cirrus_vga.c
+800 -800
View File
File diff suppressed because it is too large Load Diff
hw/display/omap_dss.c
+299 -299
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File diff suppressed because it is too large Load Diff
hw/display/pxa2xx_lcd.c
+92 -92
View File
@@ -86,106 +86,106 @@ typedef struct QEMU_PACKED {
uint32_t ldcmd;
} PXAFrameDescriptor;
#define LCCR0 0x000 /* LCD Controller Control register 0 */
#define LCCR1 0x004 /* LCD Controller Control register 1 */
#define LCCR2 0x008 /* LCD Controller Control register 2 */
#define LCCR3 0x00c /* LCD Controller Control register 3 */
#define LCCR4 0x010 /* LCD Controller Control register 4 */
#define LCCR5 0x014 /* LCD Controller Control register 5 */
#define LCCR0 0x000 /* LCD Controller Control register 0 */
#define LCCR1 0x004 /* LCD Controller Control register 1 */
#define LCCR2 0x008 /* LCD Controller Control register 2 */
#define LCCR3 0x00c /* LCD Controller Control register 3 */
#define LCCR4 0x010 /* LCD Controller Control register 4 */
#define LCCR5 0x014 /* LCD Controller Control register 5 */
#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
#define LCSR1 0x034 /* LCD Controller Status register 1 */
#define LCSR0 0x038 /* LCD Controller Status register 0 */
#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
#define LCSR1 0x034 /* LCD Controller Status register 1 */
#define LCSR0 0x038 /* LCD Controller Status register 0 */
#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
#define TRGBR 0x040 /* TMED RGB Seed register */
#define TCR 0x044 /* TMED Control register */
#define TRGBR 0x040 /* TMED RGB Seed register */
#define TCR 0x044 /* TMED Control register */
#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
#define CCR 0x090 /* Cursor Control register */
#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
#define CCR 0x090 /* Cursor Control register */
#define CMDCR 0x100 /* Command Control register */
#define PRSR 0x104 /* Panel Read Status register */
#define CMDCR 0x100 /* Command Control register */
#define PRSR 0x104 /* Panel Read Status register */
#define PXA_LCDDMA_CHANS 7
#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
#define DMA_FSADR 0x04 /* Frame Source Address register */
#define DMA_FIDR 0x08 /* Frame ID register */
#define DMA_LDCMD 0x0c /* Command register */
#define PXA_LCDDMA_CHANS 7
#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
#define DMA_FSADR 0x04 /* Frame Source Address register */
#define DMA_FIDR 0x08 /* Frame ID register */
#define DMA_LDCMD 0x0c /* Command register */
/* LCD Buffer Strength Control register */
#define BSCNTR 0x04000054
#define BSCNTR 0x04000054
/* Bitfield masks */
#define LCCR0_ENB (1 << 0)
#define LCCR0_CMS (1 << 1)
#define LCCR0_SDS (1 << 2)
#define LCCR0_LDM (1 << 3)
#define LCCR0_SOFM0 (1 << 4)
#define LCCR0_IUM (1 << 5)
#define LCCR0_EOFM0 (1 << 6)
#define LCCR0_PAS (1 << 7)
#define LCCR0_DPD (1 << 9)
#define LCCR0_DIS (1 << 10)
#define LCCR0_QDM (1 << 11)
#define LCCR0_PDD (0xff << 12)
#define LCCR0_BSM0 (1 << 20)
#define LCCR0_OUM (1 << 21)
#define LCCR0_LCDT (1 << 22)
#define LCCR0_RDSTM (1 << 23)
#define LCCR0_CMDIM (1 << 24)
#define LCCR0_OUC (1 << 25)
#define LCCR0_LDDALT (1 << 26)
#define LCCR1_PPL(x) ((x) & 0x3ff)
#define LCCR2_LPP(x) ((x) & 0x3ff)
#define LCCR3_API (15 << 16)
#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
#define LCCR4_K1(x) (((x) >> 0) & 7)
#define LCCR4_K2(x) (((x) >> 3) & 7)
#define LCCR4_K3(x) (((x) >> 6) & 7)
#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
#define LCCR5_SOFM(ch) (1 << (ch - 1))
#define LCCR5_EOFM(ch) (1 << (ch + 7))
#define LCCR5_BSM(ch) (1 << (ch + 15))
#define LCCR5_IUM(ch) (1 << (ch + 23))
#define OVLC1_EN (1 << 31)
#define CCR_CEN (1 << 31)
#define FBR_BRA (1 << 0)
#define FBR_BINT (1 << 1)
#define FBR_SRCADDR (0xfffffff << 4)
#define LCSR0_LDD (1 << 0)
#define LCSR0_SOF0 (1 << 1)
#define LCSR0_BER (1 << 2)
#define LCSR0_ABC (1 << 3)
#define LCSR0_IU0 (1 << 4)
#define LCSR0_IU1 (1 << 5)
#define LCSR0_OU (1 << 6)
#define LCSR0_QD (1 << 7)
#define LCSR0_EOF0 (1 << 8)
#define LCSR0_BS0 (1 << 9)
#define LCSR0_SINT (1 << 10)
#define LCSR0_RDST (1 << 11)
#define LCSR0_CMDINT (1 << 12)
#define LCSR0_BERCH(x) (((x) & 7) << 28)
#define LCSR1_SOF(ch) (1 << (ch - 1))
#define LCSR1_EOF(ch) (1 << (ch + 7))
#define LCSR1_BS(ch) (1 << (ch + 15))
#define LCSR1_IU(ch) (1 << (ch + 23))
#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
#define LDCMD_EOFINT (1 << 21)
#define LDCMD_SOFINT (1 << 22)
#define LDCMD_PAL (1 << 26)
#define LCCR0_ENB (1 << 0)
#define LCCR0_CMS (1 << 1)
#define LCCR0_SDS (1 << 2)
#define LCCR0_LDM (1 << 3)
#define LCCR0_SOFM0 (1 << 4)
#define LCCR0_IUM (1 << 5)
#define LCCR0_EOFM0 (1 << 6)
#define LCCR0_PAS (1 << 7)
#define LCCR0_DPD (1 << 9)
#define LCCR0_DIS (1 << 10)
#define LCCR0_QDM (1 << 11)
#define LCCR0_PDD (0xff << 12)
#define LCCR0_BSM0 (1 << 20)
#define LCCR0_OUM (1 << 21)
#define LCCR0_LCDT (1 << 22)
#define LCCR0_RDSTM (1 << 23)
#define LCCR0_CMDIM (1 << 24)
#define LCCR0_OUC (1 << 25)
#define LCCR0_LDDALT (1 << 26)
#define LCCR1_PPL(x) ((x) & 0x3ff)
#define LCCR2_LPP(x) ((x) & 0x3ff)
#define LCCR3_API (15 << 16)
#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
#define LCCR4_K1(x) (((x) >> 0) & 7)
#define LCCR4_K2(x) (((x) >> 3) & 7)
#define LCCR4_K3(x) (((x) >> 6) & 7)
#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
#define LCCR5_SOFM(ch) (1 << (ch - 1))
#define LCCR5_EOFM(ch) (1 << (ch + 7))
#define LCCR5_BSM(ch) (1 << (ch + 15))
#define LCCR5_IUM(ch) (1 << (ch + 23))
#define OVLC1_EN (1 << 31)
#define CCR_CEN (1 << 31)
#define FBR_BRA (1 << 0)
#define FBR_BINT (1 << 1)
#define FBR_SRCADDR (0xfffffff << 4)
#define LCSR0_LDD (1 << 0)
#define LCSR0_SOF0 (1 << 1)
#define LCSR0_BER (1 << 2)
#define LCSR0_ABC (1 << 3)
#define LCSR0_IU0 (1 << 4)
#define LCSR0_IU1 (1 << 5)
#define LCSR0_OU (1 << 6)
#define LCSR0_QD (1 << 7)
#define LCSR0_EOF0 (1 << 8)
#define LCSR0_BS0 (1 << 9)
#define LCSR0_SINT (1 << 10)
#define LCSR0_RDST (1 << 11)
#define LCSR0_CMDINT (1 << 12)
#define LCSR0_BERCH(x) (((x) & 7) << 28)
#define LCSR1_SOF(ch) (1 << (ch - 1))
#define LCSR1_EOF(ch) (1 << (ch + 7))
#define LCSR1_BS(ch) (1 << (ch + 15))
#define LCSR1_IU(ch) (1 << (ch + 23))
#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
#define LDCMD_EOFINT (1 << 21)
#define LDCMD_SOFINT (1 << 22)
#define LDCMD_PAL (1 << 26)
/* Size of a pixel in the QEMU UI output surface, in bytes */
#define DEST_PIXEL_WIDTH 4
@@ -788,7 +788,7 @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
case TCR:
return s->tcr;
case 0x200 ... 0x1000: /* DMA per-channel registers */
case 0x200 ... 0x1000: /* DMA per-channel registers */
ch = (offset - 0x200) >> 4;
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
goto fail;
@@ -938,7 +938,7 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
s->tcr = value & 0x7fff;
break;
case 0x200 ... 0x1000: /* DMA per-channel registers */
case 0x200 ... 0x1000: /* DMA per-channel registers */
ch = (offset - 0x200) >> 4;
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
goto fail;
hw/display/vga_regs.h
+3 -3
View File
@@ -4,9 +4,9 @@
* Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
*
* Copyright history from vga16fb.c:
* Copyright 1999 Ben Pfaff and Petr Vandrovec
* Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
* Based on VESA framebuffer (c) 1998 Gerd Knorr
* Copyright 1999 Ben Pfaff and Petr Vandrovec
* Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
* Based on VESA framebuffer (c) 1998 Gerd Knorr
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
hw/display/xenfb.c
+129 -129
View File
@@ -76,7 +76,7 @@ struct XenFB {
int do_resize;
struct {
int x,y,w,h;
int x,y,w,h;
} up_rects[UP_QUEUE];
int up_count;
int up_fullscreen;
@@ -116,32 +116,32 @@ static void common_unbind(struct common *c)
xen_pv_unbind_evtchn(&c->xendev);
if (c->page) {
xenforeignmemory_unmap(xen_fmem, c->page, 1);
c->page = NULL;
c->page = NULL;
}
}
/* -------------------------------------------------------------------- */
/* Send an event to the keyboard frontend driver */
static int xenfb_kbd_event(struct XenInput *xenfb,
union xenkbd_in_event *event)
union xenkbd_in_event *event)
{
struct xenkbd_page *page = xenfb->c.page;
uint32_t prod;
if (xenfb->c.xendev.be_state != XenbusStateConnected)
return 0;
return 0;
if (!page)
return 0;
prod = page->in_prod;
if (prod - page->in_cons == XENKBD_IN_RING_LEN) {
errno = EAGAIN;
return -1;
errno = EAGAIN;
return -1;
}
xen_mb(); /* ensure ring space available */
xen_mb(); /* ensure ring space available */
XENKBD_IN_RING_REF(page, prod) = *event;
xen_wmb(); /* ensure ring contents visible */
xen_wmb(); /* ensure ring contents visible */
page->in_prod = prod + 1;
return xen_pv_send_notify(&xenfb->c.xendev);
}
@@ -161,7 +161,7 @@ static int xenfb_send_key(struct XenInput *xenfb, bool down, int keycode)
/* Send a relative mouse movement event */
static int xenfb_send_motion(struct XenInput *xenfb,
int rel_x, int rel_y, int rel_z)
int rel_x, int rel_y, int rel_z)
{
union xenkbd_in_event event;
@@ -176,7 +176,7 @@ static int xenfb_send_motion(struct XenInput *xenfb,
/* Send an absolute mouse movement event */
static int xenfb_send_position(struct XenInput *xenfb,
int abs_x, int abs_y, int z)
int abs_x, int abs_y, int z)
{
union xenkbd_in_event event;
@@ -354,7 +354,7 @@ static int input_initialise(struct XenLegacyDevice *xendev)
rc = common_bind(&in->c);
if (rc != 0)
return rc;
return rc;
return 0;
}
@@ -415,7 +415,7 @@ static void input_event(struct XenLegacyDevice *xendev)
/* We don't understand any keyboard events, so just ignore them. */
if (page->out_prod == page->out_cons)
return;
return;
page->out_cons = page->out_prod;
xen_pv_send_notify(&xenfb->c.xendev);
}
@@ -429,7 +429,7 @@ static void xenfb_copy_mfns(int mode, int count, xen_pfn_t *dst, void *src)
int i;
for (i = 0; i < count; i++)
dst[i] = (mode == 32) ? src32[i] : src64[i];
dst[i] = (mode == 32) ? src32[i] : src64[i];
}
static int xenfb_map_fb(struct XenFB *xenfb)
@@ -447,43 +447,43 @@ static int xenfb_map_fb(struct XenFB *xenfb)
mode = sizeof(unsigned long) * 8;
if (!protocol) {
/*
* Undefined protocol, some guesswork needed.
*
* Old frontends which don't set the protocol use
* one page directory only, thus pd[1] must be zero.
* pd[1] of the 32bit struct layout and the lower
* 32 bits of pd[0] of the 64bit struct layout have
* the same location, so we can check that ...
*/
uint32_t *ptr32 = NULL;
uint32_t *ptr64 = NULL;
/*
* Undefined protocol, some guesswork needed.
*
* Old frontends which don't set the protocol use
* one page directory only, thus pd[1] must be zero.
* pd[1] of the 32bit struct layout and the lower
* 32 bits of pd[0] of the 64bit struct layout have
* the same location, so we can check that ...
*/
uint32_t *ptr32 = NULL;
uint32_t *ptr64 = NULL;
#if defined(__i386__)
ptr32 = (void*)page->pd;
ptr64 = ((void*)page->pd) + 4;
ptr32 = (void*)page->pd;
ptr64 = ((void*)page->pd) + 4;
#elif defined(__x86_64__)
ptr32 = ((void*)page->pd) - 4;
ptr64 = (void*)page->pd;
ptr32 = ((void*)page->pd) - 4;
ptr64 = (void*)page->pd;
#endif
if (ptr32) {
if (ptr32[1] == 0) {
mode = 32;
pd = ptr32;
} else {
mode = 64;
pd = ptr64;
}
}
if (ptr32) {
if (ptr32[1] == 0) {
mode = 32;
pd = ptr32;
} else {
mode = 64;
pd = ptr64;
}
}
#if defined(__x86_64__)
} else if (strcmp(protocol, XEN_IO_PROTO_ABI_X86_32) == 0) {
/* 64bit dom0, 32bit domU */
mode = 32;
pd = ((void*)page->pd) - 4;
/* 64bit dom0, 32bit domU */
mode = 32;
pd = ((void*)page->pd) - 4;
#elif defined(__i386__)
} else if (strcmp(protocol, XEN_IO_PROTO_ABI_X86_64) == 0) {
/* 32bit dom0, 64bit domU */
mode = 64;
pd = ((void*)page->pd) + 4;
/* 32bit dom0, 64bit domU */
mode = 64;
pd = ((void*)page->pd) + 4;
#endif
}
@@ -503,14 +503,14 @@ static int xenfb_map_fb(struct XenFB *xenfb)
map = xenforeignmemory_map(xen_fmem, xenfb->c.xendev.dom,
PROT_READ, n_fbdirs, pgmfns, NULL);
if (map == NULL)
goto out;
goto out;
xenfb_copy_mfns(mode, xenfb->fbpages, fbmfns, map);
xenforeignmemory_unmap(xen_fmem, map, n_fbdirs);
xenfb->pixels = xenforeignmemory_map(xen_fmem, xenfb->c.xendev.dom,
PROT_READ, xenfb->fbpages, fbmfns, NULL);
if (xenfb->pixels == NULL)
goto out;
goto out;
ret = 0; /* all is fine */
@@ -589,35 +589,35 @@ static int xenfb_configure_fb(struct XenFB *xenfb, size_t fb_len_lim,
/* A convenient function for munging pixels between different depths */
#define BLT(SRC_T,DST_T,RSB,GSB,BSB,RDB,GDB,BDB) \
for (line = y ; line < (y+h) ; line++) { \
SRC_T *src = (SRC_T *)(xenfb->pixels \
+ xenfb->offset \
+ (line * xenfb->row_stride) \
+ (x * xenfb->depth / 8)); \
DST_T *dst = (DST_T *)(data \
+ (line * linesize) \
+ (x * bpp / 8)); \
int col; \
const int RSS = 32 - (RSB + GSB + BSB); \
const int GSS = 32 - (GSB + BSB); \
const int BSS = 32 - (BSB); \
const uint32_t RSM = (~0U) << (32 - RSB); \
const uint32_t GSM = (~0U) << (32 - GSB); \
const uint32_t BSM = (~0U) << (32 - BSB); \
const int RDS = 32 - (RDB + GDB + BDB); \
const int GDS = 32 - (GDB + BDB); \
const int BDS = 32 - (BDB); \
const uint32_t RDM = (~0U) << (32 - RDB); \
const uint32_t GDM = (~0U) << (32 - GDB); \
const uint32_t BDM = (~0U) << (32 - BDB); \
for (col = x ; col < (x+w) ; col++) { \
uint32_t spix = *src; \
*dst = (((spix << RSS) & RSM & RDM) >> RDS) | \
(((spix << GSS) & GSM & GDM) >> GDS) | \
(((spix << BSS) & BSM & BDM) >> BDS); \
src = (SRC_T *) ((unsigned long) src + xenfb->depth / 8); \
dst = (DST_T *) ((unsigned long) dst + bpp / 8); \
} \
for (line = y ; line < (y+h) ; line++) { \
SRC_T *src = (SRC_T *)(xenfb->pixels \
+ xenfb->offset \
+ (line * xenfb->row_stride) \
+ (x * xenfb->depth / 8)); \
DST_T *dst = (DST_T *)(data \
+ (line * linesize) \
+ (x * bpp / 8)); \
int col; \
const int RSS = 32 - (RSB + GSB + BSB); \
const int GSS = 32 - (GSB + BSB); \
const int BSS = 32 - (BSB); \
const uint32_t RSM = (~0U) << (32 - RSB); \
const uint32_t GSM = (~0U) << (32 - GSB); \
const uint32_t BSM = (~0U) << (32 - BSB); \
const int RDS = 32 - (RDB + GDB + BDB); \
const int GDS = 32 - (GDB + BDB); \
const int BDS = 32 - (BDB); \
const uint32_t RDM = (~0U) << (32 - RDB); \
const uint32_t GDM = (~0U) << (32 - GDB); \
const uint32_t BDM = (~0U) << (32 - BDB); \
for (col = x ; col < (x+w) ; col++) { \
uint32_t spix = *src; \
*dst = (((spix << RSS) & RSM & RDM) >> RDS) | \
(((spix << GSS) & GSM & GDM) >> GDS) | \
(((spix << BSS) & BSM & BDM) >> BDS); \
src = (SRC_T *) ((unsigned long) src + xenfb->depth / 8); \
dst = (DST_T *) ((unsigned long) dst + bpp / 8); \
} \
}
@@ -657,7 +657,7 @@ static void xenfb_guest_copy(struct XenFB *xenfb, int x, int y, int w, int h)
break;
default:
oops = 1;
}
}
}
if (oops) /* should not happen */
xen_pv_printf(&xenfb->c.xendev, 0, "%s: oops: convert %d -> %d bpp?\n",
@@ -816,60 +816,60 @@ static void xenfb_handle_events(struct XenFB *xenfb)
if (prod - out_cons > XENFB_OUT_RING_LEN) {
return;
}
xen_rmb(); /* ensure we see ring contents up to prod */
xen_rmb(); /* ensure we see ring contents up to prod */
for (cons = out_cons; cons != prod; cons++) {
union xenfb_out_event *event = &XENFB_OUT_RING_REF(page, cons);
union xenfb_out_event *event = &XENFB_OUT_RING_REF(page, cons);
uint8_t type = event->type;
int x, y, w, h;
int x, y, w, h;
switch (type) {
case XENFB_TYPE_UPDATE:
if (xenfb->up_count == UP_QUEUE)
xenfb->up_fullscreen = 1;
if (xenfb->up_fullscreen)
break;
x = MAX(event->update.x, 0);
y = MAX(event->update.y, 0);
w = MIN(event->update.width, xenfb->width - x);
h = MIN(event->update.height, xenfb->height - y);
if (w < 0 || h < 0) {
switch (type) {
case XENFB_TYPE_UPDATE:
if (xenfb->up_count == UP_QUEUE)
xenfb->up_fullscreen = 1;
if (xenfb->up_fullscreen)
break;
x = MAX(event->update.x, 0);
y = MAX(event->update.y, 0);
w = MIN(event->update.width, xenfb->width - x);
h = MIN(event->update.height, xenfb->height - y);
if (w < 0 || h < 0) {
xen_pv_printf(&xenfb->c.xendev, 1, "bogus update ignored\n");
break;
}
if (x != event->update.x ||
break;
}
if (x != event->update.x ||
y != event->update.y ||
w != event->update.width ||
h != event->update.height) {
w != event->update.width ||
h != event->update.height) {
xen_pv_printf(&xenfb->c.xendev, 1, "bogus update clipped\n");
}
if (w == xenfb->width && h > xenfb->height / 2) {
/* scroll detector: updated more than 50% of the lines,
* don't bother keeping track of the rectangles then */
xenfb->up_fullscreen = 1;
} else {
xenfb->up_rects[xenfb->up_count].x = x;
xenfb->up_rects[xenfb->up_count].y = y;
xenfb->up_rects[xenfb->up_count].w = w;
xenfb->up_rects[xenfb->up_count].h = h;
xenfb->up_count++;
}
break;
}
if (w == xenfb->width && h > xenfb->height / 2) {
/* scroll detector: updated more than 50% of the lines,
* don't bother keeping track of the rectangles then */
xenfb->up_fullscreen = 1;
} else {
xenfb->up_rects[xenfb->up_count].x = x;
xenfb->up_rects[xenfb->up_count].y = y;
xenfb->up_rects[xenfb->up_count].w = w;
xenfb->up_rects[xenfb->up_count].h = h;
xenfb->up_count++;
}
break;
#ifdef XENFB_TYPE_RESIZE
case XENFB_TYPE_RESIZE:
if (xenfb_configure_fb(xenfb, xenfb->fb_len,
event->resize.width,
event->resize.height,
event->resize.depth,
xenfb->fb_len,
event->resize.offset,
event->resize.stride) < 0)
break;
xenfb_invalidate(xenfb);
break;
case XENFB_TYPE_RESIZE:
if (xenfb_configure_fb(xenfb, xenfb->fb_len,
event->resize.width,
event->resize.height,
event->resize.depth,
xenfb->fb_len,
event->resize.offset,
event->resize.stride) < 0)
break;
xenfb_invalidate(xenfb);
break;
#endif
}
}
}
xen_mb(); /* ensure we're done with ring contents */
xen_mb(); /* ensure we're done with ring contents */
page->out_cons = cons;
}
@@ -889,32 +889,32 @@ static int fb_initialise(struct XenLegacyDevice *xendev)
int rc;
if (xenstore_read_fe_int(xendev, "videoram", &videoram) == -1)
videoram = 0;
videoram = 0;
rc = common_bind(&fb->c);
if (rc != 0)
return rc;
return rc;
fb_page = fb->c.page;
rc = xenfb_configure_fb(fb, videoram * MiB,
fb_page->width, fb_page->height, fb_page->depth,
fb_page->mem_length, 0, fb_page->line_length);
fb_page->width, fb_page->height, fb_page->depth,
fb_page->mem_length, 0, fb_page->line_length);
if (rc != 0)
return rc;
return rc;
rc = xenfb_map_fb(fb);
if (rc != 0)
return rc;
return rc;
fb->con = graphic_console_init(NULL, 0, &xenfb_ops, fb);
if (xenstore_read_fe_int(xendev, "feature-update", &fb->feature_update) == -1)
fb->feature_update = 0;
fb->feature_update = 0;
if (fb->feature_update)
xenstore_write_be_int(xendev, "request-update", 1);
xenstore_write_be_int(xendev, "request-update", 1);
xen_pv_printf(xendev, 1, "feature-update=%d, videoram=%d\n",
fb->feature_update, videoram);
fb->feature_update, videoram);
return 0;
}
hw/s390x/s390-pci-kvm.c
+1 -3
View File
@@ -22,9 +22,7 @@
bool s390_pci_kvm_interp_allowed(void)
{
return (kvm_s390_get_zpci_op() && !s390_is_pv() &&
!object_property_get_bool(OBJECT(qdev_get_machine()),
"zpcii-disable", NULL));
return kvm_s390_get_zpci_op() && !s390_is_pv();
}
int s390_pci_kvm_aif_enable(S390PCIBusDevice *pbdev, ZpciFib *fib, bool assist)
hw/s390x/s390-virtio-ccw.c
+5 -24
View File
@@ -627,21 +627,6 @@ static inline void machine_set_dea_key_wrap(Object *obj, bool value,
ms->dea_key_wrap = value;
}
static inline bool machine_get_zpcii_disable(Object *obj, Error **errp)
{
S390CcwMachineState *ms = S390_CCW_MACHINE(obj);
return ms->zpcii_disable;
}
static inline void machine_set_zpcii_disable(Object *obj, bool value,
Error **errp)
{
S390CcwMachineState *ms = S390_CCW_MACHINE(obj);
ms->zpcii_disable = value;
}
static S390CcwMachineClass *current_mc;
/*
@@ -778,12 +763,6 @@ static void ccw_machine_class_init(ObjectClass *oc, void *data)
"Up to 8 chars in set of [A-Za-z0-9. ] (lower case chars converted"
" to upper case) to pass to machine loader, boot manager,"
" and guest kernel");
object_class_property_add_bool(oc, "zpcii-disable",
machine_get_zpcii_disable,
machine_set_zpcii_disable);
object_class_property_set_description(oc, "zpcii-disable",
"disable zPCI interpretation facilties");
}
static inline void s390_machine_initfn(Object *obj)
@@ -792,7 +771,6 @@ static inline void s390_machine_initfn(Object *obj)
ms->aes_key_wrap = true;
ms->dea_key_wrap = true;
ms->zpcii_disable = false;
}
static const TypeInfo ccw_machine_info = {
@@ -857,20 +835,23 @@ DEFINE_CCW_MACHINE(7_2, "7.2", true);
static void ccw_machine_7_1_instance_options(MachineState *machine)
{
static const S390FeatInit qemu_cpu_feat = { S390_FEAT_LIST_QEMU_V7_1 };
S390CcwMachineState *ms = S390_CCW_MACHINE(machine);
ccw_machine_7_2_instance_options(machine);
s390_cpudef_featoff_greater(16, 1, S390_FEAT_PAIE);
s390_set_qemu_cpu_model(0x8561, 15, 1, qemu_cpu_feat);
ms->zpcii_disable = true;
}
static void ccw_machine_7_1_class_options(MachineClass *mc)
{
S390CcwMachineClass *s390mc = S390_CCW_MACHINE_CLASS(mc);
static GlobalProperty compat[] = {
{ TYPE_S390_PCI_DEVICE, "interpret", "off", },
{ TYPE_S390_PCI_DEVICE, "forwarding-assist", "off", },
};
ccw_machine_7_2_class_options(mc);
compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
s390mc->max_threads = S390_MAX_CPUS;
}
DEFINE_CCW_MACHINE(7_1, "7.1", false);
hw/usb/dev-hub.c
+39 -39
View File
@@ -54,44 +54,44 @@ struct USBHubState {
#define TYPE_USB_HUB "usb-hub"
OBJECT_DECLARE_SIMPLE_TYPE(USBHubState, USB_HUB)
#define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
#define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
#define GetHubDescriptor (0xa000 | USB_REQ_GET_DESCRIPTOR)
#define GetHubStatus (0xa000 | USB_REQ_GET_STATUS)
#define GetPortStatus (0xa300 | USB_REQ_GET_STATUS)
#define SetHubFeature (0x2000 | USB_REQ_SET_FEATURE)
#define SetPortFeature (0x2300 | USB_REQ_SET_FEATURE)
#define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
#define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
#define GetHubDescriptor (0xa000 | USB_REQ_GET_DESCRIPTOR)
#define GetHubStatus (0xa000 | USB_REQ_GET_STATUS)
#define GetPortStatus (0xa300 | USB_REQ_GET_STATUS)
#define SetHubFeature (0x2000 | USB_REQ_SET_FEATURE)
#define SetPortFeature (0x2300 | USB_REQ_SET_FEATURE)
#define PORT_STAT_CONNECTION 0x0001
#define PORT_STAT_ENABLE 0x0002
#define PORT_STAT_SUSPEND 0x0004
#define PORT_STAT_OVERCURRENT 0x0008
#define PORT_STAT_RESET 0x0010
#define PORT_STAT_POWER 0x0100
#define PORT_STAT_LOW_SPEED 0x0200
#define PORT_STAT_CONNECTION 0x0001
#define PORT_STAT_ENABLE 0x0002
#define PORT_STAT_SUSPEND 0x0004
#define PORT_STAT_OVERCURRENT 0x0008
#define PORT_STAT_RESET 0x0010
#define PORT_STAT_POWER 0x0100
#define PORT_STAT_LOW_SPEED 0x0200
#define PORT_STAT_HIGH_SPEED 0x0400
#define PORT_STAT_TEST 0x0800
#define PORT_STAT_INDICATOR 0x1000
#define PORT_STAT_C_CONNECTION 0x0001
#define PORT_STAT_C_ENABLE 0x0002
#define PORT_STAT_C_SUSPEND 0x0004
#define PORT_STAT_C_OVERCURRENT 0x0008
#define PORT_STAT_C_RESET 0x0010
#define PORT_STAT_C_CONNECTION 0x0001
#define PORT_STAT_C_ENABLE 0x0002
#define PORT_STAT_C_SUSPEND 0x0004
#define PORT_STAT_C_OVERCURRENT 0x0008
#define PORT_STAT_C_RESET 0x0010
#define PORT_CONNECTION 0
#define PORT_ENABLE 1
#define PORT_SUSPEND 2
#define PORT_OVERCURRENT 3
#define PORT_RESET 4
#define PORT_POWER 8
#define PORT_LOWSPEED 9
#define PORT_HIGHSPEED 10
#define PORT_C_CONNECTION 16
#define PORT_C_ENABLE 17
#define PORT_C_SUSPEND 18
#define PORT_C_OVERCURRENT 19
#define PORT_C_RESET 20
#define PORT_CONNECTION 0
#define PORT_ENABLE 1
#define PORT_SUSPEND 2
#define PORT_OVERCURRENT 3
#define PORT_RESET 4
#define PORT_POWER 8
#define PORT_LOWSPEED 9
#define PORT_HIGHSPEED 10
#define PORT_C_CONNECTION 16
#define PORT_C_ENABLE 17
#define PORT_C_SUSPEND 18
#define PORT_C_OVERCURRENT 19
#define PORT_C_RESET 20
#define PORT_TEST 21
#define PORT_INDICATOR 22
@@ -155,13 +155,13 @@ static const USBDesc desc_hub = {
static const uint8_t qemu_hub_hub_descriptor[] =
{
0x00, /* u8 bLength; patched in later */
0x29, /* u8 bDescriptorType; Hub-descriptor */
0x00, /* u8 bNbrPorts; (patched later) */
0x0a, /* u16 wHubCharacteristics; */
0x00, /* (per-port OC, no power switching) */
0x01, /* u8 bPwrOn2pwrGood; 2ms */
0x00 /* u8 bHubContrCurrent; 0 mA */
0x00, /* u8 bLength; patched in later */
0x29, /* u8 bDescriptorType; Hub-descriptor */
0x00, /* u8 bNbrPorts; (patched later) */
0x0a, /* u16 wHubCharacteristics; */
0x00, /* (per-port OC, no power switching) */
0x01, /* u8 bPwrOn2pwrGood; 2ms */
0x00 /* u8 bHubContrCurrent; 0 mA */
/* DeviceRemovable and PortPwrCtrlMask patched in later */
};
hw/usb/dev-network.c
+143 -143
View File
@@ -52,7 +52,7 @@
#define RNDIS_PRODUCT_NUM 0xa4a2 /* Ethernet/RNDIS Gadget */
enum usbstring_idx {
STRING_MANUFACTURER = 1,
STRING_MANUFACTURER = 1,
STRING_PRODUCT,
STRING_ETHADDR,
STRING_DATA,
@@ -64,39 +64,39 @@ enum usbstring_idx {
STRING_SERIALNUMBER,
};
#define DEV_CONFIG_VALUE 1 /* CDC or a subset */
#define DEV_RNDIS_CONFIG_VALUE 2 /* RNDIS; optional */
#define DEV_CONFIG_VALUE 1 /* CDC or a subset */
#define DEV_RNDIS_CONFIG_VALUE 2 /* RNDIS; optional */
#define USB_CDC_SUBCLASS_ACM 0x02
#define USB_CDC_SUBCLASS_ETHERNET 0x06
#define USB_CDC_SUBCLASS_ACM 0x02
#define USB_CDC_SUBCLASS_ETHERNET 0x06
#define USB_CDC_PROTO_NONE 0
#define USB_CDC_ACM_PROTO_VENDOR 0xff
#define USB_CDC_PROTO_NONE 0
#define USB_CDC_ACM_PROTO_VENDOR 0xff
#define USB_CDC_HEADER_TYPE 0x00 /* header_desc */
#define USB_CDC_CALL_MANAGEMENT_TYPE 0x01 /* call_mgmt_descriptor */
#define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */
#define USB_CDC_UNION_TYPE 0x06 /* union_desc */
#define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */
#define USB_CDC_HEADER_TYPE 0x00 /* header_desc */
#define USB_CDC_CALL_MANAGEMENT_TYPE 0x01 /* call_mgmt_descriptor */
#define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */
#define USB_CDC_UNION_TYPE 0x06 /* union_desc */
#define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */
#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00
#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01
#define USB_CDC_REQ_SET_LINE_CODING 0x20
#define USB_CDC_REQ_GET_LINE_CODING 0x21
#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22
#define USB_CDC_REQ_SEND_BREAK 0x23
#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER 0x41
#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER 0x42
#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43
#define USB_CDC_GET_ETHERNET_STATISTIC 0x44
#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00
#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01
#define USB_CDC_REQ_SET_LINE_CODING 0x20
#define USB_CDC_REQ_GET_LINE_CODING 0x21
#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22
#define USB_CDC_REQ_SEND_BREAK 0x23
#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER 0x41
#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER 0x42
#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43
#define USB_CDC_GET_ETHERNET_STATISTIC 0x44
#define USB_CDC_NETWORK_CONNECTION 0x00
#define USB_CDC_NETWORK_CONNECTION 0x00
#define LOG2_STATUS_INTERVAL_MSEC 5 /* 1 << 5 == 32 msec */
#define STATUS_BYTECOUNT 16 /* 8 byte header + data */
#define LOG2_STATUS_INTERVAL_MSEC 5 /* 1 << 5 == 32 msec */
#define STATUS_BYTECOUNT 16 /* 8 byte header + data */
#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */
#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */
static const USBDescStrings usb_net_stringtable = {
[STRING_MANUFACTURER] = "QEMU",
@@ -306,57 +306,57 @@ static const USBDesc desc_net = {
/*
* RNDIS Definitions - in theory not specific to USB.
*/
#define RNDIS_MAXIMUM_FRAME_SIZE 1518
#define RNDIS_MAX_TOTAL_SIZE 1558
#define RNDIS_MAXIMUM_FRAME_SIZE 1518
#define RNDIS_MAX_TOTAL_SIZE 1558
/* Remote NDIS Versions */
#define RNDIS_MAJOR_VERSION 1
#define RNDIS_MINOR_VERSION 0
#define RNDIS_MAJOR_VERSION 1
#define RNDIS_MINOR_VERSION 0
/* Status Values */
#define RNDIS_STATUS_SUCCESS 0x00000000U /* Success */
#define RNDIS_STATUS_FAILURE 0xc0000001U /* Unspecified error */
#define RNDIS_STATUS_INVALID_DATA 0xc0010015U /* Invalid data */
#define RNDIS_STATUS_NOT_SUPPORTED 0xc00000bbU /* Unsupported request */
#define RNDIS_STATUS_MEDIA_CONNECT 0x4001000bU /* Device connected */
#define RNDIS_STATUS_MEDIA_DISCONNECT 0x4001000cU /* Device disconnected */
#define RNDIS_STATUS_SUCCESS 0x00000000U /* Success */
#define RNDIS_STATUS_FAILURE 0xc0000001U /* Unspecified error */
#define RNDIS_STATUS_INVALID_DATA 0xc0010015U /* Invalid data */
#define RNDIS_STATUS_NOT_SUPPORTED 0xc00000bbU /* Unsupported request */
#define RNDIS_STATUS_MEDIA_CONNECT 0x4001000bU /* Device connected */
#define RNDIS_STATUS_MEDIA_DISCONNECT 0x4001000cU /* Device disconnected */
/* Message Set for Connectionless (802.3) Devices */
enum {
RNDIS_PACKET_MSG = 1,
RNDIS_INITIALIZE_MSG = 2, /* Initialize device */
RNDIS_HALT_MSG = 3,
RNDIS_QUERY_MSG = 4,
RNDIS_SET_MSG = 5,
RNDIS_RESET_MSG = 6,
RNDIS_INDICATE_STATUS_MSG = 7,
RNDIS_KEEPALIVE_MSG = 8,
RNDIS_PACKET_MSG = 1,
RNDIS_INITIALIZE_MSG = 2, /* Initialize device */
RNDIS_HALT_MSG = 3,
RNDIS_QUERY_MSG = 4,
RNDIS_SET_MSG = 5,
RNDIS_RESET_MSG = 6,
RNDIS_INDICATE_STATUS_MSG = 7,
RNDIS_KEEPALIVE_MSG = 8,
};
/* Message completion */
enum {
RNDIS_INITIALIZE_CMPLT = 0x80000002U,
RNDIS_QUERY_CMPLT = 0x80000004U,
RNDIS_SET_CMPLT = 0x80000005U,
RNDIS_RESET_CMPLT = 0x80000006U,
RNDIS_KEEPALIVE_CMPLT = 0x80000008U,
RNDIS_INITIALIZE_CMPLT = 0x80000002U,
RNDIS_QUERY_CMPLT = 0x80000004U,
RNDIS_SET_CMPLT = 0x80000005U,
RNDIS_RESET_CMPLT = 0x80000006U,
RNDIS_KEEPALIVE_CMPLT = 0x80000008U,
};
/* Device Flags */
enum {
RNDIS_DF_CONNECTIONLESS = 1,
RNDIS_DF_CONNECTIONORIENTED = 2,
RNDIS_DF_CONNECTIONLESS = 1,
RNDIS_DF_CONNECTIONORIENTED = 2,
};
#define RNDIS_MEDIUM_802_3 0x00000000U
#define RNDIS_MEDIUM_802_3 0x00000000U
/* from drivers/net/sk98lin/h/skgepnmi.h */
#define OID_PNP_CAPABILITIES 0xfd010100
#define OID_PNP_SET_POWER 0xfd010101
#define OID_PNP_QUERY_POWER 0xfd010102
#define OID_PNP_ADD_WAKE_UP_PATTERN 0xfd010103
#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xfd010104
#define OID_PNP_ENABLE_WAKE_UP 0xfd010106
#define OID_PNP_CAPABILITIES 0xfd010100
#define OID_PNP_SET_POWER 0xfd010101
#define OID_PNP_QUERY_POWER 0xfd010102
#define OID_PNP_ADD_WAKE_UP_PATTERN 0xfd010103
#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xfd010104
#define OID_PNP_ENABLE_WAKE_UP 0xfd010106
typedef uint32_t le32;
@@ -494,88 +494,88 @@ enum rndis_state
/* from ndis.h */
enum ndis_oid {
/* Required Object IDs (OIDs) */
OID_GEN_SUPPORTED_LIST = 0x00010101,
OID_GEN_HARDWARE_STATUS = 0x00010102,
OID_GEN_MEDIA_SUPPORTED = 0x00010103,
OID_GEN_MEDIA_IN_USE = 0x00010104,
OID_GEN_MAXIMUM_LOOKAHEAD = 0x00010105,
OID_GEN_MAXIMUM_FRAME_SIZE = 0x00010106,
OID_GEN_LINK_SPEED = 0x00010107,
OID_GEN_TRANSMIT_BUFFER_SPACE = 0x00010108,
OID_GEN_RECEIVE_BUFFER_SPACE = 0x00010109,
OID_GEN_TRANSMIT_BLOCK_SIZE = 0x0001010a,
OID_GEN_RECEIVE_BLOCK_SIZE = 0x0001010b,
OID_GEN_VENDOR_ID = 0x0001010c,
OID_GEN_VENDOR_DESCRIPTION = 0x0001010d,
OID_GEN_CURRENT_PACKET_FILTER = 0x0001010e,
OID_GEN_CURRENT_LOOKAHEAD = 0x0001010f,
OID_GEN_DRIVER_VERSION = 0x00010110,
OID_GEN_MAXIMUM_TOTAL_SIZE = 0x00010111,
OID_GEN_PROTOCOL_OPTIONS = 0x00010112,
OID_GEN_MAC_OPTIONS = 0x00010113,
OID_GEN_MEDIA_CONNECT_STATUS = 0x00010114,
OID_GEN_MAXIMUM_SEND_PACKETS = 0x00010115,
OID_GEN_VENDOR_DRIVER_VERSION = 0x00010116,
OID_GEN_SUPPORTED_GUIDS = 0x00010117,
OID_GEN_NETWORK_LAYER_ADDRESSES = 0x00010118,
OID_GEN_TRANSPORT_HEADER_OFFSET = 0x00010119,
OID_GEN_MACHINE_NAME = 0x0001021a,
OID_GEN_RNDIS_CONFIG_PARAMETER = 0x0001021b,
OID_GEN_VLAN_ID = 0x0001021c,
OID_GEN_SUPPORTED_LIST = 0x00010101,
OID_GEN_HARDWARE_STATUS = 0x00010102,
OID_GEN_MEDIA_SUPPORTED = 0x00010103,
OID_GEN_MEDIA_IN_USE = 0x00010104,
OID_GEN_MAXIMUM_LOOKAHEAD = 0x00010105,
OID_GEN_MAXIMUM_FRAME_SIZE = 0x00010106,
OID_GEN_LINK_SPEED = 0x00010107,
OID_GEN_TRANSMIT_BUFFER_SPACE = 0x00010108,
OID_GEN_RECEIVE_BUFFER_SPACE = 0x00010109,
OID_GEN_TRANSMIT_BLOCK_SIZE = 0x0001010a,
OID_GEN_RECEIVE_BLOCK_SIZE = 0x0001010b,
OID_GEN_VENDOR_ID = 0x0001010c,
OID_GEN_VENDOR_DESCRIPTION = 0x0001010d,
OID_GEN_CURRENT_PACKET_FILTER = 0x0001010e,
OID_GEN_CURRENT_LOOKAHEAD = 0x0001010f,
OID_GEN_DRIVER_VERSION = 0x00010110,
OID_GEN_MAXIMUM_TOTAL_SIZE = 0x00010111,
OID_GEN_PROTOCOL_OPTIONS = 0x00010112,
OID_GEN_MAC_OPTIONS = 0x00010113,
OID_GEN_MEDIA_CONNECT_STATUS = 0x00010114,
OID_GEN_MAXIMUM_SEND_PACKETS = 0x00010115,
OID_GEN_VENDOR_DRIVER_VERSION = 0x00010116,
OID_GEN_SUPPORTED_GUIDS = 0x00010117,
OID_GEN_NETWORK_LAYER_ADDRESSES = 0x00010118,
OID_GEN_TRANSPORT_HEADER_OFFSET = 0x00010119,
OID_GEN_MACHINE_NAME = 0x0001021a,
OID_GEN_RNDIS_CONFIG_PARAMETER = 0x0001021b,
OID_GEN_VLAN_ID = 0x0001021c,
/* Optional OIDs */
OID_GEN_MEDIA_CAPABILITIES = 0x00010201,
OID_GEN_PHYSICAL_MEDIUM = 0x00010202,
OID_GEN_MEDIA_CAPABILITIES = 0x00010201,
OID_GEN_PHYSICAL_MEDIUM = 0x00010202,
/* Required statistics OIDs */
OID_GEN_XMIT_OK = 0x00020101,
OID_GEN_RCV_OK = 0x00020102,
OID_GEN_XMIT_ERROR = 0x00020103,
OID_GEN_RCV_ERROR = 0x00020104,
OID_GEN_RCV_NO_BUFFER = 0x00020105,
OID_GEN_XMIT_OK = 0x00020101,
OID_GEN_RCV_OK = 0x00020102,
OID_GEN_XMIT_ERROR = 0x00020103,
OID_GEN_RCV_ERROR = 0x00020104,
OID_GEN_RCV_NO_BUFFER = 0x00020105,
/* Optional statistics OIDs */
OID_GEN_DIRECTED_BYTES_XMIT = 0x00020201,
OID_GEN_DIRECTED_FRAMES_XMIT = 0x00020202,
OID_GEN_MULTICAST_BYTES_XMIT = 0x00020203,
OID_GEN_MULTICAST_FRAMES_XMIT = 0x00020204,
OID_GEN_BROADCAST_BYTES_XMIT = 0x00020205,
OID_GEN_BROADCAST_FRAMES_XMIT = 0x00020206,
OID_GEN_DIRECTED_BYTES_RCV = 0x00020207,
OID_GEN_DIRECTED_FRAMES_RCV = 0x00020208,
OID_GEN_MULTICAST_BYTES_RCV = 0x00020209,
OID_GEN_MULTICAST_FRAMES_RCV = 0x0002020a,
OID_GEN_BROADCAST_BYTES_RCV = 0x0002020b,
OID_GEN_BROADCAST_FRAMES_RCV = 0x0002020c,
OID_GEN_RCV_CRC_ERROR = 0x0002020d,
OID_GEN_TRANSMIT_QUEUE_LENGTH = 0x0002020e,
OID_GEN_GET_TIME_CAPS = 0x0002020f,
OID_GEN_GET_NETCARD_TIME = 0x00020210,
OID_GEN_NETCARD_LOAD = 0x00020211,
OID_GEN_DEVICE_PROFILE = 0x00020212,
OID_GEN_INIT_TIME_MS = 0x00020213,
OID_GEN_RESET_COUNTS = 0x00020214,
OID_GEN_MEDIA_SENSE_COUNTS = 0x00020215,
OID_GEN_FRIENDLY_NAME = 0x00020216,
OID_GEN_MINIPORT_INFO = 0x00020217,
OID_GEN_RESET_VERIFY_PARAMETERS = 0x00020218,
OID_GEN_DIRECTED_BYTES_XMIT = 0x00020201,
OID_GEN_DIRECTED_FRAMES_XMIT = 0x00020202,
OID_GEN_MULTICAST_BYTES_XMIT = 0x00020203,
OID_GEN_MULTICAST_FRAMES_XMIT = 0x00020204,
OID_GEN_BROADCAST_BYTES_XMIT = 0x00020205,
OID_GEN_BROADCAST_FRAMES_XMIT = 0x00020206,
OID_GEN_DIRECTED_BYTES_RCV = 0x00020207,
OID_GEN_DIRECTED_FRAMES_RCV = 0x00020208,
OID_GEN_MULTICAST_BYTES_RCV = 0x00020209,
OID_GEN_MULTICAST_FRAMES_RCV = 0x0002020a,
OID_GEN_BROADCAST_BYTES_RCV = 0x0002020b,
OID_GEN_BROADCAST_FRAMES_RCV = 0x0002020c,
OID_GEN_RCV_CRC_ERROR = 0x0002020d,
OID_GEN_TRANSMIT_QUEUE_LENGTH = 0x0002020e,
OID_GEN_GET_TIME_CAPS = 0x0002020f,
OID_GEN_GET_NETCARD_TIME = 0x00020210,
OID_GEN_NETCARD_LOAD = 0x00020211,
OID_GEN_DEVICE_PROFILE = 0x00020212,
OID_GEN_INIT_TIME_MS = 0x00020213,
OID_GEN_RESET_COUNTS = 0x00020214,
OID_GEN_MEDIA_SENSE_COUNTS = 0x00020215,
OID_GEN_FRIENDLY_NAME = 0x00020216,
OID_GEN_MINIPORT_INFO = 0x00020217,
OID_GEN_RESET_VERIFY_PARAMETERS = 0x00020218,
/* IEEE 802.3 (Ethernet) OIDs */
OID_802_3_PERMANENT_ADDRESS = 0x01010101,
OID_802_3_CURRENT_ADDRESS = 0x01010102,
OID_802_3_MULTICAST_LIST = 0x01010103,
OID_802_3_MAXIMUM_LIST_SIZE = 0x01010104,
OID_802_3_MAC_OPTIONS = 0x01010105,
OID_802_3_RCV_ERROR_ALIGNMENT = 0x01020101,
OID_802_3_XMIT_ONE_COLLISION = 0x01020102,
OID_802_3_XMIT_MORE_COLLISIONS = 0x01020103,
OID_802_3_XMIT_DEFERRED = 0x01020201,
OID_802_3_XMIT_MAX_COLLISIONS = 0x01020202,
OID_802_3_RCV_OVERRUN = 0x01020203,
OID_802_3_XMIT_UNDERRUN = 0x01020204,
OID_802_3_XMIT_HEARTBEAT_FAILURE = 0x01020205,
OID_802_3_XMIT_TIMES_CRS_LOST = 0x01020206,
OID_802_3_XMIT_LATE_COLLISIONS = 0x01020207,
OID_802_3_PERMANENT_ADDRESS = 0x01010101,
OID_802_3_CURRENT_ADDRESS = 0x01010102,
OID_802_3_MULTICAST_LIST = 0x01010103,
OID_802_3_MAXIMUM_LIST_SIZE = 0x01010104,
OID_802_3_MAC_OPTIONS = 0x01010105,
OID_802_3_RCV_ERROR_ALIGNMENT = 0x01020101,
OID_802_3_XMIT_ONE_COLLISION = 0x01020102,
OID_802_3_XMIT_MORE_COLLISIONS = 0x01020103,
OID_802_3_XMIT_DEFERRED = 0x01020201,
OID_802_3_XMIT_MAX_COLLISIONS = 0x01020202,
OID_802_3_RCV_OVERRUN = 0x01020203,
OID_802_3_XMIT_UNDERRUN = 0x01020204,
OID_802_3_XMIT_HEARTBEAT_FAILURE = 0x01020205,
OID_802_3_XMIT_TIMES_CRS_LOST = 0x01020206,
OID_802_3_XMIT_LATE_COLLISIONS = 0x01020207,
};
static const uint32_t oid_supported_list[] =
@@ -618,13 +618,13 @@ static const uint32_t oid_supported_list[] =
OID_802_3_XMIT_MORE_COLLISIONS,
};
#define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA (1 << 0)
#define NDIS_MAC_OPTION_RECEIVE_SERIALIZED (1 << 1)
#define NDIS_MAC_OPTION_TRANSFERS_NOT_PEND (1 << 2)
#define NDIS_MAC_OPTION_NO_LOOPBACK (1 << 3)
#define NDIS_MAC_OPTION_FULL_DUPLEX (1 << 4)
#define NDIS_MAC_OPTION_EOTX_INDICATION (1 << 5)
#define NDIS_MAC_OPTION_8021P_PRIORITY (1 << 6)
#define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA (1 << 0)
#define NDIS_MAC_OPTION_RECEIVE_SERIALIZED (1 << 1)
#define NDIS_MAC_OPTION_TRANSFERS_NOT_PEND (1 << 2)
#define NDIS_MAC_OPTION_NO_LOOPBACK (1 << 3)
#define NDIS_MAC_OPTION_FULL_DUPLEX (1 << 4)
#define NDIS_MAC_OPTION_EOTX_INDICATION (1 << 5)
#define NDIS_MAC_OPTION_8021P_PRIORITY (1 << 6)
struct rndis_response {
QTAILQ_ENTRY(rndis_response) entries;
@@ -1375,12 +1375,12 @@ static void usb_net_realize(USBDevice *dev, Error **errp)
s->rndis_state = RNDIS_UNINITIALIZED;
QTAILQ_INIT(&s->rndis_resp);
s->medium = 0; /* NDIS_MEDIUM_802_3 */
s->medium = 0; /* NDIS_MEDIUM_802_3 */
s->speed = 1000000; /* 100MBps, in 100Bps units */
s->media_state = 0; /* NDIS_MEDIA_STATE_CONNECTED */;
s->media_state = 0; /* NDIS_MEDIA_STATE_CONNECTED */;
s->filter = 0;
s->vendorid = 0x1234;
s->connection = 1; /* Connected */
s->connection = 1; /* Connected */
s->intr = usb_ep_get(dev, USB_TOKEN_IN, 1);
s->bulk_in = usb_ep_get(dev, USB_TOKEN_IN, 2);
hw/usb/dev-wacom.c
+2 -2
View File
@@ -36,8 +36,8 @@
#include "qom/object.h"
/* Interface requests */
#define WACOM_GET_REPORT 0x2101
#define WACOM_SET_REPORT 0x2109
#define WACOM_GET_REPORT 0x2101
#define WACOM_SET_REPORT 0x2109
struct USBWacomState {
USBDevice dev;
hw/usb/hcd-musb.c
+163 -163
View File
@@ -28,227 +28,227 @@
#include "hw/hw.h"
/* Common USB registers */
#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
#define MUSB_HDRC_POWER 0x01 /* 8-bit */
#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
#define MUSB_HDRC_POWER 0x01 /* 8-bit */
#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
#define MUSB_HDRC_INTRRX 0x04
#define MUSB_HDRC_INTRTXE 0x06
#define MUSB_HDRC_INTRRXE 0x08
#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
#define MUSB_HDRC_INTRRX 0x04
#define MUSB_HDRC_INTRTXE 0x06
#define MUSB_HDRC_INTRRXE 0x08
#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
/* Per-EP registers in indexed mode */
#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
/* EP FIFOs */
#define MUSB_HDRC_FIFO 0x20
#define MUSB_HDRC_FIFO 0x20
/* Additional Control Registers */
#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
/* These are indexed */
#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
/* Some more registers */
#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
/* Added in HDRC 1.9(?) & MHDRC 1.4 */
/* ULPI pass-through */
#define MUSB_HDRC_ULPI_VBUSCTL 0x70
#define MUSB_HDRC_ULPI_REGDATA 0x74
#define MUSB_HDRC_ULPI_REGADDR 0x75
#define MUSB_HDRC_ULPI_REGCTL 0x76
#define MUSB_HDRC_ULPI_VBUSCTL 0x70
#define MUSB_HDRC_ULPI_REGDATA 0x74
#define MUSB_HDRC_ULPI_REGADDR 0x75
#define MUSB_HDRC_ULPI_REGCTL 0x76
/* Extended config & PHY control */
#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
/* Per-EP BUSCTL registers */
#define MUSB_HDRC_BUSCTL 0x80
#define MUSB_HDRC_BUSCTL 0x80
/* Per-EP registers in flat mode */
#define MUSB_HDRC_EP 0x100
#define MUSB_HDRC_EP 0x100
/* offsets to registers in flat model */
#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
/* "Bus control" registers */
#define MUSB_HDRC_TXFUNCADDR 0x00
#define MUSB_HDRC_TXHUBADDR 0x02
#define MUSB_HDRC_TXHUBPORT 0x03
#define MUSB_HDRC_TXFUNCADDR 0x00
#define MUSB_HDRC_TXHUBADDR 0x02
#define MUSB_HDRC_TXHUBPORT 0x03
#define MUSB_HDRC_RXFUNCADDR 0x04
#define MUSB_HDRC_RXHUBADDR 0x06
#define MUSB_HDRC_RXHUBPORT 0x07
#define MUSB_HDRC_RXFUNCADDR 0x04
#define MUSB_HDRC_RXHUBADDR 0x06
#define MUSB_HDRC_RXHUBPORT 0x07
/*
* MUSBHDRC Register bit masks
*/
/* POWER */
#define MGC_M_POWER_ISOUPDATE 0x80
#define MGC_M_POWER_SOFTCONN 0x40
#define MGC_M_POWER_HSENAB 0x20
#define MGC_M_POWER_HSMODE 0x10
#define MGC_M_POWER_RESET 0x08
#define MGC_M_POWER_RESUME 0x04
#define MGC_M_POWER_SUSPENDM 0x02
#define MGC_M_POWER_ENSUSPEND 0x01
#define MGC_M_POWER_ISOUPDATE 0x80
#define MGC_M_POWER_SOFTCONN 0x40
#define MGC_M_POWER_HSENAB 0x20
#define MGC_M_POWER_HSMODE 0x10
#define MGC_M_POWER_RESET 0x08
#define MGC_M_POWER_RESUME 0x04
#define MGC_M_POWER_SUSPENDM 0x02
#define MGC_M_POWER_ENSUSPEND 0x01
/* INTRUSB */
#define MGC_M_INTR_SUSPEND 0x01
#define MGC_M_INTR_RESUME 0x02
#define MGC_M_INTR_RESET 0x04
#define MGC_M_INTR_BABBLE 0x04
#define MGC_M_INTR_SOF 0x08
#define MGC_M_INTR_CONNECT 0x10
#define MGC_M_INTR_DISCONNECT 0x20
#define MGC_M_INTR_SESSREQ 0x40
#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
#define MGC_M_INTR_SUSPEND 0x01
#define MGC_M_INTR_RESUME 0x02
#define MGC_M_INTR_RESET 0x04
#define MGC_M_INTR_BABBLE 0x04
#define MGC_M_INTR_SOF 0x08
#define MGC_M_INTR_CONNECT 0x10
#define MGC_M_INTR_DISCONNECT 0x20
#define MGC_M_INTR_SESSREQ 0x40
#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
/* DEVCTL */
#define MGC_M_DEVCTL_BDEVICE 0x80
#define MGC_M_DEVCTL_FSDEV 0x40
#define MGC_M_DEVCTL_LSDEV 0x20
#define MGC_M_DEVCTL_VBUS 0x18
#define MGC_S_DEVCTL_VBUS 3
#define MGC_M_DEVCTL_HM 0x04
#define MGC_M_DEVCTL_HR 0x02
#define MGC_M_DEVCTL_SESSION 0x01
#define MGC_M_DEVCTL_BDEVICE 0x80
#define MGC_M_DEVCTL_FSDEV 0x40
#define MGC_M_DEVCTL_LSDEV 0x20
#define MGC_M_DEVCTL_VBUS 0x18
#define MGC_S_DEVCTL_VBUS 3
#define MGC_M_DEVCTL_HM 0x04
#define MGC_M_DEVCTL_HR 0x02
#define MGC_M_DEVCTL_SESSION 0x01
/* TESTMODE */
#define MGC_M_TEST_FORCE_HOST 0x80
#define MGC_M_TEST_FIFO_ACCESS 0x40
#define MGC_M_TEST_FORCE_FS 0x20
#define MGC_M_TEST_FORCE_HS 0x10
#define MGC_M_TEST_PACKET 0x08
#define MGC_M_TEST_K 0x04
#define MGC_M_TEST_J 0x02
#define MGC_M_TEST_SE0_NAK 0x01
#define MGC_M_TEST_FORCE_HOST 0x80
#define MGC_M_TEST_FIFO_ACCESS 0x40
#define MGC_M_TEST_FORCE_FS 0x20
#define MGC_M_TEST_FORCE_HS 0x10
#define MGC_M_TEST_PACKET 0x08
#define MGC_M_TEST_K 0x04
#define MGC_M_TEST_J 0x02
#define MGC_M_TEST_SE0_NAK 0x01
/* CSR0 */
#define MGC_M_CSR0_FLUSHFIFO 0x0100
#define MGC_M_CSR0_TXPKTRDY 0x0002
#define MGC_M_CSR0_RXPKTRDY 0x0001
#define MGC_M_CSR0_FLUSHFIFO 0x0100
#define MGC_M_CSR0_TXPKTRDY 0x0002
#define MGC_M_CSR0_RXPKTRDY 0x0001
/* CSR0 in Peripheral mode */
#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
#define MGC_M_CSR0_P_SENDSTALL 0x0020
#define MGC_M_CSR0_P_SETUPEND 0x0010
#define MGC_M_CSR0_P_DATAEND 0x0008
#define MGC_M_CSR0_P_SENTSTALL 0x0004
#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
#define MGC_M_CSR0_P_SENDSTALL 0x0020
#define MGC_M_CSR0_P_SETUPEND 0x0010
#define MGC_M_CSR0_P_DATAEND 0x0008
#define MGC_M_CSR0_P_SENTSTALL 0x0004
/* CSR0 in Host mode */
#define MGC_M_CSR0_H_NO_PING 0x0800
#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
#define MGC_M_CSR0_H_STATUSPKT 0x0040
#define MGC_M_CSR0_H_REQPKT 0x0020
#define MGC_M_CSR0_H_ERROR 0x0010
#define MGC_M_CSR0_H_SETUPPKT 0x0008
#define MGC_M_CSR0_H_RXSTALL 0x0004
#define MGC_M_CSR0_H_NO_PING 0x0800
#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
#define MGC_M_CSR0_H_STATUSPKT 0x0040
#define MGC_M_CSR0_H_REQPKT 0x0020
#define MGC_M_CSR0_H_ERROR 0x0010
#define MGC_M_CSR0_H_SETUPPKT 0x0008
#define MGC_M_CSR0_H_RXSTALL 0x0004
/* CONFIGDATA */
#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
/* TXCSR in Peripheral and Host mode */
#define MGC_M_TXCSR_AUTOSET 0x8000
#define MGC_M_TXCSR_ISO 0x4000
#define MGC_M_TXCSR_MODE 0x2000
#define MGC_M_TXCSR_DMAENAB 0x1000
#define MGC_M_TXCSR_FRCDATATOG 0x0800
#define MGC_M_TXCSR_DMAMODE 0x0400
#define MGC_M_TXCSR_CLRDATATOG 0x0040
#define MGC_M_TXCSR_FLUSHFIFO 0x0008
#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
#define MGC_M_TXCSR_TXPKTRDY 0x0001
#define MGC_M_TXCSR_AUTOSET 0x8000
#define MGC_M_TXCSR_ISO 0x4000
#define MGC_M_TXCSR_MODE 0x2000
#define MGC_M_TXCSR_DMAENAB 0x1000
#define MGC_M_TXCSR_FRCDATATOG 0x0800
#define MGC_M_TXCSR_DMAMODE 0x0400
#define MGC_M_TXCSR_CLRDATATOG 0x0040
#define MGC_M_TXCSR_FLUSHFIFO 0x0008
#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
#define MGC_M_TXCSR_TXPKTRDY 0x0001
/* TXCSR in Peripheral mode */
#define MGC_M_TXCSR_P_INCOMPTX 0x0080
#define MGC_M_TXCSR_P_SENTSTALL 0x0020
#define MGC_M_TXCSR_P_SENDSTALL 0x0010
#define MGC_M_TXCSR_P_UNDERRUN 0x0004
#define MGC_M_TXCSR_P_INCOMPTX 0x0080
#define MGC_M_TXCSR_P_SENTSTALL 0x0020
#define MGC_M_TXCSR_P_SENDSTALL 0x0010
#define MGC_M_TXCSR_P_UNDERRUN 0x0004
/* TXCSR in Host mode */
#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
#define MGC_M_TXCSR_H_RXSTALL 0x0020
#define MGC_M_TXCSR_H_ERROR 0x0004
#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
#define MGC_M_TXCSR_H_RXSTALL 0x0020
#define MGC_M_TXCSR_H_ERROR 0x0004
/* RXCSR in Peripheral and Host mode */
#define MGC_M_RXCSR_AUTOCLEAR 0x8000
#define MGC_M_RXCSR_DMAENAB 0x2000
#define MGC_M_RXCSR_DISNYET 0x1000
#define MGC_M_RXCSR_DMAMODE 0x0800
#define MGC_M_RXCSR_INCOMPRX 0x0100
#define MGC_M_RXCSR_CLRDATATOG 0x0080
#define MGC_M_RXCSR_FLUSHFIFO 0x0010
#define MGC_M_RXCSR_DATAERROR 0x0008
#define MGC_M_RXCSR_FIFOFULL 0x0002
#define MGC_M_RXCSR_RXPKTRDY 0x0001
#define MGC_M_RXCSR_AUTOCLEAR 0x8000
#define MGC_M_RXCSR_DMAENAB 0x2000
#define MGC_M_RXCSR_DISNYET 0x1000
#define MGC_M_RXCSR_DMAMODE 0x0800
#define MGC_M_RXCSR_INCOMPRX 0x0100
#define MGC_M_RXCSR_CLRDATATOG 0x0080
#define MGC_M_RXCSR_FLUSHFIFO 0x0010
#define MGC_M_RXCSR_DATAERROR 0x0008
#define MGC_M_RXCSR_FIFOFULL 0x0002
#define MGC_M_RXCSR_RXPKTRDY 0x0001
/* RXCSR in Peripheral mode */
#define MGC_M_RXCSR_P_ISO 0x4000
#define MGC_M_RXCSR_P_SENTSTALL 0x0040
#define MGC_M_RXCSR_P_SENDSTALL 0x0020
#define MGC_M_RXCSR_P_OVERRUN 0x0004
#define MGC_M_RXCSR_P_ISO 0x4000
#define MGC_M_RXCSR_P_SENTSTALL 0x0040
#define MGC_M_RXCSR_P_SENDSTALL 0x0020
#define MGC_M_RXCSR_P_OVERRUN 0x0004
/* RXCSR in Host mode */
#define MGC_M_RXCSR_H_AUTOREQ 0x4000
#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
#define MGC_M_RXCSR_H_RXSTALL 0x0040
#define MGC_M_RXCSR_H_REQPKT 0x0020
#define MGC_M_RXCSR_H_ERROR 0x0004
#define MGC_M_RXCSR_H_AUTOREQ 0x4000
#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
#define MGC_M_RXCSR_H_RXSTALL 0x0040
#define MGC_M_RXCSR_H_REQPKT 0x0020
#define MGC_M_RXCSR_H_ERROR 0x0004
/* HUBADDR */
#define MGC_M_HUBADDR_MULTI_TT 0x80
#define MGC_M_HUBADDR_MULTI_TT 0x80
/* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
#define MGC_M_ULPI_REGCTL_REG 0x01
#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
#define MGC_M_ULPI_REGCTL_REG 0x01
/* #define MUSB_DEBUG */
@@ -296,7 +296,7 @@ struct MUSBEndPoint {
uint8_t interval[2];
uint8_t config;
uint8_t fifosize;
int timeout[2]; /* Always in microframes */
int timeout[2]; /* Always in microframes */
uint8_t *buf[2];
int fifolen[2];
@@ -542,7 +542,7 @@ static void musb_cb_tick1(void *opaque)
ep->delayed_cb[1](&ep->packey[1].p, opaque);
}
#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
static void musb_schedule_cb(USBPort *port, USBPacket *packey)
{
@@ -1323,7 +1323,7 @@ static void musb_writeb(void *opaque, hwaddr addr, uint32_t value)
/* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
if ((value & MGC_M_POWER_HSENAB) &&
s->port.dev->speed == USB_SPEED_HIGH)
s->power |= MGC_M_POWER_HSMODE; /* Success */
s->power |= MGC_M_POWER_HSMODE; /* Success */
/* Restart frame counting. */
}
if (value & MGC_M_POWER_SUSPENDM) {
hw/usb/quirks-pl2303-ids.h
+90 -90
View File
@@ -1,150 +1,150 @@
/*
* Prolific PL2303 USB to serial adaptor driver header file
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#define BENQ_VENDOR_ID 0x04a5
#define BENQ_PRODUCT_ID_S81 0x4027
#define BENQ_VENDOR_ID 0x04a5
#define BENQ_PRODUCT_ID_S81 0x4027
#define PL2303_VENDOR_ID 0x067b
#define PL2303_PRODUCT_ID 0x2303
#define PL2303_PRODUCT_ID_RSAQ2 0x04bb
#define PL2303_PRODUCT_ID_DCU11 0x1234
#define PL2303_PRODUCT_ID_PHAROS 0xaaa0
#define PL2303_PRODUCT_ID_RSAQ3 0xaaa2
#define PL2303_PRODUCT_ID_ALDIGA 0x0611
#define PL2303_PRODUCT_ID_MMX 0x0612
#define PL2303_PRODUCT_ID_GPRS 0x0609
#define PL2303_PRODUCT_ID_HCR331 0x331a
#define PL2303_PRODUCT_ID_MOTOROLA 0x0307
#define PL2303_VENDOR_ID 0x067b
#define PL2303_PRODUCT_ID 0x2303
#define PL2303_PRODUCT_ID_RSAQ2 0x04bb
#define PL2303_PRODUCT_ID_DCU11 0x1234
#define PL2303_PRODUCT_ID_PHAROS 0xaaa0
#define PL2303_PRODUCT_ID_RSAQ3 0xaaa2
#define PL2303_PRODUCT_ID_ALDIGA 0x0611
#define PL2303_PRODUCT_ID_MMX 0x0612
#define PL2303_PRODUCT_ID_GPRS 0x0609
#define PL2303_PRODUCT_ID_HCR331 0x331a
#define PL2303_PRODUCT_ID_MOTOROLA 0x0307
#define ATEN_VENDOR_ID 0x0557
#define ATEN_VENDOR_ID2 0x0547
#define ATEN_PRODUCT_ID 0x2008
#define ATEN_VENDOR_ID 0x0557
#define ATEN_VENDOR_ID2 0x0547
#define ATEN_PRODUCT_ID 0x2008
#define IODATA_VENDOR_ID 0x04bb
#define IODATA_PRODUCT_ID 0x0a03
#define IODATA_PRODUCT_ID_RSAQ5 0x0a0e
#define IODATA_VENDOR_ID 0x04bb
#define IODATA_PRODUCT_ID 0x0a03
#define IODATA_PRODUCT_ID_RSAQ5 0x0a0e
#define ELCOM_VENDOR_ID 0x056e
#define ELCOM_PRODUCT_ID 0x5003
#define ELCOM_PRODUCT_ID_UCSGT 0x5004
#define ELCOM_VENDOR_ID 0x056e
#define ELCOM_PRODUCT_ID 0x5003
#define ELCOM_PRODUCT_ID_UCSGT 0x5004
#define ITEGNO_VENDOR_ID 0x0eba
#define ITEGNO_PRODUCT_ID 0x1080
#define ITEGNO_PRODUCT_ID_2080 0x2080
#define ITEGNO_VENDOR_ID 0x0eba
#define ITEGNO_PRODUCT_ID 0x1080
#define ITEGNO_PRODUCT_ID_2080 0x2080
#define MA620_VENDOR_ID 0x0df7
#define MA620_PRODUCT_ID 0x0620
#define MA620_VENDOR_ID 0x0df7
#define MA620_PRODUCT_ID 0x0620
#define RATOC_VENDOR_ID 0x0584
#define RATOC_PRODUCT_ID 0xb000
#define RATOC_VENDOR_ID 0x0584
#define RATOC_PRODUCT_ID 0xb000
#define TRIPP_VENDOR_ID 0x2478
#define TRIPP_PRODUCT_ID 0x2008
#define TRIPP_VENDOR_ID 0x2478
#define TRIPP_PRODUCT_ID 0x2008
#define RADIOSHACK_VENDOR_ID 0x1453
#define RADIOSHACK_PRODUCT_ID 0x4026
#define RADIOSHACK_VENDOR_ID 0x1453
#define RADIOSHACK_PRODUCT_ID 0x4026
#define DCU10_VENDOR_ID 0x0731
#define DCU10_PRODUCT_ID 0x0528
#define DCU10_VENDOR_ID 0x0731
#define DCU10_PRODUCT_ID 0x0528
#define SITECOM_VENDOR_ID 0x6189
#define SITECOM_PRODUCT_ID 0x2068
#define SITECOM_VENDOR_ID 0x6189
#define SITECOM_PRODUCT_ID 0x2068
/* Alcatel OT535/735 USB cable */
#define ALCATEL_VENDOR_ID 0x11f7
#define ALCATEL_PRODUCT_ID 0x02df
#define ALCATEL_VENDOR_ID 0x11f7
#define ALCATEL_PRODUCT_ID 0x02df
/* Samsung I330 phone cradle */
#define SAMSUNG_VENDOR_ID 0x04e8
#define SAMSUNG_PRODUCT_ID 0x8001
#define SAMSUNG_VENDOR_ID 0x04e8
#define SAMSUNG_PRODUCT_ID 0x8001
#define SIEMENS_VENDOR_ID 0x11f5
#define SIEMENS_PRODUCT_ID_SX1 0x0001
#define SIEMENS_PRODUCT_ID_X65 0x0003
#define SIEMENS_PRODUCT_ID_X75 0x0004
#define SIEMENS_PRODUCT_ID_EF81 0x0005
#define SIEMENS_VENDOR_ID 0x11f5
#define SIEMENS_PRODUCT_ID_SX1 0x0001
#define SIEMENS_PRODUCT_ID_X65 0x0003
#define SIEMENS_PRODUCT_ID_X75 0x0004
#define SIEMENS_PRODUCT_ID_EF81 0x0005
#define SYNTECH_VENDOR_ID 0x0745
#define SYNTECH_PRODUCT_ID 0x0001
#define SYNTECH_VENDOR_ID 0x0745
#define SYNTECH_PRODUCT_ID 0x0001
/* Nokia CA-42 Cable */
#define NOKIA_CA42_VENDOR_ID 0x078b
#define NOKIA_CA42_PRODUCT_ID 0x1234
#define NOKIA_CA42_VENDOR_ID 0x078b
#define NOKIA_CA42_PRODUCT_ID 0x1234
/* CA-42 CLONE Cable www.ca-42.com chipset: Prolific Technology Inc */
#define CA_42_CA42_VENDOR_ID 0x10b5
#define CA_42_CA42_PRODUCT_ID 0xac70
#define CA_42_CA42_VENDOR_ID 0x10b5
#define CA_42_CA42_PRODUCT_ID 0xac70
#define SAGEM_VENDOR_ID 0x079b
#define SAGEM_PRODUCT_ID 0x0027
#define SAGEM_VENDOR_ID 0x079b
#define SAGEM_PRODUCT_ID 0x0027
/* Leadtek GPS 9531 (ID 0413:2101) */
#define LEADTEK_VENDOR_ID 0x0413
#define LEADTEK_9531_PRODUCT_ID 0x2101
#define LEADTEK_VENDOR_ID 0x0413
#define LEADTEK_9531_PRODUCT_ID 0x2101
/* USB GSM cable from Speed Dragon Multimedia, Ltd */
#define SPEEDDRAGON_VENDOR_ID 0x0e55
#define SPEEDDRAGON_PRODUCT_ID 0x110b
#define SPEEDDRAGON_VENDOR_ID 0x0e55
#define SPEEDDRAGON_PRODUCT_ID 0x110b
/* DATAPILOT Universal-2 Phone Cable */
#define DATAPILOT_U2_VENDOR_ID 0x0731
#define DATAPILOT_U2_PRODUCT_ID 0x2003
#define DATAPILOT_U2_VENDOR_ID 0x0731
#define DATAPILOT_U2_PRODUCT_ID 0x2003
/* Belkin "F5U257" Serial Adapter */
#define BELKIN_VENDOR_ID 0x050d
#define BELKIN_PRODUCT_ID 0x0257
#define BELKIN_VENDOR_ID 0x050d
#define BELKIN_PRODUCT_ID 0x0257
/* Alcor Micro Corp. USB 2.0 TO RS-232 */
#define ALCOR_VENDOR_ID 0x058F
#define ALCOR_PRODUCT_ID 0x9720
#define ALCOR_VENDOR_ID 0x058F
#define ALCOR_PRODUCT_ID 0x9720
/* Willcom WS002IN Data Driver (by NetIndex Inc.) */
#define WS002IN_VENDOR_ID 0x11f6
#define WS002IN_PRODUCT_ID 0x2001
#define WS002IN_VENDOR_ID 0x11f6
#define WS002IN_PRODUCT_ID 0x2001
/* Corega CG-USBRS232R Serial Adapter */
#define COREGA_VENDOR_ID 0x07aa
#define COREGA_PRODUCT_ID 0x002a
#define COREGA_VENDOR_ID 0x07aa
#define COREGA_PRODUCT_ID 0x002a
/* Y.C. Cable U.S.A., Inc - USB to RS-232 */
#define YCCABLE_VENDOR_ID 0x05ad
#define YCCABLE_PRODUCT_ID 0x0fba
#define YCCABLE_VENDOR_ID 0x05ad
#define YCCABLE_PRODUCT_ID 0x0fba
/* "Superial" USB - Serial */
#define SUPERIAL_VENDOR_ID 0x5372
#define SUPERIAL_PRODUCT_ID 0x2303
#define SUPERIAL_VENDOR_ID 0x5372
#define SUPERIAL_PRODUCT_ID 0x2303
/* Hewlett-Packard LD220-HP POS Pole Display */
#define HP_VENDOR_ID 0x03f0
#define HP_LD220_PRODUCT_ID 0x3524
#define HP_VENDOR_ID 0x03f0
#define HP_LD220_PRODUCT_ID 0x3524
/* Cressi Edy (diving computer) PC interface */
#define CRESSI_VENDOR_ID 0x04b8
#define CRESSI_EDY_PRODUCT_ID 0x0521
#define CRESSI_VENDOR_ID 0x04b8
#define CRESSI_EDY_PRODUCT_ID 0x0521
/* Zeagle dive computer interface */
#define ZEAGLE_VENDOR_ID 0x04b8
#define ZEAGLE_N2ITION3_PRODUCT_ID 0x0522
#define ZEAGLE_VENDOR_ID 0x04b8
#define ZEAGLE_N2ITION3_PRODUCT_ID 0x0522
/* Sony, USB data cable for CMD-Jxx mobile phones */
#define SONY_VENDOR_ID 0x054c
#define SONY_QN3USB_PRODUCT_ID 0x0437
#define SONY_VENDOR_ID 0x054c
#define SONY_QN3USB_PRODUCT_ID 0x0437
/* Sanwa KB-USB2 multimeter cable (ID: 11ad:0001) */
#define SANWA_VENDOR_ID 0x11ad
#define SANWA_PRODUCT_ID 0x0001
#define SANWA_VENDOR_ID 0x11ad
#define SANWA_PRODUCT_ID 0x0001
/* ADLINK ND-6530 RS232,RS485 and RS422 adapter */
#define ADLINK_VENDOR_ID 0x0b63
#define ADLINK_ND6530_PRODUCT_ID 0x6530
#define ADLINK_VENDOR_ID 0x0b63
#define ADLINK_ND6530_PRODUCT_ID 0x6530
/* SMART USB Serial Adapter */
#define SMART_VENDOR_ID 0x0b8c
#define SMART_PRODUCT_ID 0x2303
#define SMART_VENDOR_ID 0x0b8c
#define SMART_PRODUCT_ID 0x2303
include/hw/s390x/s390-virtio-ccw.h
-1
View File
@@ -27,7 +27,6 @@ struct S390CcwMachineState {
bool aes_key_wrap;
bool dea_key_wrap;
bool pv;
bool zpcii_disable;
uint8_t loadparm[8];
};
include/hw/usb.h
+50 -50
View File
@@ -66,42 +66,42 @@
//#define USB_STATE_POWERED 2
#define USB_STATE_DEFAULT 3
//#define USB_STATE_ADDRESS 4
//#define USB_STATE_CONFIGURED 5
//#define USB_STATE_CONFIGURED 5
#define USB_STATE_SUSPENDED 6
#define USB_CLASS_AUDIO 1
#define USB_CLASS_COMM 2
#define USB_CLASS_HID 3
#define USB_CLASS_PHYSICAL 5
#define USB_CLASS_STILL_IMAGE 6
#define USB_CLASS_PRINTER 7
#define USB_CLASS_MASS_STORAGE 8
#define USB_CLASS_HUB 9
#define USB_CLASS_CDC_DATA 0x0a
#define USB_CLASS_CSCID 0x0b
#define USB_CLASS_CONTENT_SEC 0x0d
#define USB_CLASS_APP_SPEC 0xfe
#define USB_CLASS_VENDOR_SPEC 0xff
#define USB_CLASS_AUDIO 1
#define USB_CLASS_COMM 2
#define USB_CLASS_HID 3
#define USB_CLASS_PHYSICAL 5
#define USB_CLASS_STILL_IMAGE 6
#define USB_CLASS_PRINTER 7
#define USB_CLASS_MASS_STORAGE 8
#define USB_CLASS_HUB 9
#define USB_CLASS_CDC_DATA 0x0a
#define USB_CLASS_CSCID 0x0b
#define USB_CLASS_CONTENT_SEC 0x0d
#define USB_CLASS_APP_SPEC 0xfe
#define USB_CLASS_VENDOR_SPEC 0xff
#define USB_SUBCLASS_UNDEFINED 0
#define USB_SUBCLASS_AUDIO_CONTROL 1
#define USB_SUBCLASS_AUDIO_STREAMING 2
#define USB_SUBCLASS_AUDIO_MIDISTREAMING 3
#define USB_DIR_OUT 0
#define USB_DIR_IN 0x80
#define USB_DIR_OUT 0
#define USB_DIR_IN 0x80
#define USB_TYPE_MASK (0x03 << 5)
#define USB_TYPE_STANDARD (0x00 << 5)
#define USB_TYPE_CLASS (0x01 << 5)
#define USB_TYPE_VENDOR (0x02 << 5)
#define USB_TYPE_RESERVED (0x03 << 5)
#define USB_TYPE_MASK (0x03 << 5)
#define USB_TYPE_STANDARD (0x00 << 5)
#define USB_TYPE_CLASS (0x01 << 5)
#define USB_TYPE_VENDOR (0x02 << 5)
#define USB_TYPE_RESERVED (0x03 << 5)
#define USB_RECIP_MASK 0x1f
#define USB_RECIP_DEVICE 0x00
#define USB_RECIP_INTERFACE 0x01
#define USB_RECIP_ENDPOINT 0x02
#define USB_RECIP_OTHER 0x03
#define USB_RECIP_MASK 0x1f
#define USB_RECIP_DEVICE 0x00
#define USB_RECIP_INTERFACE 0x01
#define USB_RECIP_ENDPOINT 0x02
#define USB_RECIP_OTHER 0x03
#define DeviceRequest ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
#define DeviceOutRequest ((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
@@ -126,28 +126,28 @@
#define EndpointOutRequest \
((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_ENDPOINT)<<8)
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
#define USB_REQ_SET_SEL 0x30
#define USB_REQ_SET_ISOCH_DELAY 0x31
#define USB_DEVICE_SELF_POWERED 0
#define USB_DEVICE_REMOTE_WAKEUP 1
#define USB_DEVICE_SELF_POWERED 0
#define USB_DEVICE_REMOTE_WAKEUP 1
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
#define USB_DT_DEVICE_QUALIFIER 0x06
#define USB_DT_OTHER_SPEED_CONFIG 0x07
#define USB_DT_DEBUG 0x0A
@@ -167,10 +167,10 @@
#define USB_CFG_ATT_WAKEUP (1 << 5)
#define USB_CFG_ATT_BATTERY (1 << 4)
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_XFER_INVALID 255
#define USB_INTERFACE_INVALID 255
@@ -569,9 +569,9 @@ static inline bool usb_device_is_scsi_storage(USBDevice *dev)
/* quirks.c */
/* In bulk endpoints are streaming data sources (iow behave like isoc eps) */
#define USB_QUIRK_BUFFER_BULK_IN 0x01
#define USB_QUIRK_BUFFER_BULK_IN 0x01
/* Bulk pkts in FTDI format, need special handling when combining packets */
#define USB_QUIRK_IS_FTDI 0x02
#define USB_QUIRK_IS_FTDI 0x02
int usb_get_quirks(uint16_t vendor_id, uint16_t product_id,
uint8_t interface_class, uint8_t interface_subclass,
include/hw/usb/dwc2-regs.h
+753 -753
View File
File diff suppressed because it is too large Load Diff
qemu-options.hx
+1 -7
View File
@@ -37,8 +37,7 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \
" memory-encryption=@var{} memory encryption object to use (default=none)\n"
" hmat=on|off controls ACPI HMAT support (default=off)\n"
" memory-backend='backend-id' specifies explicitly provided backend for main RAM (default=none)\n"
" cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n"
" zpcii-disable=on|off disables zPCI interpretation facilities (default=off)\n",
" cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n",
QEMU_ARCH_ALL)
SRST
``-machine [type=]name[,prop=value[,...]]``
@@ -158,11 +157,6 @@ SRST
::
-machine cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interleave-granularity=512k
``zpcii-disable=on|off``
Disables zPCI interpretation facilties on s390-ccw hosts.
This feature can be used to disable hardware virtual assists
related to zPCI devices. The default is off.
ERST
DEF("M", HAS_ARG, QEMU_OPTION_M,
ui/vgafont.h
+4607 -4607
View File
File diff suppressed because it is too large Load Diff
ui/vnc-enc-zywrle-template.c
+10 -10
View File
@@ -86,17 +86,17 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#undef L_2
#if ZYWRLE_ENDIAN == ENDIAN_BIG
# define S_0 1
# define S_1 0
# define L_0 3
# define L_1 2
# define L_2 1
# define S_0 1
# define S_1 0
# define L_0 3
# define L_1 2
# define L_2 1
#else
# define S_0 0
# define S_1 1
# define L_0 0
# define L_1 1
# define L_2 2
# define S_0 0
# define S_1 1
# define L_0 0
# define L_1 1
# define L_2 2
#endif
#define ZYWRLE_QUANTIZE
ui/vnc-enc-zywrle.h
+8 -8
View File
@@ -51,14 +51,14 @@ static const unsigned int zywrle_param[3][3]={
{0x0000F000, 0x00000000, 0x00000000},
{0x0000C000, 0x00F0F0F0, 0x00000000},
{0x0000C000, 0x00C0C0C0, 0x00F0F0F0},
/* {0x0000FF00, 0x00000000, 0x00000000},
/* {0x0000FF00, 0x00000000, 0x00000000},
{0x0000FF00, 0x00FFFFFF, 0x00000000},
{0x0000FF00, 0x00FFFFFF, 0x00FFFFFF}, */
};
#else
/* Type B:Non liner quantization filter. */
static const int8_t zywrle_conv[4][256]={
{ /* bi=5, bo=5 r=0.0:PSNR=24.849 */
{ /* bi=5, bo=5 r=0.0:PSNR=24.849 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -92,7 +92,7 @@ static const int8_t zywrle_conv[4][256]={
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
},
{ /* bi=5, bo=5 r=2.0:PSNR=74.031 */
{ /* bi=5, bo=5 r=2.0:PSNR=74.031 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 32,
@@ -126,7 +126,7 @@ static const int8_t zywrle_conv[4][256]={
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
},
{ /* bi=5, bo=4 r=2.0:PSNR=64.441 */
{ /* bi=5, bo=4 r=2.0:PSNR=64.441 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -160,7 +160,7 @@ static const int8_t zywrle_conv[4][256]={
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
},
{ /* bi=5, bo=2 r=2.0:PSNR=43.175 */
{ /* bi=5, bo=2 r=2.0:PSNR=43.175 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -274,14 +274,14 @@ static inline void harr(int8_t *px0, int8_t *px1)
x1 += x0;
if (((x1 ^ orgx1) & 0x80) == 0) {
/* |x1| > |x0| */
x0 -= x1; /* H = -B */
x0 -= x1; /* H = -B */
}
} else {
/* same sign */
x0 -= x1;
if (((x0 ^ orgx0) & 0x80) == 0) {
/* |x0| > |x1| */
x1 += x0; /* L = A */
x1 += x0; /* L = A */
}
}
*px0 = (int8_t)x1;
@@ -585,7 +585,7 @@ static inline void wavelet(int *buf, int width, int height, int level)
} \
} while (0)
#define ZYWRLE_PACK_COEFF(buf, data, t, width, height, scanline, level) \
#define ZYWRLE_PACK_COEFF(buf, data, t, width, height, scanline, level) \
ZYWRLE_TRANSFER_COEFF(buf, data, t, width, height, scanline, level, \
ZYWRLE_LOAD_COEFF(ph, r, g, b); \
ZYWRLE_SAVE_PIXEL(data, r, g, b);)

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