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tcg: Rename cpu_env to tcg_env

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Allow the name 'cpu_env' to be used for something else.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2023-10-03 08:01:02 -07:00
parent a953b5fa15
commit ad75a51e84
91 changed files with 3818 additions and 3819 deletions
Download Patch File Download Diff File Expand all files Collapse all files
accel/tcg/plugin-gen.c
+4 -4
View File
@@ -104,7 +104,7 @@ static void gen_empty_udata_cb(void)
TCGv_ptr udata = tcg_temp_ebb_new_ptr();
tcg_gen_movi_ptr(udata, 0);
tcg_gen_ld_i32(cpu_index, cpu_env,
tcg_gen_ld_i32(cpu_index, tcg_env,
-offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
gen_helper_plugin_vcpu_udata_cb(cpu_index, udata);
@@ -138,7 +138,7 @@ static void gen_empty_mem_cb(TCGv_i64 addr, uint32_t info)
tcg_gen_movi_i32(meminfo, info);
tcg_gen_movi_ptr(udata, 0);
tcg_gen_ld_i32(cpu_index, cpu_env,
tcg_gen_ld_i32(cpu_index, tcg_env,
-offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr, udata);
@@ -157,7 +157,7 @@ static void gen_empty_mem_helper(void)
TCGv_ptr ptr = tcg_temp_ebb_new_ptr();
tcg_gen_movi_ptr(ptr, 0);
tcg_gen_st_ptr(ptr, cpu_env, offsetof(CPUState, plugin_mem_cbs) -
tcg_gen_st_ptr(ptr, tcg_env, offsetof(CPUState, plugin_mem_cbs) -
offsetof(ArchCPU, env));
tcg_temp_free_ptr(ptr);
}
@@ -581,7 +581,7 @@ void plugin_gen_disable_mem_helpers(void)
if (!tcg_ctx->plugin_tb->mem_helper) {
return;
}
tcg_gen_st_ptr(tcg_constant_ptr(NULL), cpu_env,
tcg_gen_st_ptr(tcg_constant_ptr(NULL), tcg_env,
offsetof(CPUState, plugin_mem_cbs) - offsetof(ArchCPU, env));
}
accel/tcg/translator.c
+3 -3
View File
@@ -22,7 +22,7 @@ static void set_can_do_io(DisasContextBase *db, bool val)
db->saved_can_do_io = val;
QEMU_BUILD_BUG_ON(sizeof_field(CPUState, neg.can_do_io) != 1);
tcg_gen_st8_i32(tcg_constant_i32(val), cpu_env,
tcg_gen_st8_i32(tcg_constant_i32(val), tcg_env,
offsetof(ArchCPU, parent_obj.neg.can_do_io) -
offsetof(ArchCPU, env));
}
@@ -49,7 +49,7 @@ static TCGOp *gen_tb_start(DisasContextBase *db, uint32_t cflags)
if ((cflags & CF_USE_ICOUNT) || !(cflags & CF_NOIRQ)) {
count = tcg_temp_new_i32();
tcg_gen_ld_i32(count, cpu_env,
tcg_gen_ld_i32(count, tcg_env,
offsetof(ArchCPU, parent_obj.neg.icount_decr.u32)
- offsetof(ArchCPU, env));
}
@@ -79,7 +79,7 @@ static TCGOp *gen_tb_start(DisasContextBase *db, uint32_t cflags)
}
if (cflags & CF_USE_ICOUNT) {
tcg_gen_st16_i32(count, cpu_env,
tcg_gen_st16_i32(count, tcg_env,
offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.low)
- offsetof(ArchCPU, env));
}
include/tcg/tcg.h
+1 -1
View File
@@ -577,7 +577,7 @@ static inline bool temp_readonly(TCGTemp *ts)
extern __thread TCGContext *tcg_ctx;
extern const void *tcg_code_gen_epilogue;
extern uintptr_t tcg_splitwx_diff;
extern TCGv_env cpu_env;
extern TCGv_env tcg_env;
bool in_code_gen_buffer(const void *p);
target/alpha/translate.c
+71 -71
View File
@@ -131,13 +131,13 @@ void alpha_translate_init(void)
int i;
for (i = 0; i < 31; i++) {
cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env,
cpu_std_ir[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUAlphaState, ir[i]),
greg_names[i]);
}
for (i = 0; i < 31; i++) {
cpu_fir[i] = tcg_global_mem_new_i64(cpu_env,
cpu_fir[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUAlphaState, fir[i]),
freg_names[i]);
}
@@ -146,7 +146,7 @@ void alpha_translate_init(void)
memcpy(cpu_pal_ir, cpu_std_ir, sizeof(cpu_pal_ir));
for (i = 0; i < 8; i++) {
int r = (i == 7 ? 25 : i + 8);
cpu_pal_ir[r] = tcg_global_mem_new_i64(cpu_env,
cpu_pal_ir[r] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUAlphaState,
shadow[i]),
shadow_names[i]);
@@ -155,7 +155,7 @@ void alpha_translate_init(void)
for (i = 0; i < ARRAY_SIZE(vars); ++i) {
const GlobalVar *v = &vars[i];
*v->var = tcg_global_mem_new_i64(cpu_env, v->ofs, v->name);
*v->var = tcg_global_mem_new_i64(tcg_env, v->ofs, v->name);
}
}
@@ -244,12 +244,12 @@ static int get_flag_ofs(unsigned shift)
static void ld_flag_byte(TCGv val, unsigned shift)
{
tcg_gen_ld8u_i64(val, cpu_env, get_flag_ofs(shift));
tcg_gen_ld8u_i64(val, tcg_env, get_flag_ofs(shift));
}
static void st_flag_byte(TCGv val, unsigned shift)
{
tcg_gen_st8_i64(val, cpu_env, get_flag_ofs(shift));
tcg_gen_st8_i64(val, tcg_env, get_flag_ofs(shift));
}
static void gen_excp_1(int exception, int error_code)
@@ -258,7 +258,7 @@ static void gen_excp_1(int exception, int error_code)
tmp1 = tcg_constant_i32(exception);
tmp2 = tcg_constant_i32(error_code);
gen_helper_excp(cpu_env, tmp1, tmp2);
gen_helper_excp(tcg_env, tmp1, tmp2);
}
static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code)
@@ -582,7 +582,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int fn11)
tcg_gen_movi_i32(tmp, float_round_down);
break;
case QUAL_RM_D:
tcg_gen_ld8u_i32(tmp, cpu_env,
tcg_gen_ld8u_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fpcr_dyn_round));
break;
}
@@ -591,7 +591,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int fn11)
/* ??? The "fpu/softfloat.h" interface is to call set_float_rounding_mode.
With CONFIG_SOFTFLOAT that expands to an out-of-line call that just
sets the one field. */
tcg_gen_st8_i32(tmp, cpu_env,
tcg_gen_st8_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fp_status.float_rounding_mode));
#else
gen_helper_setroundmode(tmp);
@@ -611,7 +611,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int fn11)
tmp = tcg_temp_new_i32();
if (fn11) {
/* Underflow is enabled, use the FPCR setting. */
tcg_gen_ld8u_i32(tmp, cpu_env,
tcg_gen_ld8u_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fpcr_flush_to_zero));
} else {
/* Underflow is disabled, force flush-to-zero. */
@@ -619,7 +619,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int fn11)
}
#if defined(CONFIG_SOFTFLOAT_INLINE)
tcg_gen_st8_i32(tmp, cpu_env,
tcg_gen_st8_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fp_status.flush_to_zero));
#else
gen_helper_setflushzero(tmp);
@@ -636,16 +636,16 @@ static TCGv gen_ieee_input(DisasContext *ctx, int reg, int fn11, int is_cmp)
val = cpu_fir[reg];
if ((fn11 & QUAL_S) == 0) {
if (is_cmp) {
gen_helper_ieee_input_cmp(cpu_env, val);
gen_helper_ieee_input_cmp(tcg_env, val);
} else {
gen_helper_ieee_input(cpu_env, val);
gen_helper_ieee_input(tcg_env, val);
}
} else {
#ifndef CONFIG_USER_ONLY
/* In system mode, raise exceptions for denormals like real
hardware. In user mode, proceed as if the OS completion
handler is handling the denormal as per spec. */
gen_helper_ieee_input_s(cpu_env, val);
gen_helper_ieee_input_s(tcg_env, val);
#endif
}
}
@@ -678,9 +678,9 @@ static void gen_fp_exc_raise(int rc, int fn11)
or if we were to do something clever with imprecise exceptions. */
reg = tcg_constant_i32(rc + 32);
if (fn11 & QUAL_S) {
gen_helper_fp_exc_raise_s(cpu_env, ign, reg);
gen_helper_fp_exc_raise_s(tcg_env, ign, reg);
} else {
gen_helper_fp_exc_raise(cpu_env, ign, reg);
gen_helper_fp_exc_raise(tcg_env, ign, reg);
}
}
@@ -705,7 +705,7 @@ static void gen_ieee_arith2(DisasContext *ctx,
gen_qual_flushzero(ctx, fn11);
vb = gen_ieee_input(ctx, rb, fn11, 0);
helper(dest_fpr(ctx, rc), cpu_env, vb);
helper(dest_fpr(ctx, rc), tcg_env, vb);
gen_fp_exc_raise(rc, fn11);
}
@@ -732,10 +732,10 @@ static void gen_cvttq(DisasContext *ctx, int rb, int rc, int fn11)
/* Almost all integer conversions use cropped rounding;
special case that. */
if ((fn11 & QUAL_RM_MASK) == QUAL_RM_C) {
gen_helper_cvttq_c(vc, cpu_env, vb);
gen_helper_cvttq_c(vc, tcg_env, vb);
} else {
gen_qual_roundmode(ctx, fn11);
gen_helper_cvttq(vc, cpu_env, vb);
gen_helper_cvttq(vc, tcg_env, vb);
}
gen_fp_exc_raise(rc, fn11);
}
@@ -754,10 +754,10 @@ static void gen_ieee_intcvt(DisasContext *ctx,
is inexact. Thus we only need to worry about exceptions when
inexact handling is requested. */
if (fn11 & QUAL_I) {
helper(vc, cpu_env, vb);
helper(vc, tcg_env, vb);
gen_fp_exc_raise(rc, fn11);
} else {
helper(vc, cpu_env, vb);
helper(vc, tcg_env, vb);
}
}
@@ -797,7 +797,7 @@ static void gen_ieee_arith3(DisasContext *ctx,
va = gen_ieee_input(ctx, ra, fn11, 0);
vb = gen_ieee_input(ctx, rb, fn11, 0);
vc = dest_fpr(ctx, rc);
helper(vc, cpu_env, va, vb);
helper(vc, tcg_env, va, vb);
gen_fp_exc_raise(rc, fn11);
}
@@ -826,7 +826,7 @@ static void gen_ieee_compare(DisasContext *ctx,
va = gen_ieee_input(ctx, ra, fn11, 1);
vb = gen_ieee_input(ctx, rb, fn11, 1);
vc = dest_fpr(ctx, rc);
helper(vc, cpu_env, va, vb);
helper(vc, tcg_env, va, vb);
gen_fp_exc_raise(rc, fn11);
}
@@ -1059,12 +1059,12 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
break;
case 0x9E:
/* RDUNIQUE */
tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env,
tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,
offsetof(CPUAlphaState, unique));
break;
case 0x9F:
/* WRUNIQUE */
tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, unique));
break;
default:
@@ -1088,17 +1088,17 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
break;
case 0x2D:
/* WRVPTPTR */
tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, vptptr));
break;
case 0x31:
/* WRVAL */
tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, sysval));
break;
case 0x32:
/* RDVAL */
tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env,
tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,
offsetof(CPUAlphaState, sysval));
break;
@@ -1126,23 +1126,23 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
case 0x38:
/* WRUSP */
tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, usp));
break;
case 0x3A:
/* RDUSP */
tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env,
tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,
offsetof(CPUAlphaState, usp));
break;
case 0x3C:
/* WHAMI */
tcg_gen_ld32s_i64(ctx->ir[IR_V0], cpu_env,
tcg_gen_ld32s_i64(ctx->ir[IR_V0], tcg_env,
-offsetof(AlphaCPU, env) + offsetof(CPUState, cpu_index));
break;
case 0x3E:
/* WTINT */
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(AlphaCPU, env) +
offsetof(CPUState, halted));
tcg_gen_movi_i64(ctx->ir[IR_V0], 0);
@@ -1174,7 +1174,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
}
tcg_gen_movi_i64(tmp, exc_addr);
tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr));
tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr));
entry += (palcode & 0x80
? 0x2000 + (palcode - 0x80) * 64
@@ -1254,9 +1254,9 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno)
if (data == 0) {
tcg_gen_movi_i64(va, 0);
} else if (data & PR_LONG) {
tcg_gen_ld32s_i64(va, cpu_env, data & ~PR_LONG);
tcg_gen_ld32s_i64(va, tcg_env, data & ~PR_LONG);
} else {
tcg_gen_ld_i64(va, cpu_env, data);
tcg_gen_ld_i64(va, tcg_env, data);
}
break;
}
@@ -1272,17 +1272,17 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
switch (regno) {
case 255:
/* TBIA */
gen_helper_tbia(cpu_env);
gen_helper_tbia(tcg_env);
break;
case 254:
/* TBIS */
gen_helper_tbis(cpu_env, vb);
gen_helper_tbis(tcg_env, vb);
break;
case 253:
/* WAIT */
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(AlphaCPU, env) + offsetof(CPUState, halted));
return gen_excp(ctx, EXCP_HALTED, 0);
@@ -1296,16 +1296,16 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
if (translator_io_start(&ctx->base)) {
ret = DISAS_PC_STALE;
}
gen_helper_set_alarm(cpu_env, vb);
gen_helper_set_alarm(tcg_env, vb);
break;
case 7:
/* PALBR */
tcg_gen_st_i64(vb, cpu_env, offsetof(CPUAlphaState, palbr));
tcg_gen_st_i64(vb, tcg_env, offsetof(CPUAlphaState, palbr));
/* Changing the PAL base register implies un-chaining all of the TBs
that ended with a CALL_PAL. Since the base register usually only
changes during boot, flushing everything works well. */
gen_helper_tb_flush(cpu_env);
gen_helper_tb_flush(tcg_env);
return DISAS_PC_STALE;
case 32 ... 39:
@@ -1327,9 +1327,9 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
data = cpu_pr_data(regno);
if (data != 0) {
if (data & PR_LONG) {
tcg_gen_st32_i64(vb, cpu_env, data & ~PR_LONG);
tcg_gen_st32_i64(vb, tcg_env, data & ~PR_LONG);
} else {
tcg_gen_st_i64(vb, cpu_env, data);
tcg_gen_st_i64(vb, tcg_env, data);
}
}
break;
@@ -1594,7 +1594,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tcg_gen_ext32s_i64(vc, vb);
tcg_gen_add_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp);
gen_helper_check_overflow(cpu_env, vc, tmp);
gen_helper_check_overflow(tcg_env, vc, tmp);
break;
case 0x49:
/* SUBL/V */
@@ -1603,7 +1603,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tcg_gen_ext32s_i64(vc, vb);
tcg_gen_sub_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp);
gen_helper_check_overflow(cpu_env, vc, tmp);
gen_helper_check_overflow(tcg_env, vc, tmp);
break;
case 0x4D:
/* CMPLT */
@@ -1620,7 +1620,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tcg_gen_and_i64(tmp, tmp, tmp2);
tcg_gen_shri_i64(tmp, tmp, 63);
tcg_gen_movi_i64(tmp2, 0);
gen_helper_check_overflow(cpu_env, tmp, tmp2);
gen_helper_check_overflow(tcg_env, tmp, tmp2);
break;
case 0x69:
/* SUBQ/V */
@@ -1633,7 +1633,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tcg_gen_and_i64(tmp, tmp, tmp2);
tcg_gen_shri_i64(tmp, tmp, 63);
tcg_gen_movi_i64(tmp2, 0);
gen_helper_check_overflow(cpu_env, tmp, tmp2);
gen_helper_check_overflow(tcg_env, tmp, tmp2);
break;
case 0x6D:
/* CMPLE */
@@ -1924,7 +1924,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tcg_gen_ext32s_i64(vc, vb);
tcg_gen_mul_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp);
gen_helper_check_overflow(cpu_env, vc, tmp);
gen_helper_check_overflow(tcg_env, vc, tmp);
break;
case 0x60:
/* MULQ/V */
@@ -1932,7 +1932,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tmp2 = tcg_temp_new();
tcg_gen_muls2_i64(vc, tmp, va, vb);
tcg_gen_sari_i64(tmp2, vc, 63);
gen_helper_check_overflow(cpu_env, tmp, tmp2);
gen_helper_check_overflow(tcg_env, tmp, tmp2);
break;
default:
goto invalid_opc;
@@ -1957,7 +1957,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
REQUIRE_REG_31(ra);
REQUIRE_FEN;
vb = load_fpr(ctx, rb);
gen_helper_sqrtf(vc, cpu_env, vb);
gen_helper_sqrtf(vc, tcg_env, vb);
break;
case 0x0B:
/* SQRTS */
@@ -1986,7 +1986,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
REQUIRE_REG_31(ra);
REQUIRE_FEN;
vb = load_fpr(ctx, rb);
gen_helper_sqrtg(vc, cpu_env, vb);
gen_helper_sqrtg(vc, tcg_env, vb);
break;
case 0x02B:
/* SQRTT */
@@ -2009,22 +2009,22 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x00:
/* ADDF */
REQUIRE_FEN;
gen_helper_addf(vc, cpu_env, va, vb);
gen_helper_addf(vc, tcg_env, va, vb);
break;
case 0x01:
/* SUBF */
REQUIRE_FEN;
gen_helper_subf(vc, cpu_env, va, vb);
gen_helper_subf(vc, tcg_env, va, vb);
break;
case 0x02:
/* MULF */
REQUIRE_FEN;
gen_helper_mulf(vc, cpu_env, va, vb);
gen_helper_mulf(vc, tcg_env, va, vb);
break;
case 0x03:
/* DIVF */
REQUIRE_FEN;
gen_helper_divf(vc, cpu_env, va, vb);
gen_helper_divf(vc, tcg_env, va, vb);
break;
case 0x1E:
/* CVTDG -- TODO */
@@ -2033,43 +2033,43 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x20:
/* ADDG */
REQUIRE_FEN;
gen_helper_addg(vc, cpu_env, va, vb);
gen_helper_addg(vc, tcg_env, va, vb);
break;
case 0x21:
/* SUBG */
REQUIRE_FEN;
gen_helper_subg(vc, cpu_env, va, vb);
gen_helper_subg(vc, tcg_env, va, vb);
break;
case 0x22:
/* MULG */
REQUIRE_FEN;
gen_helper_mulg(vc, cpu_env, va, vb);
gen_helper_mulg(vc, tcg_env, va, vb);
break;
case 0x23:
/* DIVG */
REQUIRE_FEN;
gen_helper_divg(vc, cpu_env, va, vb);
gen_helper_divg(vc, tcg_env, va, vb);
break;
case 0x25:
/* CMPGEQ */
REQUIRE_FEN;
gen_helper_cmpgeq(vc, cpu_env, va, vb);
gen_helper_cmpgeq(vc, tcg_env, va, vb);
break;
case 0x26:
/* CMPGLT */
REQUIRE_FEN;
gen_helper_cmpglt(vc, cpu_env, va, vb);
gen_helper_cmpglt(vc, tcg_env, va, vb);
break;
case 0x27:
/* CMPGLE */
REQUIRE_FEN;
gen_helper_cmpgle(vc, cpu_env, va, vb);
gen_helper_cmpgle(vc, tcg_env, va, vb);
break;
case 0x2C:
/* CVTGF */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtgf(vc, cpu_env, vb);
gen_helper_cvtgf(vc, tcg_env, vb);
break;
case 0x2D:
/* CVTGD -- TODO */
@@ -2079,19 +2079,19 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
/* CVTGQ */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtgq(vc, cpu_env, vb);
gen_helper_cvtgq(vc, tcg_env, vb);
break;
case 0x3C:
/* CVTQF */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtqf(vc, cpu_env, vb);
gen_helper_cvtqf(vc, tcg_env, vb);
break;
case 0x3E:
/* CVTQG */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtqg(vc, cpu_env, vb);
gen_helper_cvtqg(vc, tcg_env, vb);
break;
default:
goto invalid_opc;
@@ -2242,7 +2242,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
/* MT_FPCR */
REQUIRE_FEN;
va = load_fpr(ctx, ra);
gen_helper_store_fpcr(cpu_env, va);
gen_helper_store_fpcr(tcg_env, va);
if (ctx->tb_rm == QUAL_RM_D) {
/* Re-do the copy of the rounding mode to fp_status
the next time we use dynamic rounding. */
@@ -2253,7 +2253,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
/* MF_FPCR */
REQUIRE_FEN;
va = dest_fpr(ctx, ra);
gen_helper_load_fpcr(va, cpu_env);
gen_helper_load_fpcr(va, tcg_env);
break;
case 0x02A:
/* FCMOVEQ */
@@ -2292,7 +2292,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
REQUIRE_FEN;
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
gen_helper_cvtql(vc, cpu_env, vb);
gen_helper_cvtql(vc, tcg_env, vb);
gen_fp_exc_raise(rc, fn11);
break;
default:
@@ -2332,7 +2332,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
if (translator_io_start(&ctx->base)) {
ret = DISAS_PC_STALE;
}
gen_helper_load_pcc(va, cpu_env);
gen_helper_load_pcc(va, tcg_env);
break;
case 0xE000:
/* RC */
@@ -2628,7 +2628,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
address from EXC_ADDR. This turns out to be useful for our
emulation PALcode, so continue to accept it. */
vb = dest_sink(ctx);
tcg_gen_ld_i64(vb, cpu_env, offsetof(CPUAlphaState, exc_addr));
tcg_gen_ld_i64(vb, tcg_env, offsetof(CPUAlphaState, exc_addr));
} else {
vb = load_gpr(ctx, rb);
}
target/arm/tcg/translate-a32.h
+1 -1
View File
@@ -55,7 +55,7 @@ bool mve_skip_vmov(DisasContext *s, int vn, int index, int size);
static inline TCGv_i32 load_cpu_offset(int offset)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_ld_i32(tmp, cpu_env, offset);
tcg_gen_ld_i32(tmp, tcg_env, offset);
return tmp;
}
target/arm/tcg/translate-a64.c
+189 -189
View File
File diff suppressed because it is too large Load Diff
target/arm/tcg/translate-a64.h
+2 -2
View File
@@ -115,7 +115,7 @@ static inline int vec_full_reg_offset(DisasContext *s, int regno)
static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
{
TCGv_ptr ret = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno));
tcg_gen_addi_ptr(ret, tcg_env, vec_full_reg_offset(s, regno));
return ret;
}
@@ -179,7 +179,7 @@ static inline int pred_gvec_reg_size(DisasContext *s)
static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno)
{
TCGv_ptr ret = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno));
tcg_gen_addi_ptr(ret, tcg_env, pred_full_reg_offset(s, regno));
return ret;
}
target/arm/tcg/translate-m-nocp.c
+12 -12
View File
@@ -85,9 +85,9 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
fptr = load_reg(s, a->rn);
if (a->l) {
gen_helper_v7m_vlldm(cpu_env, fptr);
gen_helper_v7m_vlldm(tcg_env, fptr);
} else {
gen_helper_v7m_vlstm(cpu_env, fptr);
gen_helper_v7m_vlstm(tcg_env, fptr);
}
clear_eci_state(s);
@@ -322,7 +322,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
switch (regno) {
case ARM_VFP_FPSCR:
tmp = loadfn(s, opaque, true);
gen_helper_vfp_set_fpscr(cpu_env, tmp);
gen_helper_vfp_set_fpscr(tcg_env, tmp);
gen_lookup_tb(s);
break;
case ARM_VFP_FPSCR_NZCVQC:
@@ -391,7 +391,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
R_V7M_CONTROL_SFPA_SHIFT, 1);
store_cpu_field(control, v7m.control[M_REG_S]);
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
gen_helper_vfp_set_fpscr(cpu_env, tmp);
gen_helper_vfp_set_fpscr(tcg_env, tmp);
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
break;
}
@@ -451,12 +451,12 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
switch (regno) {
case ARM_VFP_FPSCR:
tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env);
gen_helper_vfp_get_fpscr(tmp, tcg_env);
storefn(s, opaque, tmp, true);
break;
case ARM_VFP_FPSCR_NZCVQC:
tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env);
gen_helper_vfp_get_fpscr(tmp, tcg_env);
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK);
storefn(s, opaque, tmp, true);
break;
@@ -475,7 +475,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
/* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */
tmp = tcg_temp_new_i32();
sfpa = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env);
gen_helper_vfp_get_fpscr(tmp, tcg_env);
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
control = load_cpu_field(v7m.control[M_REG_S]);
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
@@ -493,7 +493,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
store_cpu_field(control, v7m.control[M_REG_S]);
fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
gen_helper_vfp_set_fpscr(tcg_env, fpscr);
lookup_tb = true;
break;
}
@@ -528,7 +528,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
tmp = tcg_temp_new_i32();
sfpa = tcg_temp_new_i32();
fpscr = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(fpscr, cpu_env);
gen_helper_vfp_get_fpscr(fpscr, tcg_env);
tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
control = load_cpu_field(v7m.control[M_REG_S]);
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
@@ -540,7 +540,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0),
fpdscr, fpscr);
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
gen_helper_vfp_set_fpscr(tcg_env, fpscr);
break;
}
case ARM_VFP_VPR:
@@ -643,7 +643,7 @@ static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value,
}
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
gen_helper_v8m_stackcheck(cpu_env, addr);
gen_helper_v8m_stackcheck(tcg_env, addr);
}
if (do_access) {
@@ -682,7 +682,7 @@ static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque,
}
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
gen_helper_v8m_stackcheck(cpu_env, addr);
gen_helper_v8m_stackcheck(tcg_env, addr);
}
if (do_access) {
target/arm/tcg/translate-mve.c
+26 -26
View File
@@ -56,7 +56,7 @@ static inline long mve_qreg_offset(unsigned reg)
static TCGv_ptr mve_qreg_ptr(unsigned reg)
{
TCGv_ptr ret = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg));
tcg_gen_addi_ptr(ret, tcg_env, mve_qreg_offset(reg));
return ret;
}
@@ -173,7 +173,7 @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
}
qreg = mve_qreg_ptr(a->qd);
fn(cpu_env, qreg, addr);
fn(tcg_env, qreg, addr);
/*
* Writeback always happens after the last beat of the insn,
@@ -234,7 +234,7 @@ static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a, MVEGenLdStSGFn fn)
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, addr);
fn(tcg_env, qd, qm, addr);
mve_update_eci(s);
return true;
}
@@ -330,7 +330,7 @@ static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_sg_imm *a,
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, tcg_constant_i32(offset));
fn(tcg_env, qd, qm, tcg_constant_i32(offset));
mve_update_eci(s);
return true;
}
@@ -397,7 +397,7 @@ static bool do_vldst_il(DisasContext *s, arg_vldst_il *a, MVEGenLdStIlFn *fn,
* We pass the index of Qd, not a pointer, because the helper must
* access multiple Q registers starting at Qd and working up.
*/
fn(cpu_env, tcg_constant_i32(a->qd), rn);
fn(tcg_env, tcg_constant_i32(a->qd), rn);
if (a->w) {
tcg_gen_addi_i32(rn, rn, addrinc);
@@ -491,7 +491,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
} else {
qd = mve_qreg_ptr(a->qd);
tcg_gen_dup_i32(a->size, rt, rt);
gen_helper_mve_vdup(cpu_env, qd, rt);
gen_helper_mve_vdup(tcg_env, qd, rt);
}
mve_update_eci(s);
return true;
@@ -517,7 +517,7 @@ static bool do_1op_vec(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn,
} else {
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm);
fn(tcg_env, qd, qm);
}
mve_update_eci(s);
return true;
@@ -612,7 +612,7 @@ static bool do_vcvt_rmode(DisasContext *s, arg_1op *a,
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode)));
fn(tcg_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode)));
mve_update_eci(s);
return true;
}
@@ -800,7 +800,7 @@ static bool do_2op_vec(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn,
qd = mve_qreg_ptr(a->qd);
qn = mve_qreg_ptr(a->qn);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qn, qm);
fn(tcg_env, qd, qn, qm);
}
mve_update_eci(s);
return true;
@@ -1052,7 +1052,7 @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
qd = mve_qreg_ptr(a->qd);
qn = mve_qreg_ptr(a->qn);
rm = load_reg(s, a->rm);
fn(cpu_env, qd, qn, rm);
fn(tcg_env, qd, qn, rm);
mve_update_eci(s);
return true;
}
@@ -1183,7 +1183,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
rda_i = tcg_constant_i64(0);
}
fn(rda_o, cpu_env, qn, qm, rda_i);
fn(rda_o, tcg_env, qn, qm, rda_i);
rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
@@ -1281,7 +1281,7 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
rda_o = tcg_temp_new_i32();
}
fn(rda_o, cpu_env, qn, qm, rda_i);
fn(rda_o, tcg_env, qn, qm, rda_i);
store_reg(s, a->rda, rda_o);
mve_update_eci(s);
@@ -1377,7 +1377,7 @@ static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a)
return true;
}
gen_helper_mve_vpnot(cpu_env);
gen_helper_mve_vpnot(tcg_env);
/* This insn updates predication bits */
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
mve_update_eci(s);
@@ -1419,7 +1419,7 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
}
qm = mve_qreg_ptr(a->qm);
fns[a->size][a->u](rda_o, cpu_env, qm, rda_i);
fns[a->size][a->u](rda_o, tcg_env, qm, rda_i);
store_reg(s, a->rda, rda_o);
mve_update_eci(s);
@@ -1471,9 +1471,9 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
qm = mve_qreg_ptr(a->qm);
if (a->u) {
gen_helper_mve_vaddlv_u(rda_o, cpu_env, qm, rda_i);
gen_helper_mve_vaddlv_u(rda_o, tcg_env, qm, rda_i);
} else {
gen_helper_mve_vaddlv_s(rda_o, cpu_env, qm, rda_i);
gen_helper_mve_vaddlv_s(rda_o, tcg_env, qm, rda_i);
}
rdalo = tcg_temp_new_i32();
@@ -1508,7 +1508,7 @@ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn,
imm, 16, 16);
} else {
qd = mve_qreg_ptr(a->qd);
fn(cpu_env, qd, tcg_constant_i64(imm));
fn(tcg_env, qd, tcg_constant_i64(imm));
}
mve_update_eci(s);
return true;
@@ -1580,7 +1580,7 @@ static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
} else {
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, tcg_constant_i32(shift));
fn(tcg_env, qd, qm, tcg_constant_i32(shift));
}
mve_update_eci(s);
return true;
@@ -1685,7 +1685,7 @@ static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a,
qda = mve_qreg_ptr(a->qda);
rm = load_reg(s, a->rm);
fn(cpu_env, qda, qda, rm);
fn(tcg_env, qda, qda, rm);
mve_update_eci(s);
return true;
}
@@ -1827,7 +1827,7 @@ static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
qd = mve_qreg_ptr(a->qd);
rdm = load_reg(s, a->rdm);
gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
gen_helper_mve_vshlc(rdm, tcg_env, qd, rdm, tcg_constant_i32(a->imm));
store_reg(s, a->rdm, rdm);
mve_update_eci(s);
return true;
@@ -1856,7 +1856,7 @@ static bool do_vidup(DisasContext *s, arg_vidup *a, MVEGenVIDUPFn *fn)
qd = mve_qreg_ptr(a->qd);
rn = load_reg(s, a->rn);
fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm));
fn(rn, tcg_env, qd, rn, tcg_constant_i32(a->imm));
store_reg(s, a->rn, rn);
mve_update_eci(s);
return true;
@@ -1891,7 +1891,7 @@ static bool do_viwdup(DisasContext *s, arg_viwdup *a, MVEGenVIWDUPFn *fn)
qd = mve_qreg_ptr(a->qd);
rn = load_reg(s, a->rn);
rm = load_reg(s, a->rm);
fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm));
fn(rn, tcg_env, qd, rn, rm, tcg_constant_i32(a->imm));
store_reg(s, a->rn, rn);
mve_update_eci(s);
return true;
@@ -1957,7 +1957,7 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn)
qn = mve_qreg_ptr(a->qn);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qn, qm);
fn(tcg_env, qn, qm);
if (a->mask) {
/* VPT */
gen_vpst(s, a->mask);
@@ -1988,7 +1988,7 @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a,
} else {
rm = load_reg(s, a->rm);
}
fn(cpu_env, qn, rm);
fn(tcg_env, qn, rm);
if (a->mask) {
/* VPT */
gen_vpst(s, a->mask);
@@ -2089,7 +2089,7 @@ static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn)
qm = mve_qreg_ptr(a->qm);
rda = load_reg(s, a->rda);
fn(rda, cpu_env, qm, rda);
fn(rda, tcg_env, qm, rda);
store_reg(s, a->rda, rda);
mve_update_eci(s);
return true;
@@ -2153,7 +2153,7 @@ static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn)
qm = mve_qreg_ptr(a->qm);
qn = mve_qreg_ptr(a->qn);
rda = load_reg(s, a->rda);
fn(rda, cpu_env, qn, qm, rda);
fn(rda, tcg_env, qn, qm, rda);
store_reg(s, a->rda, rda);
mve_update_eci(s);
return true;
target/arm/tcg/translate-neon.c
+39 -39
View File
@@ -32,7 +32,7 @@
static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
{
TCGv_ptr ret = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg));
tcg_gen_addi_ptr(ret, tcg_env, vfp_reg_offset(dp, reg));
return ret;
}
@@ -42,13 +42,13 @@ static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
switch (mop) {
case MO_UB:
tcg_gen_ld8u_i32(var, cpu_env, offset);
tcg_gen_ld8u_i32(var, tcg_env, offset);
break;
case MO_UW:
tcg_gen_ld16u_i32(var, cpu_env, offset);
tcg_gen_ld16u_i32(var, tcg_env, offset);
break;
case MO_UL:
tcg_gen_ld_i32(var, cpu_env, offset);
tcg_gen_ld_i32(var, tcg_env, offset);
break;
default:
g_assert_not_reached();
@@ -61,16 +61,16 @@ static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
switch (mop) {
case MO_UB:
tcg_gen_ld8u_i64(var, cpu_env, offset);
tcg_gen_ld8u_i64(var, tcg_env, offset);
break;
case MO_UW:
tcg_gen_ld16u_i64(var, cpu_env, offset);
tcg_gen_ld16u_i64(var, tcg_env, offset);
break;
case MO_UL:
tcg_gen_ld32u_i64(var, cpu_env, offset);
tcg_gen_ld32u_i64(var, tcg_env, offset);
break;
case MO_UQ:
tcg_gen_ld_i64(var, cpu_env, offset);
tcg_gen_ld_i64(var, tcg_env, offset);
break;
default:
g_assert_not_reached();
@@ -83,13 +83,13 @@ static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
switch (size) {
case MO_8:
tcg_gen_st8_i32(var, cpu_env, offset);
tcg_gen_st8_i32(var, tcg_env, offset);
break;
case MO_16:
tcg_gen_st16_i32(var, cpu_env, offset);
tcg_gen_st16_i32(var, tcg_env, offset);
break;
case MO_32:
tcg_gen_st_i32(var, cpu_env, offset);
tcg_gen_st_i32(var, tcg_env, offset);
break;
default:
g_assert_not_reached();
@@ -102,16 +102,16 @@ static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
switch (size) {
case MO_8:
tcg_gen_st8_i64(var, cpu_env, offset);
tcg_gen_st8_i64(var, tcg_env, offset);
break;
case MO_16:
tcg_gen_st16_i64(var, cpu_env, offset);
tcg_gen_st16_i64(var, tcg_env, offset);
break;
case MO_32:
tcg_gen_st32_i64(var, cpu_env, offset);
tcg_gen_st32_i64(var, tcg_env, offset);
break;
case MO_64:
tcg_gen_st_i64(var, cpu_env, offset);
tcg_gen_st_i64(var, tcg_env, offset);
break;
default:
g_assert_not_reached();
@@ -296,7 +296,7 @@ static bool trans_VFML(DisasContext *s, arg_VFML *a)
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
vfp_reg_offset(a->q, a->vn),
vfp_reg_offset(a->q, a->vm),
cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
tcg_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
gen_helper_gvec_fmlal_a32);
return true;
}
@@ -390,7 +390,7 @@ static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
vfp_reg_offset(a->q, a->vn),
vfp_reg_offset(a->q, a->rm),
cpu_env, opr_sz, opr_sz,
tcg_env, opr_sz, opr_sz,
(a->index << 2) | a->s, /* is_2 == 0 */
gen_helper_gvec_fmlal_idx_a32);
return true;
@@ -920,7 +920,7 @@ DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1)
#define DO_3SAME_64_ENV(INSN, FUNC) \
static void gen_##INSN##_elt(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \
{ \
FUNC(d, cpu_env, n, m); \
FUNC(d, tcg_env, n, m); \
} \
DO_3SAME_64(INSN, gen_##INSN##_elt)
@@ -953,7 +953,7 @@ DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64)
}
/*
* Some helper functions need to be passed the cpu_env. In order
* Some helper functions need to be passed the tcg_env. In order
* to use those with the gvec APIs like tcg_gen_gvec_3() we need
* to create wrapper functions whose prototype is a NeonGenTwoOpFn()
* and which call a NeonGenTwoOpEnvFn().
@@ -961,7 +961,7 @@ DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64)
#define WRAP_ENV_FN(WRAPNAME, FUNC) \
static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \
{ \
FUNC(d, cpu_env, n, m); \
FUNC(d, tcg_env, n, m); \
}
#define DO_3SAME_32_ENV(INSN, FUNC) \
@@ -1305,7 +1305,7 @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
{
/*
* 2-reg-and-shift operations, size == 3 case, where the
* function needs to be passed cpu_env.
* function needs to be passed tcg_env.
*/
TCGv_i64 constimm;
int pass;
@@ -1338,7 +1338,7 @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
TCGv_i64 tmp = tcg_temp_new_i64();
read_neon_element64(tmp, a->vm, pass, MO_64);
fn(tmp, cpu_env, tmp, constimm);
fn(tmp, tcg_env, tmp, constimm);
write_neon_element64(tmp, a->vd, pass, MO_64);
}
return true;
@@ -1349,7 +1349,7 @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
{
/*
* 2-reg-and-shift operations, size < 3 case, where the
* helper needs to be passed cpu_env.
* helper needs to be passed tcg_env.
*/
TCGv_i32 constimm, tmp;
int pass;
@@ -1381,7 +1381,7 @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
read_neon_element32(tmp, a->vm, pass, MO_32);
fn(tmp, cpu_env, tmp, constimm);
fn(tmp, tcg_env, tmp, constimm);
write_neon_element32(tmp, a->vd, pass, MO_32);
}
return true;
@@ -1447,11 +1447,11 @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
read_neon_element64(rm2, a->vm, 1, MO_64);
shiftfn(rm1, rm1, constimm);
narrowfn(rd, cpu_env, rm1);
narrowfn(rd, tcg_env, rm1);
write_neon_element32(rd, a->vd, 0, MO_32);
shiftfn(rm2, rm2, constimm);
narrowfn(rd, cpu_env, rm2);
narrowfn(rd, tcg_env, rm2);
write_neon_element32(rd, a->vd, 1, MO_32);
return true;
@@ -1514,7 +1514,7 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
tcg_gen_concat_i32_i64(rtmp, rm1, rm2);
narrowfn(rm1, cpu_env, rtmp);
narrowfn(rm1, tcg_env, rtmp);
write_neon_element32(rm1, a->vd, 0, MO_32);
shiftfn(rm3, rm3, constimm);
@@ -1522,7 +1522,7 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
narrowfn(rm3, cpu_env, rtmp);
narrowfn(rm3, tcg_env, rtmp);
write_neon_element32(rm3, a->vd, 1, MO_32);
return true;
}
@@ -2159,13 +2159,13 @@ DO_VMLAL(VMLSL_U,mull_u,sub)
static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
{
gen_helper_neon_mull_s16(rd, rn, rm);
gen_helper_neon_addl_saturate_s32(rd, cpu_env, rd, rd);
gen_helper_neon_addl_saturate_s32(rd, tcg_env, rd, rd);
}
static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
{
gen_mull_s32(rd, rn, rm);
gen_helper_neon_addl_saturate_s64(rd, cpu_env, rd, rd);
gen_helper_neon_addl_saturate_s64(rd, tcg_env, rd, rd);
}
static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a)
@@ -2182,12 +2182,12 @@ static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a)
static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{
gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm);
gen_helper_neon_addl_saturate_s32(rd, tcg_env, rn, rm);
}
static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{
gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm);
gen_helper_neon_addl_saturate_s64(rd, tcg_env, rn, rm);
}
static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a)
@@ -2211,13 +2211,13 @@ static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a)
static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{
gen_helper_neon_negl_u32(rm, rm);
gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm);
gen_helper_neon_addl_saturate_s32(rd, tcg_env, rn, rm);
}
static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{
tcg_gen_neg_i64(rm, rm);
gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm);
gen_helper_neon_addl_saturate_s64(rd, tcg_env, rn, rm);
}
static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a)
@@ -2550,7 +2550,7 @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
read_neon_element32(rn, a->vn, pass, MO_32);
read_neon_element32(rd, a->vd, pass, MO_32);
opfn(rd, cpu_env, rn, scalar, rd);
opfn(rd, tcg_env, rn, scalar, rd);
write_neon_element32(rd, a->vd, pass, MO_32);
}
return true;
@@ -2837,7 +2837,7 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
val = tcg_temp_new_i64();
read_neon_element64(val, a->vm, 0, MO_64);
gen_helper_neon_tbl(val, cpu_env, desc, val, def);
gen_helper_neon_tbl(val, tcg_env, desc, val, def);
write_neon_element64(val, a->vd, 0, MO_64);
return true;
}
@@ -3171,9 +3171,9 @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
rd1 = tcg_temp_new_i32();
read_neon_element64(rm, a->vm, 0, MO_64);
narrowfn(rd0, cpu_env, rm);
narrowfn(rd0, tcg_env, rm);
read_neon_element64(rm, a->vm, 1, MO_64);
narrowfn(rd1, cpu_env, rm);
narrowfn(rd1, tcg_env, rm);
write_neon_element32(rd0, a->vd, 0, MO_32);
write_neon_element32(rd1, a->vd, 1, MO_32);
return true;
@@ -3625,7 +3625,7 @@ static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a)
#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \
static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \
{ \
FUNC(d, cpu_env, m); \
FUNC(d, tcg_env, m); \
}
WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8)
target/arm/tcg/translate-sme.c
+4 -4
View File
@@ -90,7 +90,7 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
/* Add the byte offset to env to produce the final pointer. */
addr = tcg_temp_new_ptr();
tcg_gen_ext_i32_ptr(addr, tmp);
tcg_gen_add_ptr(addr, addr, cpu_env);
tcg_gen_add_ptr(addr, addr, tcg_env);
return addr;
}
@@ -106,7 +106,7 @@ static TCGv_ptr get_tile(DisasContext *s, int esz, int tile)
offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray);
tcg_gen_addi_ptr(addr, cpu_env, offset);
tcg_gen_addi_ptr(addr, tcg_env, offset);
return addr;
}
@@ -116,7 +116,7 @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
return false;
}
if (sme_za_enabled_check(s)) {
gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm),
gen_helper_sme_zero(tcg_env, tcg_constant_i32(a->imm),
tcg_constant_i32(streaming_vec_reg_size(s)));
}
return true;
@@ -237,7 +237,7 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
svl = streaming_vec_reg_size(s);
desc = simd_desc(svl, svl, desc);
fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr,
fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
tcg_constant_i32(desc));
return true;
}
target/arm/tcg/translate-sve.c
+86 -86
View File
@@ -497,8 +497,8 @@ static void do_predtest(DisasContext *s, int dofs, int gofs, int words)
TCGv_ptr gptr = tcg_temp_new_ptr();
TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_addi_ptr(dptr, cpu_env, dofs);
tcg_gen_addi_ptr(gptr, cpu_env, gofs);
tcg_gen_addi_ptr(dptr, tcg_env, dofs);
tcg_gen_addi_ptr(gptr, tcg_env, gofs);
gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words));
@@ -956,8 +956,8 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
t_zn = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
fn(temp, t_zn, t_pg, desc);
write_fp_dreg(s, a->rd, temp);
@@ -1209,7 +1209,7 @@ static bool do_index(DisasContext *s, int esz, int rd,
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
t_zd = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, rd));
if (esz == 3) {
gen_helper_sve_index_d(t_zd, start, incr, desc);
} else {
@@ -1379,12 +1379,12 @@ static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a,
TCGv_i64 pm = tcg_temp_new_i64();
TCGv_i64 pg = tcg_temp_new_i64();
tcg_gen_ld_i64(pn, cpu_env, nofs);
tcg_gen_ld_i64(pm, cpu_env, mofs);
tcg_gen_ld_i64(pg, cpu_env, gofs);
tcg_gen_ld_i64(pn, tcg_env, nofs);
tcg_gen_ld_i64(pm, tcg_env, mofs);
tcg_gen_ld_i64(pg, tcg_env, gofs);
gvec_op->fni8(pd, pn, pm, pg);
tcg_gen_st_i64(pd, cpu_env, dofs);
tcg_gen_st_i64(pd, tcg_env, dofs);
do_predtest1(pd, pg);
} else {
@@ -1654,8 +1654,8 @@ static bool trans_PTEST(DisasContext *s, arg_PTEST *a)
TCGv_i64 pn = tcg_temp_new_i64();
TCGv_i64 pg = tcg_temp_new_i64();
tcg_gen_ld_i64(pn, cpu_env, nofs);
tcg_gen_ld_i64(pg, cpu_env, gofs);
tcg_gen_ld_i64(pn, tcg_env, nofs);
tcg_gen_ld_i64(pg, tcg_env, gofs);
do_predtest1(pn, pg);
} else {
do_predtest(s, nofs, gofs, words);
@@ -1736,7 +1736,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
t = tcg_temp_new_i64();
if (fullsz <= 64) {
tcg_gen_movi_i64(t, lastword);
tcg_gen_st_i64(t, cpu_env, ofs);
tcg_gen_st_i64(t, tcg_env, ofs);
goto done;
}
@@ -1755,17 +1755,17 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
tcg_gen_movi_i64(t, word);
for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
tcg_gen_st_i64(t, cpu_env, ofs + i);
tcg_gen_st_i64(t, tcg_env, ofs + i);
}
if (lastword != word) {
tcg_gen_movi_i64(t, lastword);
tcg_gen_st_i64(t, cpu_env, ofs + i);
tcg_gen_st_i64(t, tcg_env, ofs + i);
i += 8;
}
if (i < fullsz) {
tcg_gen_movi_i64(t, 0);
for (; i < fullsz; i += 8) {
tcg_gen_st_i64(t, cpu_env, ofs + i);
tcg_gen_st_i64(t, tcg_env, ofs + i);
}
}
@@ -1822,8 +1822,8 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_pd, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->rn));
t = tcg_temp_new_i32();
gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc));
@@ -1919,8 +1919,8 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
dptr = tcg_temp_new_ptr();
nptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd));
tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn));
tcg_gen_addi_ptr(dptr, tcg_env, vec_full_reg_offset(s, rd));
tcg_gen_addi_ptr(nptr, tcg_env, vec_full_reg_offset(s, rn));
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
switch (esz) {
@@ -2163,9 +2163,9 @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
TCGv_ptr t_zn = tcg_temp_new_ptr();
TCGv_ptr t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, rn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, rd));
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, rn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
fns[esz](t_zd, t_zn, t_pg, val, desc);
}
@@ -2310,8 +2310,8 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
TCGv_ptr t_zd = tcg_temp_new_ptr();
TCGv_ptr t_zn = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
fns[a->esz](t_zd, t_zn, val, desc);
}
@@ -2323,7 +2323,7 @@ static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a)
}
if (sve_access_check(s)) {
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64));
tcg_gen_ld_i64(t, tcg_env, vec_reg_offset(s, a->rm, 0, MO_64));
do_insr_i64(s, a, t);
}
return true;
@@ -2409,9 +2409,9 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd);
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(t_d, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_n, tcg_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_m, tcg_env, pred_full_reg_offset(s, a->rm));
fn(t_d, t_n, t_m, tcg_constant_i32(desc));
return true;
@@ -2429,8 +2429,8 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
TCGv_ptr t_n = tcg_temp_new_ptr();
uint32_t desc = 0;
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_d, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_n, tcg_env, pred_full_reg_offset(s, a->rn));
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
@@ -2525,7 +2525,7 @@ static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg)
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg));
tcg_gen_addi_ptr(t_p, tcg_env, pred_full_reg_offset(s, pg));
gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc));
}
@@ -2602,7 +2602,7 @@ static TCGv_i64 load_last_active(DisasContext *s, TCGv_i32 last,
}
#endif
tcg_gen_ext_i32_ptr(p, last);
tcg_gen_add_ptr(p, p, cpu_env);
tcg_gen_add_ptr(p, p, tcg_env);
return load_esz(p, vec_full_reg_offset(s, rm), esz);
}
@@ -2674,7 +2674,7 @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
}
/* The conceit here is that while last < 0 indicates not found, after
* adjusting for cpu_env->vfp.zregs[rm], it is still a valid address
* adjusting for tcg_env->vfp.zregs[rm], it is still a valid address
* from which we can load garbage. We then discard the garbage with
* a conditional move.
*/
@@ -2690,7 +2690,7 @@ static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before)
if (sve_access_check(s)) {
int esz = a->esz;
int ofs = vec_reg_offset(s, a->rd, 0, esz);
TCGv_i64 reg = load_esz(cpu_env, ofs, esz);
TCGv_i64 reg = load_esz(tcg_env, ofs, esz);
do_clast_scalar(s, esz, a->pg, a->rn, before, reg);
write_fp_dreg(s, a->rd, reg);
@@ -2794,7 +2794,7 @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a)
}
if (sve_access_check(s)) {
int ofs = vec_reg_offset(s, a->rn, 0, a->esz);
TCGv_i64 t = load_esz(cpu_env, ofs, a->esz);
TCGv_i64 t = load_esz(tcg_env, ofs, a->esz);
do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t);
}
return true;
@@ -2847,10 +2847,10 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
zm = tcg_temp_new_ptr();
pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
tcg_gen_addi_ptr(pd, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(zm, tcg_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(pg, tcg_env, pred_full_reg_offset(s, a->pg));
gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0)));
@@ -2920,9 +2920,9 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
zn = tcg_temp_new_ptr();
pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
tcg_gen_addi_ptr(pd, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(pg, tcg_env, pred_full_reg_offset(s, a->pg));
gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm)));
@@ -2971,10 +2971,10 @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
TCGv_ptr g = tcg_temp_new_ptr();
TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(m, cpu_env, pred_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
tcg_gen_addi_ptr(d, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(n, tcg_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(m, tcg_env, pred_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(g, tcg_env, pred_full_reg_offset(s, a->pg));
if (a->s) {
TCGv_i32 t = tcg_temp_new_i32();
@@ -3001,9 +3001,9 @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
TCGv_ptr g = tcg_temp_new_ptr();
TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
tcg_gen_addi_ptr(d, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(n, tcg_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(g, tcg_env, pred_full_reg_offset(s, a->pg));
if (a->s) {
TCGv_i32 t = tcg_temp_new_i32();
@@ -3044,10 +3044,10 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
if (psz <= 8) {
uint64_t psz_mask;
tcg_gen_ld_i64(val, cpu_env, pred_full_reg_offset(s, pn));
tcg_gen_ld_i64(val, tcg_env, pred_full_reg_offset(s, pn));
if (pn != pg) {
TCGv_i64 g = tcg_temp_new_i64();
tcg_gen_ld_i64(g, cpu_env, pred_full_reg_offset(s, pg));
tcg_gen_ld_i64(g, tcg_env, pred_full_reg_offset(s, pg));
tcg_gen_and_i64(val, val, g);
}
@@ -3066,8 +3066,8 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz);
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
tcg_gen_addi_ptr(t_pn, tcg_env, pred_full_reg_offset(s, pn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc));
}
@@ -3291,7 +3291,7 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(ptr, tcg_env, pred_full_reg_offset(s, a->rd));
if (a->lt) {
gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
@@ -3354,7 +3354,7 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(ptr, tcg_env, pred_full_reg_offset(s, a->rd));
gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
do_pred_flags(t2);
@@ -3684,8 +3684,8 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
t_zn = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
fn(temp, t_zn, t_pg, status, t_desc);
@@ -3802,11 +3802,11 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
return true;
}
t_val = load_esz(cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz);
t_val = load_esz(tcg_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz);
t_rm = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
tcg_gen_addi_ptr(t_rm, tcg_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
@@ -3878,9 +3878,9 @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
t_zd = tcg_temp_new_ptr();
t_zn = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, zd));
tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, zn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, zd));
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, zn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
@@ -4228,7 +4228,7 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
/*
* Predicate register loads can be any multiple of 2.
* Note that we still store the entire 64-bit unit into cpu_env.
* Note that we still store the entire 64-bit unit into tcg_env.
*/
if (len_remain >= 8) {
t0 = tcg_temp_new_i64();
@@ -4370,7 +4370,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = vec_full_reg_size(s);
int off = vec_full_reg_offset(s, a->rd);
gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
gen_sve_ldr(s, tcg_env, off, size, a->rn, a->imm * size);
}
return true;
}
@@ -4383,7 +4383,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = pred_full_reg_size(s);
int off = pred_full_reg_offset(s, a->rd);
gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
gen_sve_ldr(s, tcg_env, off, size, a->rn, a->imm * size);
}
return true;
}
@@ -4396,7 +4396,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = vec_full_reg_size(s);
int off = vec_full_reg_offset(s, a->rd);
gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
gen_sve_str(s, tcg_env, off, size, a->rn, a->imm * size);
}
return true;
}
@@ -4409,7 +4409,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = pred_full_reg_size(s);
int off = pred_full_reg_offset(s, a->rd);
gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
gen_sve_str(s, tcg_env, off, size, a->rn, a->imm * size);
}
return true;
}
@@ -4465,8 +4465,8 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
desc = simd_desc(vsz, vsz, zt | desc);
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
fn(cpu_env, t_pg, addr, tcg_constant_i32(desc));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
}
/* Indexed by [mte][be][dtype][nreg] */
@@ -4860,18 +4860,18 @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
#if HOST_BIG_ENDIAN
poff += 6;
#endif
tcg_gen_ld16u_i64(tmp, cpu_env, poff);
tcg_gen_ld16u_i64(tmp, tcg_env, poff);
poff = offsetof(CPUARMState, vfp.preg_tmp);
tcg_gen_st_i64(tmp, cpu_env, poff);
tcg_gen_st_i64(tmp, tcg_env, poff);
}
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_pg, cpu_env, poff);
tcg_gen_addi_ptr(t_pg, tcg_env, poff);
gen_helper_gvec_mem *fn
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
/* Replicate that first quadword. */
if (vsz > 16) {
@@ -4939,18 +4939,18 @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
#if HOST_BIG_ENDIAN
poff += 4;
#endif
tcg_gen_ld32u_i64(tmp, cpu_env, poff);
tcg_gen_ld32u_i64(tmp, tcg_env, poff);
poff = offsetof(CPUARMState, vfp.preg_tmp);
tcg_gen_st_i64(tmp, cpu_env, poff);
tcg_gen_st_i64(tmp, tcg_env, poff);
}
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_pg, cpu_env, poff);
tcg_gen_addi_ptr(t_pg, tcg_env, poff);
gen_helper_gvec_mem *fn
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
/*
* Replicate that first octaword.
@@ -5027,7 +5027,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
*/
uint64_t psz_mask = MAKE_64BIT_MASK(0, psz * 8);
temp = tcg_temp_new_i64();
tcg_gen_ld_i64(temp, cpu_env, pred_full_reg_offset(s, a->pg));
tcg_gen_ld_i64(temp, tcg_env, pred_full_reg_offset(s, a->pg));
tcg_gen_andi_i64(temp, temp, pred_esz_masks[esz] & psz_mask);
tcg_gen_brcondi_i64(TCG_COND_EQ, temp, 0, over);
} else {
@@ -5238,10 +5238,10 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
}
desc = simd_desc(vsz, vsz, desc | scale);
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm));
tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt));
fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
}
/* Indexed by [mte][be][ff][xs][u][msz]. */
@@ -7197,7 +7197,7 @@ static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
{
return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzzw_s,
a->rd, a->rn, a->rm, a->ra,
(sel << 1) | sub, cpu_env);
(sel << 1) | sub, tcg_env);
}
TRANS_FEAT(FMLALB_zzzw, aa64_sve2, do_FMLAL_zzzw, a, false, false)
@@ -7209,7 +7209,7 @@ static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool sel)
{
return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzxw_s,
a->rd, a->rn, a->rm, a->ra,
(a->index << 2) | (sel << 1) | sub, cpu_env);
(a->index << 2) | (sel << 1) | sub, tcg_env);
}
TRANS_FEAT(FMLALB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, false)
@@ -7289,7 +7289,7 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a)
/* Load the predicate word. */
tcg_gen_trunc_i64_ptr(ptr, didx);
tcg_gen_add_ptr(ptr, ptr, cpu_env);
tcg_gen_add_ptr(ptr, ptr, tcg_env);
tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm));
/* Extract the predicate bit and replicate to MO_64. */
target/arm/tcg/translate-vfp.c
+28 -28
View File
@@ -30,22 +30,22 @@
static inline void vfp_load_reg64(TCGv_i64 var, int reg)
{
tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
tcg_gen_ld_i64(var, tcg_env, vfp_reg_offset(true, reg));
}
static inline void vfp_store_reg64(TCGv_i64 var, int reg)
{
tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
tcg_gen_st_i64(var, tcg_env, vfp_reg_offset(true, reg));
}
static inline void vfp_load_reg32(TCGv_i32 var, int reg)
{
tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
tcg_gen_ld_i32(var, tcg_env, vfp_reg_offset(false, reg));
}
static inline void vfp_store_reg32(TCGv_i32 var, int reg)
{
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
tcg_gen_st_i32(var, tcg_env, vfp_reg_offset(false, reg));
}
/*
@@ -116,7 +116,7 @@ static void gen_preserve_fp_state(DisasContext *s, bool skip_context_update)
if (translator_io_start(&s->base)) {
s->base.is_jmp = DISAS_UPDATE_EXIT;
}
gen_helper_v7m_preserve_fp_state(cpu_env);
gen_helper_v7m_preserve_fp_state(tcg_env);
/*
* If the preserve_fp_state helper doesn't throw an exception
* then it will clear LSPACT; we don't need to repeat this for
@@ -172,7 +172,7 @@ static void gen_update_fp_context(DisasContext *s)
uint32_t bits = R_V7M_CONTROL_FPCA_MASK;
fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]);
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
gen_helper_vfp_set_fpscr(tcg_env, fpscr);
if (dc_isar_feature(aa32_mve, s)) {
store_cpu_field(tcg_constant_i32(0), v7m.vpr);
}
@@ -815,7 +815,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
if (s->current_el == 1) {
gen_set_condexec(s);
gen_update_pc(s, 0);
gen_helper_check_hcr_el2_trap(cpu_env,
gen_helper_check_hcr_el2_trap(tcg_env,
tcg_constant_i32(a->rt),
tcg_constant_i32(a->reg));
}
@@ -831,7 +831,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
} else {
tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env);
gen_helper_vfp_get_fpscr(tmp, tcg_env);
}
break;
default:
@@ -855,7 +855,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
break;
case ARM_VFP_FPSCR:
tmp = load_reg(s, a->rt);
gen_helper_vfp_set_fpscr(cpu_env, tmp);
gen_helper_vfp_set_fpscr(tcg_env, tmp);
gen_lookup_tb(s);
break;
case ARM_VFP_FPEXC:
@@ -1169,7 +1169,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
* value is above, it is UNKNOWN whether the limit check
* triggers; we choose to trigger.
*/
gen_helper_v8m_stackcheck(cpu_env, addr);
gen_helper_v8m_stackcheck(tcg_env, addr);
}
offset = 4;
@@ -1252,7 +1252,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
* value is above, it is UNKNOWN whether the limit check
* triggers; we choose to trigger.
*/
gen_helper_v8m_stackcheck(cpu_env, addr);
gen_helper_v8m_stackcheck(tcg_env, addr);
}
offset = 8;
@@ -2419,17 +2419,17 @@ DO_VFP_2OP(VNEG, dp, gen_helper_vfp_negd, aa32_fpdp_v2)
static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm)
{
gen_helper_vfp_sqrth(vd, vm, cpu_env);
gen_helper_vfp_sqrth(vd, vm, tcg_env);
}
static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
{
gen_helper_vfp_sqrts(vd, vm, cpu_env);
gen_helper_vfp_sqrts(vd, vm, tcg_env);
}
static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
{
gen_helper_vfp_sqrtd(vd, vm, cpu_env);
gen_helper_vfp_sqrtd(vd, vm, tcg_env);
}
DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith)
@@ -2464,9 +2464,9 @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a)
}
if (a->e) {
gen_helper_vfp_cmpeh(vd, vm, cpu_env);
gen_helper_vfp_cmpeh(vd, vm, tcg_env);
} else {
gen_helper_vfp_cmph(vd, vm, cpu_env);
gen_helper_vfp_cmph(vd, vm, tcg_env);
}
return true;
}
@@ -2499,9 +2499,9 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
}
if (a->e) {
gen_helper_vfp_cmpes(vd, vm, cpu_env);
gen_helper_vfp_cmpes(vd, vm, tcg_env);
} else {
gen_helper_vfp_cmps(vd, vm, cpu_env);
gen_helper_vfp_cmps(vd, vm, tcg_env);
}
return true;
}
@@ -2539,9 +2539,9 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
}
if (a->e) {
gen_helper_vfp_cmped(vd, vm, cpu_env);
gen_helper_vfp_cmped(vd, vm, tcg_env);
} else {
gen_helper_vfp_cmpd(vd, vm, cpu_env);
gen_helper_vfp_cmpd(vd, vm, tcg_env);
}
return true;
}
@@ -2564,7 +2564,7 @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
/* The T bit tells us if we want the low or high 16 bits of Vm */
tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
tcg_gen_ld16u_i32(tmp, tcg_env, vfp_f16_offset(a->vm, a->t));
gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
vfp_store_reg32(tmp, a->vd);
return true;
@@ -2598,7 +2598,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
/* The T bit tells us if we want the low or high 16 bits of Vm */
tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
tcg_gen_ld16u_i32(tmp, tcg_env, vfp_f16_offset(a->vm, a->t));
vd = tcg_temp_new_i64();
gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
vfp_store_reg64(vd, a->vd);
@@ -2623,7 +2623,7 @@ static bool trans_VCVT_b16_f32(DisasContext *s, arg_VCVT_b16_f32 *a)
vfp_load_reg32(tmp, a->vm);
gen_helper_bfcvt(tmp, tmp, fpst);
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t));
return true;
}
@@ -2647,7 +2647,7 @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
vfp_load_reg32(tmp, a->vm);
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t));
return true;
}
@@ -2682,7 +2682,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
vfp_load_reg64(vm, a->vm);
gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t));
return true;
}
@@ -2932,7 +2932,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
vm = tcg_temp_new_i32();
vd = tcg_temp_new_i64();
vfp_load_reg32(vm, a->vm);
gen_helper_vfp_fcvtds(vd, vm, cpu_env);
gen_helper_vfp_fcvtds(vd, vm, tcg_env);
vfp_store_reg64(vd, a->vd);
return true;
}
@@ -2958,7 +2958,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
vd = tcg_temp_new_i32();
vm = tcg_temp_new_i64();
vfp_load_reg64(vm, a->vm);
gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
gen_helper_vfp_fcvtsd(vd, vm, tcg_env);
vfp_store_reg32(vd, a->vd);
return true;
}
@@ -3076,7 +3076,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
vm = tcg_temp_new_i64();
vd = tcg_temp_new_i32();
vfp_load_reg64(vm, a->vm);
gen_helper_vjcvt(vd, vm, cpu_env);
gen_helper_vjcvt(vd, vm, tcg_env);
vfp_store_reg32(vd, a->vd);
return true;
}
target/arm/tcg/translate.c
+114 -114
View File
File diff suppressed because it is too large Load Diff
target/arm/tcg/translate.h
+8 -8
View File
@@ -329,7 +329,7 @@ static inline TCGv_i32 get_ahp_flag(void)
{
TCGv_i32 ret = tcg_temp_new_i32();
tcg_gen_ld_i32(ret, cpu_env,
tcg_gen_ld_i32(ret, tcg_env,
offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
tcg_gen_extract_i32(ret, ret, 26, 1);
@@ -343,9 +343,9 @@ static inline void set_pstate_bits(uint32_t bits)
tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
tcg_gen_ori_i32(p, p, bits);
tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
}
/* Clear bits within PSTATE. */
@@ -355,9 +355,9 @@ static inline void clear_pstate_bits(uint32_t bits)
tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
tcg_gen_andi_i32(p, p, ~bits);
tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
}
/* If the singlestep state is Active-not-pending, advance to Active-pending. */
@@ -374,7 +374,7 @@ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
{
/* Fill in the same_el field of the syndrome in the helper. */
uint32_t syn = syn_swstep(false, isv, ex);
gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn));
gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn));
}
/*
@@ -557,7 +557,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
default:
g_assert_not_reached();
}
tcg_gen_addi_ptr(statusptr, cpu_env, offset);
tcg_gen_addi_ptr(statusptr, tcg_env, offset);
return statusptr;
}
@@ -679,7 +679,7 @@ static inline void set_disas_label(DisasContext *s, DisasLabel l)
static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
{
TCGv_ptr ret = tcg_temp_new_ptr();
gen_helper_lookup_cp_reg(ret, cpu_env, tcg_constant_i32(key));
gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key));
return ret;
}
target/avr/translate.c
+32 -32
View File
@@ -127,25 +127,25 @@ void avr_cpu_tcg_init(void)
int i;
#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x)
cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc");
cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf");
cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf");
cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf");
cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf");
cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf");
cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf");
cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf");
cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If");
cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD");
cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX");
cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY");
cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ");
cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind");
cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp");
cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip");
cpu_pc = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(pc_w), "pc");
cpu_Cf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregC), "Cf");
cpu_Zf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregZ), "Zf");
cpu_Nf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregN), "Nf");
cpu_Vf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregV), "Vf");
cpu_Sf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregS), "Sf");
cpu_Hf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregH), "Hf");
cpu_Tf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregT), "Tf");
cpu_If = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregI), "If");
cpu_rampD = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampD), "rampD");
cpu_rampX = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampX), "rampX");
cpu_rampY = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampY), "rampY");
cpu_rampZ = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampZ), "rampZ");
cpu_eind = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(eind), "eind");
cpu_sp = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sp), "sp");
cpu_skip = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(skip), "skip");
for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) {
cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]),
cpu_r[i] = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(r[i]),
reg_names[i]);
}
#undef AVR_REG_OFFS
@@ -184,7 +184,7 @@ static int append_16(DisasContext *ctx, int x)
static bool avr_have_feature(DisasContext *ctx, int feature)
{
if (!avr_feature(ctx->env, feature)) {
gen_helper_unsupported(cpu_env);
gen_helper_unsupported(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return false;
}
@@ -1295,7 +1295,7 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
gen_helper_inb(data, tcg_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = data;
@@ -1313,7 +1313,7 @@ static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a)
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
gen_helper_inb(data, tcg_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_NE;
ctx->skip_var0 = data;
@@ -1494,7 +1494,7 @@ static TCGv gen_get_zaddr(void)
static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
{
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
gen_helper_fullwr(cpu_env, data, addr);
gen_helper_fullwr(tcg_env, data, addr);
} else {
tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB);
}
@@ -1503,7 +1503,7 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
{
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
gen_helper_fullrd(data, cpu_env, addr);
gen_helper_fullrd(data, tcg_env, addr);
} else {
tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB);
}
@@ -2130,7 +2130,7 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a)
TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_constant_i32(a->imm);
gen_helper_inb(Rd, cpu_env, port);
gen_helper_inb(Rd, tcg_env, port);
return true;
}
@@ -2143,7 +2143,7 @@ static bool trans_OUT(DisasContext *ctx, arg_OUT *a)
TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_constant_i32(a->imm);
gen_helper_outb(cpu_env, port, Rd);
gen_helper_outb(tcg_env, port, Rd);
return true;
}
@@ -2411,9 +2411,9 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
gen_helper_inb(data, tcg_env, port);
tcg_gen_ori_tl(data, data, 1 << a->bit);
gen_helper_outb(cpu_env, port, data);
gen_helper_outb(tcg_env, port, data);
return true;
}
@@ -2426,9 +2426,9 @@ static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port);
gen_helper_inb(data, tcg_env, port);
tcg_gen_andi_tl(data, data, ~(1 << a->bit));
gen_helper_outb(cpu_env, port, data);
gen_helper_outb(tcg_env, port, data);
return true;
}
@@ -2551,7 +2551,7 @@ static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
#ifdef BREAKPOINT_ON_BREAK
tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
gen_helper_debug(cpu_env);
gen_helper_debug(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
#else
/* NOP */
@@ -2577,7 +2577,7 @@ static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
*/
static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
{
gen_helper_sleep(cpu_env);
gen_helper_sleep(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
@@ -2589,7 +2589,7 @@ static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
*/
static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
{
gen_helper_wdr(cpu_env);
gen_helper_wdr(tcg_env);
return true;
}
@@ -2608,7 +2608,7 @@ static void translate(DisasContext *ctx)
uint32_t opcode = next_word(ctx);
if (!decode_insn(ctx, opcode)) {
gen_helper_unsupported(cpu_env);
gen_helper_unsupported(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
}
}
target/cris/translate.c
+34 -34
View File
@@ -171,9 +171,9 @@ static const int preg_sizes[] = {
};
#define t_gen_mov_TN_env(tn, member) \
tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
tcg_gen_ld_tl(tn, tcg_env, offsetof(CPUCRISState, member))
#define t_gen_mov_env_TN(member, tn) \
tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
tcg_gen_st_tl(tn, tcg_env, offsetof(CPUCRISState, member))
#define t_gen_movi_env_TN(member, c) \
t_gen_mov_env_TN(member, tcg_constant_tl(c))
@@ -197,10 +197,10 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
tcg_gen_andi_tl(cpu_PR[r], tn, 3);
} else {
if (r == PR_PID) {
gen_helper_tlb_flush_pid(cpu_env, tn);
gen_helper_tlb_flush_pid(tcg_env, tn);
}
if (dc->tb_flags & S_FLAG && r == PR_SPC) {
gen_helper_spc_write(cpu_env, tn);
gen_helper_spc_write(tcg_env, tn);
} else if (r == PR_CCS) {
dc->cpustate_changed = 1;
}
@@ -265,7 +265,7 @@ static void cris_lock_irq(DisasContext *dc)
static inline void t_gen_raise_exception(uint32_t index)
{
gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
gen_helper_raise_exception(tcg_env, tcg_constant_i32(index));
}
static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
@@ -504,17 +504,17 @@ static void cris_evaluate_flags(DisasContext *dc)
switch (dc->cc_op) {
case CC_OP_MCP:
gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_src,
cc_dest, cc_result);
break;
case CC_OP_MULS:
gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_result,
cpu_PR[PR_MOF]);
break;
case CC_OP_MULU:
gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_result,
cpu_PR[PR_MOF]);
break;
@@ -528,14 +528,14 @@ static void cris_evaluate_flags(DisasContext *dc)
switch (dc->cc_size) {
case 4:
gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
cpu_env, cpu_PR[PR_CCS], cc_result);
tcg_env, cpu_PR[PR_CCS], cc_result);
break;
case 2:
gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
cpu_env, cpu_PR[PR_CCS], cc_result);
tcg_env, cpu_PR[PR_CCS], cc_result);
break;
default:
gen_helper_evaluate_flags(cpu_env);
gen_helper_evaluate_flags(tcg_env);
break;
}
break;
@@ -545,21 +545,21 @@ static void cris_evaluate_flags(DisasContext *dc)
case CC_OP_SUB:
case CC_OP_CMP:
if (dc->cc_size == 4) {
gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
} else {
gen_helper_evaluate_flags(cpu_env);
gen_helper_evaluate_flags(tcg_env);
}
break;
default:
switch (dc->cc_size) {
case 4:
gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
break;
default:
gen_helper_evaluate_flags(cpu_env);
gen_helper_evaluate_flags(tcg_env);
break;
}
break;
@@ -1330,7 +1330,7 @@ static int dec_btstq(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZ);
c = tcg_constant_tl(dc->op1);
cris_evaluate_flags(dc);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2],
c, cpu_PR[PR_CCS]);
cris_alu(dc, CC_OP_MOVE,
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
@@ -1744,7 +1744,7 @@ static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_evaluate_flags(dc);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2],
cpu_R[dc->op1], cpu_PR[PR_CCS]);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
cpu_R[dc->op2], cpu_R[dc->op2], 4);
@@ -1946,7 +1946,7 @@ static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_sreg_reg(cpu_env, c2, c1);
gen_helper_movl_sreg_reg(tcg_env, c2, c1);
return 2;
}
static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
@@ -1956,7 +1956,7 @@ static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_reg_sreg(cpu_env, c1, c2);
gen_helper_movl_reg_sreg(tcg_env, c1, c2);
return 2;
}
@@ -2693,7 +2693,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, 0);
if (dc->op2 == 15) {
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(CRISCPU, env) + offsetof(CPUState, halted));
tcg_gen_movi_tl(env_pc, dc->pc + 2);
t_gen_raise_exception(EXCP_HLT);
@@ -2706,7 +2706,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
/* rfe. */
LOG_DIS("rfe\n");
cris_evaluate_flags(dc);
gen_helper_rfe(cpu_env);
gen_helper_rfe(tcg_env);
dc->base.is_jmp = DISAS_UPDATE;
dc->cpustate_changed = true;
break;
@@ -2714,7 +2714,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
/* rfn. */
LOG_DIS("rfn\n");
cris_evaluate_flags(dc);
gen_helper_rfn(cpu_env);
gen_helper_rfn(tcg_env);
dc->base.is_jmp = DISAS_UPDATE;
dc->cpustate_changed = true;
break;
@@ -3238,41 +3238,41 @@ void cris_initialize_tcg(void)
{
int i;
cc_x = tcg_global_mem_new(cpu_env,
cc_x = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
cc_src = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_src), "cc_src");
cc_dest = tcg_global_mem_new(cpu_env,
cc_dest = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_dest),
"cc_dest");
cc_result = tcg_global_mem_new(cpu_env,
cc_result = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_result),
"cc_result");
cc_op = tcg_global_mem_new(cpu_env,
cc_op = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_op), "cc_op");
cc_size = tcg_global_mem_new(cpu_env,
cc_size = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_size),
"cc_size");
cc_mask = tcg_global_mem_new(cpu_env,
cc_mask = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_mask),
"cc_mask");
env_pc = tcg_global_mem_new(cpu_env,
env_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pc),
"pc");
env_btarget = tcg_global_mem_new(cpu_env,
env_btarget = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btarget),
"btarget");
env_btaken = tcg_global_mem_new(cpu_env,
env_btaken = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btaken),
"btaken");
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
cpu_R[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, regs[i]),
regnames_v32[i]);
}
for (i = 0; i < 16; i++) {
cpu_PR[i] = tcg_global_mem_new(cpu_env,
cpu_PR[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pregs[i]),
pregnames_v32[i]);
}
target/cris/translate_v10.c.inc
+14 -14
View File
@@ -282,7 +282,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
} else {
/* BTST */
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->dst],
c, cpu_PR[PR_CCS]);
}
break;
@@ -696,7 +696,7 @@ static unsigned int dec10_reg(DisasContext *dc)
LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->dst],
cpu_R[dc->src], cpu_PR[PR_CCS]);
break;
case CRISV10_REG_DSTEP:
@@ -1235,41 +1235,41 @@ void cris_initialize_crisv10_tcg(void)
{
int i;
cc_x = tcg_global_mem_new(cpu_env,
cc_x = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
cc_src = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_src), "cc_src");
cc_dest = tcg_global_mem_new(cpu_env,
cc_dest = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_dest),
"cc_dest");
cc_result = tcg_global_mem_new(cpu_env,
cc_result = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_result),
"cc_result");
cc_op = tcg_global_mem_new(cpu_env,
cc_op = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_op), "cc_op");
cc_size = tcg_global_mem_new(cpu_env,
cc_size = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_size),
"cc_size");
cc_mask = tcg_global_mem_new(cpu_env,
cc_mask = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_mask),
"cc_mask");
env_pc = tcg_global_mem_new(cpu_env,
env_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pc),
"pc");
env_btarget = tcg_global_mem_new(cpu_env,
env_btarget = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btarget),
"btarget");
env_btaken = tcg_global_mem_new(cpu_env,
env_btaken = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btaken),
"btaken");
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
cpu_R[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, regs[i]),
regnames_v10[i]);
}
for (i = 0; i < 16; i++) {
cpu_PR[i] = tcg_global_mem_new(cpu_env,
cpu_PR[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pregs[i]),
pregnames_v10[i]);
}
target/hexagon/README
+5 -5
View File
@@ -86,7 +86,7 @@ tcg_funcs_generated.c.inc
const int RdN = insn->regno[0];
TCGv RsV = hex_gpr[insn->regno[1]];
TCGv RtV = hex_gpr[insn->regno[2]];
gen_helper_A2_add(RdV, cpu_env, RsV, RtV);
gen_helper_A2_add(RdV, tcg_env, RsV, RtV);
gen_log_reg_write(ctx, RdN, RdV);
}
@@ -143,7 +143,7 @@ istruction.
const intptr_t VdV_off =
ctx_future_vreg_off(ctx, VdN, 1, true);
TCGv_ptr VdV = tcg_temp_new_ptr();
tcg_gen_addi_ptr(VdV, cpu_env, VdV_off);
tcg_gen_addi_ptr(VdV, tcg_env, VdV_off);
const int VuN = insn->regno[1];
const intptr_t VuV_off =
vreg_src_off(ctx, VuN);
@@ -152,9 +152,9 @@ istruction.
const intptr_t VvV_off =
vreg_src_off(ctx, VvN);
TCGv_ptr VvV = tcg_temp_new_ptr();
tcg_gen_addi_ptr(VuV, cpu_env, VuV_off);
tcg_gen_addi_ptr(VvV, cpu_env, VvV_off);
gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV);
tcg_gen_addi_ptr(VuV, tcg_env, VuV_off);
tcg_gen_addi_ptr(VvV, tcg_env, VvV_off);
gen_helper_V6_vaddw(tcg_env, VdV, VuV, VvV);
}
Notice that we also generate a variable named <operand>_off for each operand of
target/hexagon/gen_tcg.h
+60 -60
View File
@@ -591,8 +591,8 @@
*/
#define fGEN_TCG_A5_ACS(SHORTCODE) \
do { \
gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \
gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV, \
gen_helper_vacsh_pred(PeV, tcg_env, RxxV, RssV, RttV); \
gen_helper_vacsh_val(RxxV, tcg_env, RxxV, RssV, RttV, \
tcg_constant_tl(ctx->need_commit)); \
} while (0)
@@ -614,7 +614,7 @@
#define fGEN_TCG_F2_sfrecipa(SHORTCODE) \
do { \
TCGv_i64 tmp = tcg_temp_new_i64(); \
gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \
gen_helper_sfrecipa(tmp, tcg_env, RsV, RtV); \
tcg_gen_extrh_i64_i32(RdV, tmp); \
tcg_gen_extrl_i64_i32(PeV, tmp); \
} while (0)
@@ -629,7 +629,7 @@
#define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \
do { \
TCGv_i64 tmp = tcg_temp_new_i64(); \
gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \
gen_helper_sfinvsqrta(tmp, tcg_env, RsV); \
tcg_gen_extrh_i64_i32(RdV, tmp); \
tcg_gen_extrl_i64_i32(PeV, tmp); \
} while (0)
@@ -1205,122 +1205,122 @@
/* Floating point */
#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
gen_helper_conv_sf2df(RddV, cpu_env, RsV)
gen_helper_conv_sf2df(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \
gen_helper_conv_df2sf(RdV, cpu_env, RssV)
gen_helper_conv_df2sf(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \
gen_helper_conv_uw2sf(RdV, cpu_env, RsV)
gen_helper_conv_uw2sf(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \
gen_helper_conv_uw2df(RddV, cpu_env, RsV)
gen_helper_conv_uw2df(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \
gen_helper_conv_w2sf(RdV, cpu_env, RsV)
gen_helper_conv_w2sf(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \
gen_helper_conv_w2df(RddV, cpu_env, RsV)
gen_helper_conv_w2df(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \
gen_helper_conv_ud2sf(RdV, cpu_env, RssV)
gen_helper_conv_ud2sf(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \
gen_helper_conv_ud2df(RddV, cpu_env, RssV)
gen_helper_conv_ud2df(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \
gen_helper_conv_d2sf(RdV, cpu_env, RssV)
gen_helper_conv_d2sf(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \
gen_helper_conv_d2df(RddV, cpu_env, RssV)
gen_helper_conv_d2df(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \
gen_helper_conv_sf2uw(RdV, cpu_env, RsV)
gen_helper_conv_sf2uw(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \
gen_helper_conv_sf2w(RdV, cpu_env, RsV)
gen_helper_conv_sf2w(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \
gen_helper_conv_sf2ud(RddV, cpu_env, RsV)
gen_helper_conv_sf2ud(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \
gen_helper_conv_sf2d(RddV, cpu_env, RsV)
gen_helper_conv_sf2d(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \
gen_helper_conv_df2uw(RdV, cpu_env, RssV)
gen_helper_conv_df2uw(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \
gen_helper_conv_df2w(RdV, cpu_env, RssV)
gen_helper_conv_df2w(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \
gen_helper_conv_df2ud(RddV, cpu_env, RssV)
gen_helper_conv_df2ud(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \
gen_helper_conv_df2d(RddV, cpu_env, RssV)
gen_helper_conv_df2d(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \
gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV)
gen_helper_conv_sf2uw_chop(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \
gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV)
gen_helper_conv_sf2w_chop(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \
gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV)
gen_helper_conv_sf2ud_chop(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \
gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV)
gen_helper_conv_sf2d_chop(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \
gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV)
gen_helper_conv_df2uw_chop(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \
gen_helper_conv_df2w_chop(RdV, cpu_env, RssV)
gen_helper_conv_df2w_chop(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \
gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV)
gen_helper_conv_df2ud_chop(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \
gen_helper_conv_df2d_chop(RddV, cpu_env, RssV)
gen_helper_conv_df2d_chop(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_sfadd(SHORTCODE) \
gen_helper_sfadd(RdV, cpu_env, RsV, RtV)
gen_helper_sfadd(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfsub(SHORTCODE) \
gen_helper_sfsub(RdV, cpu_env, RsV, RtV)
gen_helper_sfsub(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \
gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV)
gen_helper_sfcmpeq(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \
gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV)
gen_helper_sfcmpgt(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \
gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV)
gen_helper_sfcmpge(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \
gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV)
gen_helper_sfcmpuo(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfmax(SHORTCODE) \
gen_helper_sfmax(RdV, cpu_env, RsV, RtV)
gen_helper_sfmax(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfmin(SHORTCODE) \
gen_helper_sfmin(RdV, cpu_env, RsV, RtV)
gen_helper_sfmin(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfclass(SHORTCODE) \
do { \
TCGv imm = tcg_constant_tl(uiV); \
gen_helper_sfclass(PdV, cpu_env, RsV, imm); \
gen_helper_sfclass(PdV, tcg_env, RsV, imm); \
} while (0)
#define fGEN_TCG_F2_sffixupn(SHORTCODE) \
gen_helper_sffixupn(RdV, cpu_env, RsV, RtV)
gen_helper_sffixupn(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sffixupd(SHORTCODE) \
gen_helper_sffixupd(RdV, cpu_env, RsV, RtV)
gen_helper_sffixupd(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sffixupr(SHORTCODE) \
gen_helper_sffixupr(RdV, cpu_env, RsV)
gen_helper_sffixupr(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_dfadd(SHORTCODE) \
gen_helper_dfadd(RddV, cpu_env, RssV, RttV)
gen_helper_dfadd(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfsub(SHORTCODE) \
gen_helper_dfsub(RddV, cpu_env, RssV, RttV)
gen_helper_dfsub(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfmax(SHORTCODE) \
gen_helper_dfmax(RddV, cpu_env, RssV, RttV)
gen_helper_dfmax(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfmin(SHORTCODE) \
gen_helper_dfmin(RddV, cpu_env, RssV, RttV)
gen_helper_dfmin(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \
gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV)
gen_helper_dfcmpeq(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \
gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV)
gen_helper_dfcmpgt(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \
gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV)
gen_helper_dfcmpge(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \
gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV)
gen_helper_dfcmpuo(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfclass(SHORTCODE) \
do { \
TCGv imm = tcg_constant_tl(uiV); \
gen_helper_dfclass(PdV, cpu_env, RssV, imm); \
gen_helper_dfclass(PdV, tcg_env, RssV, imm); \
} while (0)
#define fGEN_TCG_F2_sfmpy(SHORTCODE) \
gen_helper_sfmpy(RdV, cpu_env, RsV, RtV)
gen_helper_sfmpy(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sffma(SHORTCODE) \
gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV)
gen_helper_sffma(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \
gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV)
gen_helper_sffma_sc(RxV, tcg_env, RxV, RsV, RtV, PuV)
#define fGEN_TCG_F2_sffms(SHORTCODE) \
gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV)
gen_helper_sffms(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \
gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV)
gen_helper_sffma_lib(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \
gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV)
gen_helper_sffms_lib(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \
gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV)
gen_helper_dfmpyfix(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
gen_helper_dfmpyhh(RxxV, tcg_env, RxxV, RssV, RttV)
/* Nothing to do for these in qemu, need to suppress compiler warnings */
#define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
@@ -1367,6 +1367,6 @@
uiV = uiV; \
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \
TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \
gen_helper_raise_exception(cpu_env, excp); \
gen_helper_raise_exception(tcg_env, excp); \
} while (0)
#endif

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