mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201020-1' into staging
target-arm queue:
* Fix AArch32 SMLAD incorrect setting of Q bit
* AArch32 VCVT fixed-point to float is always round-to-nearest
* strongarm: Fix 'time to transmit a char' unit comment
* Restrict APEI tables generation to the 'virt' machine
* bcm2835: minor code cleanups
* bcm2835: connect all IRQs from SYS_timer device
* correctly flush TLBs when TBI is enabled
* tests/qtest: Add npcm7xx timer test
* loads-stores.rst: add footnote that clarifies GETPC usage
* Fix reported EL for mte_check_fail
* Ignore HCR_EL2.ATA when {E2H,TGE} != 11
* microbit_i2c: Fix coredump when dump-vmstate
* nseries: Fix loading kernel image on n8x0 machines
* Implement v8.1M low-overhead-loops
# gpg: Signature made Tue 20 Oct 2020 21:10:35 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20201020-1: (29 commits)
target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
target/arm: Implement v8.1M low-overhead-loop instructions
target/arm: Implement v8.1M branch-future insns (as NOPs)
target/arm: Don't allow BLX imm for M-profile
target/arm: Make the t32 insn[25:23]=111 group non-overlapping
target/arm: Implement v8.1M conditional-select insns
target/arm: Implement v8.1M NOCP handling
decodetree: Fix codegen for non-overlapping group inside overlapping group
hw/arm/nseries: Fix loading kernel image on n8x0 machines
microbit_i2c: Fix coredump when dump-vmstate
target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
target/arm: Fix reported EL for mte_check_fail
target/arm: Remove redundant mmu_idx lookup
hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
loads-stores.rst: add footnote that clarifies GETPC usage
tests/qtest: Add npcm7xx timer test
target/arm: Use tlb_flush_page_bits_by_mmuidx*
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
+266
-9
@@ -409,12 +409,21 @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu)
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tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS);
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}
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static bool tlb_hit_page_mask_anyprot(CPUTLBEntry *tlb_entry,
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target_ulong page, target_ulong mask)
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{
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page &= mask;
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mask &= TARGET_PAGE_MASK | TLB_INVALID_MASK;
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return (page == (tlb_entry->addr_read & mask) ||
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page == (tlb_addr_write(tlb_entry) & mask) ||
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page == (tlb_entry->addr_code & mask));
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}
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static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry,
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target_ulong page)
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{
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return tlb_hit_page(tlb_entry->addr_read, page) ||
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tlb_hit_page(tlb_addr_write(tlb_entry), page) ||
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tlb_hit_page(tlb_entry->addr_code, page);
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return tlb_hit_page_mask_anyprot(tlb_entry, page, -1);
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}
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/**
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@@ -427,31 +436,45 @@ static inline bool tlb_entry_is_empty(const CPUTLBEntry *te)
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}
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/* Called with tlb_c.lock held */
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static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry,
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target_ulong page)
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static bool tlb_flush_entry_mask_locked(CPUTLBEntry *tlb_entry,
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target_ulong page,
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target_ulong mask)
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{
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if (tlb_hit_page_anyprot(tlb_entry, page)) {
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if (tlb_hit_page_mask_anyprot(tlb_entry, page, mask)) {
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memset(tlb_entry, -1, sizeof(*tlb_entry));
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return true;
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}
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return false;
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}
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static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry,
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target_ulong page)
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{
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return tlb_flush_entry_mask_locked(tlb_entry, page, -1);
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}
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/* Called with tlb_c.lock held */
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static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
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target_ulong page)
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static void tlb_flush_vtlb_page_mask_locked(CPUArchState *env, int mmu_idx,
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target_ulong page,
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target_ulong mask)
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{
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CPUTLBDesc *d = &env_tlb(env)->d[mmu_idx];
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int k;
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assert_cpu_is_self(env_cpu(env));
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for (k = 0; k < CPU_VTLB_SIZE; k++) {
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if (tlb_flush_entry_locked(&d->vtable[k], page)) {
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if (tlb_flush_entry_mask_locked(&d->vtable[k], page, mask)) {
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tlb_n_used_entries_dec(env, mmu_idx);
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}
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}
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}
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static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
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target_ulong page)
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{
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tlb_flush_vtlb_page_mask_locked(env, mmu_idx, page, -1);
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}
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static void tlb_flush_page_locked(CPUArchState *env, int midx,
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target_ulong page)
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{
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@@ -666,6 +689,240 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr)
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tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS);
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}
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static void tlb_flush_page_bits_locked(CPUArchState *env, int midx,
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target_ulong page, unsigned bits)
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{
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CPUTLBDesc *d = &env_tlb(env)->d[midx];
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CPUTLBDescFast *f = &env_tlb(env)->f[midx];
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target_ulong mask = MAKE_64BIT_MASK(0, bits);
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/*
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* If @bits is smaller than the tlb size, there may be multiple entries
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* within the TLB; otherwise all addresses that match under @mask hit
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* the same TLB entry.
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*
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* TODO: Perhaps allow bits to be a few bits less than the size.
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* For now, just flush the entire TLB.
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*/
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if (mask < f->mask) {
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tlb_debug("forcing full flush midx %d ("
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TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
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midx, page, mask);
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tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime());
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return;
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}
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/* Check if we need to flush due to large pages. */
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if ((page & d->large_page_mask) == d->large_page_addr) {
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tlb_debug("forcing full flush midx %d ("
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TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
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midx, d->large_page_addr, d->large_page_mask);
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tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime());
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return;
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}
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if (tlb_flush_entry_mask_locked(tlb_entry(env, midx, page), page, mask)) {
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tlb_n_used_entries_dec(env, midx);
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}
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tlb_flush_vtlb_page_mask_locked(env, midx, page, mask);
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}
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typedef struct {
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target_ulong addr;
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uint16_t idxmap;
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uint16_t bits;
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} TLBFlushPageBitsByMMUIdxData;
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static void
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tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu,
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TLBFlushPageBitsByMMUIdxData d)
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{
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CPUArchState *env = cpu->env_ptr;
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int mmu_idx;
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assert_cpu_is_self(cpu);
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tlb_debug("page addr:" TARGET_FMT_lx "/%u mmu_map:0x%x\n",
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d.addr, d.bits, d.idxmap);
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qemu_spin_lock(&env_tlb(env)->c.lock);
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for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
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if ((d.idxmap >> mmu_idx) & 1) {
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tlb_flush_page_bits_locked(env, mmu_idx, d.addr, d.bits);
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}
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}
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qemu_spin_unlock(&env_tlb(env)->c.lock);
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tb_flush_jmp_cache(cpu, d.addr);
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}
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static bool encode_pbm_to_runon(run_on_cpu_data *out,
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TLBFlushPageBitsByMMUIdxData d)
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{
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/* We need 6 bits to hold to hold @bits up to 63. */
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if (d.idxmap <= MAKE_64BIT_MASK(0, TARGET_PAGE_BITS - 6)) {
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*out = RUN_ON_CPU_TARGET_PTR(d.addr | (d.idxmap << 6) | d.bits);
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return true;
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}
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return false;
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}
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static TLBFlushPageBitsByMMUIdxData
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decode_runon_to_pbm(run_on_cpu_data data)
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{
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target_ulong addr_map_bits = (target_ulong) data.target_ptr;
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return (TLBFlushPageBitsByMMUIdxData){
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.addr = addr_map_bits & TARGET_PAGE_MASK,
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.idxmap = (addr_map_bits & ~TARGET_PAGE_MASK) >> 6,
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.bits = addr_map_bits & 0x3f
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};
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}
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static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState *cpu,
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run_on_cpu_data runon)
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{
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tlb_flush_page_bits_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon));
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}
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static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu,
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run_on_cpu_data data)
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{
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TLBFlushPageBitsByMMUIdxData *d = data.host_ptr;
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tlb_flush_page_bits_by_mmuidx_async_0(cpu, *d);
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g_free(d);
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}
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void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
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uint16_t idxmap, unsigned bits)
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{
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TLBFlushPageBitsByMMUIdxData d;
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run_on_cpu_data runon;
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/* If all bits are significant, this devolves to tlb_flush_page. */
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if (bits >= TARGET_LONG_BITS) {
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tlb_flush_page_by_mmuidx(cpu, addr, idxmap);
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return;
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}
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/* If no page bits are significant, this devolves to tlb_flush. */
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if (bits < TARGET_PAGE_BITS) {
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tlb_flush_by_mmuidx(cpu, idxmap);
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return;
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}
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/* This should already be page aligned */
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d.addr = addr & TARGET_PAGE_MASK;
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d.idxmap = idxmap;
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d.bits = bits;
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if (qemu_cpu_is_self(cpu)) {
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tlb_flush_page_bits_by_mmuidx_async_0(cpu, d);
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} else if (encode_pbm_to_runon(&runon, d)) {
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async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon);
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} else {
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TLBFlushPageBitsByMMUIdxData *p
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= g_new(TLBFlushPageBitsByMMUIdxData, 1);
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/* Otherwise allocate a structure, freed by the worker. */
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*p = d;
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async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_2,
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RUN_ON_CPU_HOST_PTR(p));
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}
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}
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void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu,
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target_ulong addr,
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uint16_t idxmap,
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unsigned bits)
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{
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TLBFlushPageBitsByMMUIdxData d;
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run_on_cpu_data runon;
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/* If all bits are significant, this devolves to tlb_flush_page. */
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if (bits >= TARGET_LONG_BITS) {
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tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap);
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return;
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}
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/* If no page bits are significant, this devolves to tlb_flush. */
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if (bits < TARGET_PAGE_BITS) {
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tlb_flush_by_mmuidx_all_cpus(src_cpu, idxmap);
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return;
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}
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/* This should already be page aligned */
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d.addr = addr & TARGET_PAGE_MASK;
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d.idxmap = idxmap;
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d.bits = bits;
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if (encode_pbm_to_runon(&runon, d)) {
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flush_all_helper(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon);
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} else {
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CPUState *dst_cpu;
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TLBFlushPageBitsByMMUIdxData *p;
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/* Allocate a separate data block for each destination cpu. */
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CPU_FOREACH(dst_cpu) {
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if (dst_cpu != src_cpu) {
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p = g_new(TLBFlushPageBitsByMMUIdxData, 1);
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*p = d;
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async_run_on_cpu(dst_cpu,
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tlb_flush_page_bits_by_mmuidx_async_2,
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RUN_ON_CPU_HOST_PTR(p));
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}
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}
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}
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|
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tlb_flush_page_bits_by_mmuidx_async_0(src_cpu, d);
|
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}
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|
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void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
|
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target_ulong addr,
|
||||
uint16_t idxmap,
|
||||
unsigned bits)
|
||||
{
|
||||
TLBFlushPageBitsByMMUIdxData d;
|
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run_on_cpu_data runon;
|
||||
|
||||
/* If all bits are significant, this devolves to tlb_flush_page. */
|
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if (bits >= TARGET_LONG_BITS) {
|
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tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap);
|
||||
return;
|
||||
}
|
||||
/* If no page bits are significant, this devolves to tlb_flush. */
|
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if (bits < TARGET_PAGE_BITS) {
|
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tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, idxmap);
|
||||
return;
|
||||
}
|
||||
|
||||
/* This should already be page aligned */
|
||||
d.addr = addr & TARGET_PAGE_MASK;
|
||||
d.idxmap = idxmap;
|
||||
d.bits = bits;
|
||||
|
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if (encode_pbm_to_runon(&runon, d)) {
|
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flush_all_helper(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon);
|
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async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1,
|
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runon);
|
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} else {
|
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CPUState *dst_cpu;
|
||||
TLBFlushPageBitsByMMUIdxData *p;
|
||||
|
||||
/* Allocate a separate data block for each destination cpu. */
|
||||
CPU_FOREACH(dst_cpu) {
|
||||
if (dst_cpu != src_cpu) {
|
||||
p = g_new(TLBFlushPageBitsByMMUIdxData, 1);
|
||||
*p = d;
|
||||
async_run_on_cpu(dst_cpu, tlb_flush_page_bits_by_mmuidx_async_2,
|
||||
RUN_ON_CPU_HOST_PTR(p));
|
||||
}
|
||||
}
|
||||
|
||||
p = g_new(TLBFlushPageBitsByMMUIdxData, 1);
|
||||
*p = d;
|
||||
async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async_2,
|
||||
RUN_ON_CPU_HOST_PTR(p));
|
||||
}
|
||||
}
|
||||
|
||||
/* update the TLBs so that writes to code in the virtual page 'addr'
|
||||
can be detected */
|
||||
void tlb_protect_code(ram_addr_t ram_addr)
|
||||
|
||||
@@ -43,4 +43,3 @@ CONFIG_FSL_IMX7=y
|
||||
CONFIG_FSL_IMX6UL=y
|
||||
CONFIG_SEMIHOSTING=y
|
||||
CONFIG_ALLWINNER_H3=y
|
||||
CONFIG_ACPI_APEI=y
|
||||
|
||||
@@ -93,7 +93,13 @@ guest CPU state in case of a guest CPU exception. This is passed
|
||||
to ``cpu_restore_state()``. Therefore the value should either be 0,
|
||||
to indicate that the guest CPU state is already synchronized, or
|
||||
the result of ``GETPC()`` from the top level ``HELPER(foo)``
|
||||
function, which is a return address into the generated code.
|
||||
function, which is a return address into the generated code [#gpc]_.
|
||||
|
||||
.. [#gpc] Note that ``GETPC()`` should be used with great care: calling
|
||||
it in other functions that are *not* the top level
|
||||
``HELPER(foo)`` will cause unexpected behavior. Instead, the
|
||||
value of ``GETPC()`` should be read from the helper and passed
|
||||
if needed to the functions that the helper calls.
|
||||
|
||||
Function names follow the pattern:
|
||||
|
||||
|
||||
@@ -26,6 +26,7 @@ config ARM_VIRT
|
||||
select ACPI_MEMORY_HOTPLUG
|
||||
select ACPI_HW_REDUCED
|
||||
select ACPI_NVDIMM
|
||||
select ACPI_APEI
|
||||
|
||||
config CHEETAH
|
||||
bool
|
||||
|
||||
@@ -171,8 +171,17 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
|
||||
memory_region_add_subregion(&s->peri_mr, ST_OFFSET,
|
||||
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systmr), 0));
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 0,
|
||||
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ,
|
||||
INTERRUPT_ARM_TIMER));
|
||||
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
|
||||
INTERRUPT_TIMER0));
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 1,
|
||||
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
|
||||
INTERRUPT_TIMER1));
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 2,
|
||||
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
|
||||
INTERRUPT_TIMER2));
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 3,
|
||||
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
|
||||
INTERRUPT_TIMER3));
|
||||
|
||||
/* UART0 */
|
||||
qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0));
|
||||
|
||||
@@ -1318,6 +1318,7 @@ static void n8x0_init(MachineState *machine,
|
||||
g_free(sz);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
binfo->ram_size = machine->ram_size;
|
||||
|
||||
memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE,
|
||||
machine->ram);
|
||||
|
||||
+1
-1
@@ -935,7 +935,7 @@ struct StrongARMUARTState {
|
||||
uint8_t rx_start;
|
||||
uint8_t rx_len;
|
||||
|
||||
uint64_t char_transmit_time; /* time to transmit a char in ticks*/
|
||||
uint64_t char_transmit_time; /* time to transmit a char in nanoseconds */
|
||||
bool wait_break_end;
|
||||
QEMUTimer *rx_timeout_timer;
|
||||
QEMUTimer *tx_timer;
|
||||
|
||||
@@ -83,6 +83,7 @@ static const VMStateDescription microbit_i2c_vmstate = {
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32_ARRAY(regs, MicrobitI2CState, MICROBIT_I2C_NREGS),
|
||||
VMSTATE_UINT32(read_idx, MicrobitI2CState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
@@ -18,6 +18,7 @@
|
||||
#include "migration/vmstate.h"
|
||||
#include "qemu/log.h"
|
||||
#include "qemu/module.h"
|
||||
#include "trace.h"
|
||||
|
||||
#define GPU_IRQS 64
|
||||
#define ARM_IRQS 8
|
||||
@@ -51,7 +52,6 @@ static void bcm2835_ic_update(BCM2835ICState *s)
|
||||
set = (s->gpu_irq_level & s->gpu_irq_enable)
|
||||
|| (s->arm_irq_level & s->arm_irq_enable);
|
||||
qemu_set_irq(s->irq, set);
|
||||
|
||||
}
|
||||
|
||||
static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level)
|
||||
@@ -59,6 +59,7 @@ static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level)
|
||||
BCM2835ICState *s = opaque;
|
||||
|
||||
assert(irq >= 0 && irq < 64);
|
||||
trace_bcm2835_ic_set_gpu_irq(irq, level);
|
||||
s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0);
|
||||
bcm2835_ic_update(s);
|
||||
}
|
||||
@@ -68,6 +69,7 @@ static void bcm2835_ic_set_arm_irq(void *opaque, int irq, int level)
|
||||
BCM2835ICState *s = opaque;
|
||||
|
||||
assert(irq >= 0 && irq < 8);
|
||||
trace_bcm2835_ic_set_cpu_irq(irq, level);
|
||||
s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0);
|
||||
bcm2835_ic_update(s);
|
||||
}
|
||||
|
||||
@@ -157,22 +157,22 @@ static void bcm2836_control_set_local_irq(void *opaque, int core, int local_irq,
|
||||
|
||||
static void bcm2836_control_set_local_irq0(void *opaque, int core, int level)
|
||||
{
|
||||
bcm2836_control_set_local_irq(opaque, core, 0, level);
|
||||
bcm2836_control_set_local_irq(opaque, core, IRQ_CNTPSIRQ, level);
|
||||
}
|
||||
|
||||
static void bcm2836_control_set_local_irq1(void *opaque, int core, int level)
|
||||
{
|
||||
bcm2836_control_set_local_irq(opaque, core, 1, level);
|
||||
bcm2836_control_set_local_irq(opaque, core, IRQ_CNTPNSIRQ, level);
|
||||
}
|
||||
|
||||
static void bcm2836_control_set_local_irq2(void *opaque, int core, int level)
|
||||
{
|
||||
bcm2836_control_set_local_irq(opaque, core, 2, level);
|
||||
bcm2836_control_set_local_irq(opaque, core, IRQ_CNTHPIRQ, level);
|
||||
}
|
||||
|
||||
static void bcm2836_control_set_local_irq3(void *opaque, int core, int level)
|
||||
{
|
||||
bcm2836_control_set_local_irq(opaque, core, 3, level);
|
||||
bcm2836_control_set_local_irq(opaque, core, IRQ_CNTVIRQ, level);
|
||||
}
|
||||
|
||||
static void bcm2836_control_set_gpu_irq(void *opaque, int irq, int level)
|
||||
|
||||
@@ -199,3 +199,7 @@ nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg wri
|
||||
heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u: 0x%"PRIx64
|
||||
heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u: 0x%"PRIx64
|
||||
heathrow_set_irq(int num, int level) "set_irq: num=0x%02x level=%d"
|
||||
|
||||
# bcm2835_ic.c
|
||||
bcm2835_ic_set_gpu_irq(int irq, int level) "GPU irq #%d level %d"
|
||||
bcm2835_ic_set_cpu_irq(int irq, int level) "CPU irq #%d level %d"
|
||||
|
||||
+36
-21
@@ -28,20 +28,13 @@ REG32(COMPARE1, 0x10)
|
||||
REG32(COMPARE2, 0x14)
|
||||
REG32(COMPARE3, 0x18)
|
||||
|
||||
static void bcm2835_systmr_update_irq(BCM2835SystemTimerState *s)
|
||||
static void bcm2835_systmr_timer_expire(void *opaque)
|
||||
{
|
||||
bool enable = !!s->reg.status;
|
||||
BCM2835SystemTimerCompare *tmr = opaque;
|
||||
|
||||
trace_bcm2835_systmr_irq(enable);
|
||||
qemu_set_irq(s->irq, enable);
|
||||
}
|
||||
|
||||
static void bcm2835_systmr_update_compare(BCM2835SystemTimerState *s,
|
||||
unsigned timer_index)
|
||||
{
|
||||
/* TODO fow now, since neither Linux nor U-boot use these timers. */
|
||||
qemu_log_mask(LOG_UNIMP, "COMPARE register %u not implemented\n",
|
||||
timer_index);
|
||||
trace_bcm2835_systmr_timer_expired(tmr->id);
|
||||
tmr->state->reg.ctrl_status |= 1 << tmr->id;
|
||||
qemu_set_irq(tmr->irq, 1);
|
||||
}
|
||||
|
||||
static uint64_t bcm2835_systmr_read(void *opaque, hwaddr offset,
|
||||
@@ -52,7 +45,7 @@ static uint64_t bcm2835_systmr_read(void *opaque, hwaddr offset,
|
||||
|
||||
switch (offset) {
|
||||
case A_CTRL_STATUS:
|
||||
r = s->reg.status;
|
||||
r = s->reg.ctrl_status;
|
||||
break;
|
||||
case A_COMPARE0 ... A_COMPARE3:
|
||||
r = s->reg.compare[(offset - A_COMPARE0) >> 2];
|
||||
@@ -75,19 +68,33 @@ static uint64_t bcm2835_systmr_read(void *opaque, hwaddr offset,
|
||||
}
|
||||
|
||||
static void bcm2835_systmr_write(void *opaque, hwaddr offset,
|
||||
uint64_t value, unsigned size)
|
||||
uint64_t value64, unsigned size)
|
||||
{
|
||||
BCM2835SystemTimerState *s = BCM2835_SYSTIMER(opaque);
|
||||
int index;
|
||||
uint32_t value = value64;
|
||||
uint32_t triggers_delay_us;
|
||||
uint64_t now;
|
||||
|
||||
trace_bcm2835_systmr_write(offset, value);
|
||||
switch (offset) {
|
||||
case A_CTRL_STATUS:
|
||||
s->reg.status &= ~value; /* Ack */
|
||||
bcm2835_systmr_update_irq(s);
|
||||
s->reg.ctrl_status &= ~value; /* Ack */
|
||||
for (index = 0; index < ARRAY_SIZE(s->tmr); index++) {
|
||||
if (extract32(value, index, 1)) {
|
||||
trace_bcm2835_systmr_irq_ack(index);
|
||||
qemu_set_irq(s->tmr[index].irq, 0);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case A_COMPARE0 ... A_COMPARE3:
|
||||
s->reg.compare[(offset - A_COMPARE0) >> 2] = value;
|
||||
bcm2835_systmr_update_compare(s, (offset - A_COMPARE0) >> 2);
|
||||
index = (offset - A_COMPARE0) >> 2;
|
||||
s->reg.compare[index] = value;
|
||||
now = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL);
|
||||
/* Compare lower 32-bits of the free-running counter. */
|
||||
triggers_delay_us = value - now;
|
||||
trace_bcm2835_systmr_run(index, triggers_delay_us);
|
||||
timer_mod(&s->tmr[index].timer, now + triggers_delay_us);
|
||||
break;
|
||||
case A_COUNTER_LOW:
|
||||
case A_COUNTER_HIGH:
|
||||
@@ -125,7 +132,14 @@ static void bcm2835_systmr_realize(DeviceState *dev, Error **errp)
|
||||
memory_region_init_io(&s->iomem, OBJECT(dev), &bcm2835_systmr_ops,
|
||||
s, "bcm2835-sys-timer", 0x20);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
|
||||
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
|
||||
|
||||
for (size_t i = 0; i < ARRAY_SIZE(s->tmr); i++) {
|
||||
s->tmr[i].id = i;
|
||||
s->tmr[i].state = s;
|
||||
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->tmr[i].irq);
|
||||
timer_init_us(&s->tmr[i].timer, QEMU_CLOCK_VIRTUAL,
|
||||
bcm2835_systmr_timer_expire, &s->tmr[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static const VMStateDescription bcm2835_systmr_vmstate = {
|
||||
@@ -133,8 +147,9 @@ static const VMStateDescription bcm2835_systmr_vmstate = {
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(reg.status, BCM2835SystemTimerState),
|
||||
VMSTATE_UINT32_ARRAY(reg.compare, BCM2835SystemTimerState, 4),
|
||||
VMSTATE_UINT32(reg.ctrl_status, BCM2835SystemTimerState),
|
||||
VMSTATE_UINT32_ARRAY(reg.compare, BCM2835SystemTimerState,
|
||||
BCM2835_SYSTIMER_COUNT),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
@@ -77,9 +77,11 @@ nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size
|
||||
nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32
|
||||
|
||||
# bcm2835_systmr.c
|
||||
bcm2835_systmr_irq(bool enable) "timer irq state %u"
|
||||
bcm2835_systmr_timer_expired(unsigned id) "timer #%u expired"
|
||||
bcm2835_systmr_irq_ack(unsigned id) "timer #%u acked"
|
||||
bcm2835_systmr_read(uint64_t offset, uint64_t data) "timer read: offset 0x%" PRIx64 " data 0x%" PRIx64
|
||||
bcm2835_systmr_write(uint64_t offset, uint64_t data) "timer write: offset 0x%" PRIx64 " data 0x%" PRIx64
|
||||
bcm2835_systmr_write(uint64_t offset, uint32_t data) "timer write: offset 0x%" PRIx64 " data 0x%" PRIx32
|
||||
bcm2835_systmr_run(unsigned id, uint64_t delay_us) "timer #%u expiring in %"PRIu64" us"
|
||||
|
||||
# avr_timer16.c
|
||||
avr_timer16_read(uint8_t addr, uint8_t value) "timer16 read addr:%u value:%u"
|
||||
|
||||
@@ -251,6 +251,25 @@ void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
|
||||
* depend on when the guests translation ends the TB.
|
||||
*/
|
||||
void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
|
||||
|
||||
/**
|
||||
* tlb_flush_page_bits_by_mmuidx
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
* @addr: virtual address of page to be flushed
|
||||
* @idxmap: bitmap of mmu indexes to flush
|
||||
* @bits: number of significant bits in address
|
||||
*
|
||||
* Similar to tlb_flush_page_mask, but with a bitmap of indexes.
|
||||
*/
|
||||
void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
|
||||
uint16_t idxmap, unsigned bits);
|
||||
|
||||
/* Similarly, with broadcast and syncing. */
|
||||
void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
|
||||
uint16_t idxmap, unsigned bits);
|
||||
void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
|
||||
(CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits);
|
||||
|
||||
/**
|
||||
* tlb_set_page_with_attrs:
|
||||
* @cpu: CPU to add this TLB entry for
|
||||
@@ -337,6 +356,23 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
||||
uint16_t idxmap)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
|
||||
target_ulong addr,
|
||||
uint16_t idxmap,
|
||||
unsigned bits)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
|
||||
target_ulong addr,
|
||||
uint16_t idxmap,
|
||||
unsigned bits)
|
||||
{
|
||||
}
|
||||
static inline void
|
||||
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
|
||||
uint16_t idxmap, unsigned bits)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* probe_access:
|
||||
|
||||
@@ -11,23 +11,32 @@
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/irq.h"
|
||||
#include "qemu/timer.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_BCM2835_SYSTIMER "bcm2835-sys-timer"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SystemTimerState, BCM2835_SYSTIMER)
|
||||
|
||||
#define BCM2835_SYSTIMER_COUNT 4
|
||||
|
||||
typedef struct {
|
||||
unsigned id;
|
||||
QEMUTimer timer;
|
||||
qemu_irq irq;
|
||||
BCM2835SystemTimerState *state;
|
||||
} BCM2835SystemTimerCompare;
|
||||
|
||||
struct BCM2835SystemTimerState {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
MemoryRegion iomem;
|
||||
qemu_irq irq;
|
||||
|
||||
struct {
|
||||
uint32_t status;
|
||||
uint32_t compare[4];
|
||||
uint32_t ctrl_status;
|
||||
uint32_t compare[BCM2835_SYSTIMER_COUNT];
|
||||
} reg;
|
||||
BCM2835SystemTimerCompare tmr[BCM2835_SYSTIMER_COUNT];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@@ -548,7 +548,7 @@ class Tree:
|
||||
output(ind, ' /* ',
|
||||
str_match_bits(innerbits, innermask), ' */\n')
|
||||
s.output_code(i + 4, extracted, innerbits, innermask)
|
||||
output(ind, ' return false;\n')
|
||||
output(ind, ' break;\n')
|
||||
output(ind, '}\n')
|
||||
# end Tree
|
||||
|
||||
|
||||
+27
-11
@@ -255,6 +255,15 @@ static void arm_cpu_reset(DeviceState *dev)
|
||||
uint8_t *rom;
|
||||
uint32_t vecbase;
|
||||
|
||||
if (cpu_isar_feature(aa32_lob, cpu)) {
|
||||
/*
|
||||
* LTPSIZE is constant 4 if MVE not implemented, and resets
|
||||
* to an UNKNOWN value if MVE is implemented. We choose to
|
||||
* always reset to 4.
|
||||
*/
|
||||
env->v7m.ltpsize = 4;
|
||||
}
|
||||
|
||||
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
|
||||
env->v7m.secure = true;
|
||||
} else {
|
||||
@@ -1429,17 +1438,22 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
|
||||
u = cpu->isar.mvfr0;
|
||||
u = FIELD_DP32(u, MVFR0, FPSP, 0);
|
||||
u = FIELD_DP32(u, MVFR0, FPDP, 0);
|
||||
u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
|
||||
u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
|
||||
u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
|
||||
u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
|
||||
u = FIELD_DP32(u, MVFR0, FPROUND, 0);
|
||||
if (!arm_feature(env, ARM_FEATURE_M)) {
|
||||
u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
|
||||
u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
|
||||
}
|
||||
cpu->isar.mvfr0 = u;
|
||||
|
||||
u = cpu->isar.mvfr1;
|
||||
u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
|
||||
u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
|
||||
u = FIELD_DP32(u, MVFR1, FPHP, 0);
|
||||
if (arm_feature(env, ARM_FEATURE_M)) {
|
||||
u = FIELD_DP32(u, MVFR1, FP16, 0);
|
||||
}
|
||||
cpu->isar.mvfr1 = u;
|
||||
|
||||
u = cpu->isar.mvfr2;
|
||||
@@ -1475,16 +1489,18 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
|
||||
u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
|
||||
cpu->isar.id_isar6 = u;
|
||||
|
||||
u = cpu->isar.mvfr1;
|
||||
u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
|
||||
u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
|
||||
u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
|
||||
u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
|
||||
cpu->isar.mvfr1 = u;
|
||||
if (!arm_feature(env, ARM_FEATURE_M)) {
|
||||
u = cpu->isar.mvfr1;
|
||||
u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
|
||||
u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
|
||||
u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
|
||||
u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
|
||||
cpu->isar.mvfr1 = u;
|
||||
|
||||
u = cpu->isar.mvfr2;
|
||||
u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
|
||||
cpu->isar.mvfr2 = u;
|
||||
u = cpu->isar.mvfr2;
|
||||
u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
|
||||
cpu->isar.mvfr2 = u;
|
||||
}
|
||||
}
|
||||
|
||||
if (!cpu->has_neon && !cpu->has_vfp) {
|
||||
|
||||
@@ -549,6 +549,7 @@ typedef struct CPUARMState {
|
||||
uint32_t fpdscr[M_REG_NUM_BANKS];
|
||||
uint32_t cpacr[M_REG_NUM_BANKS];
|
||||
uint32_t nsacr;
|
||||
int ltpsize;
|
||||
} v7m;
|
||||
|
||||
/* Information associated with an exception about to be taken:
|
||||
@@ -1985,6 +1986,7 @@ enum arm_features {
|
||||
ARM_FEATURE_VBAR, /* has cp15 VBAR */
|
||||
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
|
||||
ARM_FEATURE_M_MAIN, /* M profile Main Extension */
|
||||
ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
|
||||
};
|
||||
|
||||
static inline int arm_feature(CPUARMState *env, int feature)
|
||||
@@ -3472,6 +3474,12 @@ static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
|
||||
return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
|
||||
}
|
||||
|
||||
static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
|
||||
{
|
||||
/* (M-profile) low-overhead loops and branch future */
|
||||
return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
|
||||
}
|
||||
|
||||
static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
|
||||
{
|
||||
return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
|
||||
|
||||
+44
-11
@@ -50,6 +50,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
|
||||
#endif
|
||||
|
||||
static void switch_mode(CPUARMState *env, int mode);
|
||||
static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
|
||||
|
||||
static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
|
||||
{
|
||||
@@ -4457,6 +4458,33 @@ static int vae1_tlbmask(CPUARMState *env)
|
||||
}
|
||||
}
|
||||
|
||||
/* Return 56 if TBI is enabled, 64 otherwise. */
|
||||
static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
|
||||
uint64_t addr)
|
||||
{
|
||||
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
|
||||
int tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
|
||||
int select = extract64(addr, 55, 1);
|
||||
|
||||
return (tbi >> select) & 1 ? 56 : 64;
|
||||
}
|
||||
|
||||
static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
|
||||
{
|
||||
ARMMMUIdx mmu_idx;
|
||||
|
||||
/* Only the regime of the mmu_idx below is significant. */
|
||||
if (arm_is_secure_below_el3(env)) {
|
||||
mmu_idx = ARMMMUIdx_SE10_0;
|
||||
} else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
|
||||
== (HCR_E2H | HCR_TGE)) {
|
||||
mmu_idx = ARMMMUIdx_E20_0;
|
||||
} else {
|
||||
mmu_idx = ARMMMUIdx_E10_0;
|
||||
}
|
||||
return tlbbits_for_regime(env, mmu_idx, addr);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
@@ -4593,8 +4621,9 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
CPUState *cs = env_cpu(env);
|
||||
int mask = vae1_tlbmask(env);
|
||||
uint64_t pageaddr = sextract64(value << 12, 0, 56);
|
||||
int bits = vae1_tlbbits(env, pageaddr);
|
||||
|
||||
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
|
||||
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
@@ -4608,11 +4637,12 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
CPUState *cs = env_cpu(env);
|
||||
int mask = vae1_tlbmask(env);
|
||||
uint64_t pageaddr = sextract64(value << 12, 0, 56);
|
||||
int bits = vae1_tlbbits(env, pageaddr);
|
||||
|
||||
if (tlb_force_broadcast(env)) {
|
||||
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
|
||||
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
|
||||
} else {
|
||||
tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
|
||||
tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -4621,9 +4651,10 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
uint64_t pageaddr = sextract64(value << 12, 0, 56);
|
||||
int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr);
|
||||
|
||||
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
|
||||
ARMMMUIdxBit_E2);
|
||||
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
|
||||
ARMMMUIdxBit_E2, bits);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
@@ -4631,9 +4662,10 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
uint64_t pageaddr = sextract64(value << 12, 0, 56);
|
||||
int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr);
|
||||
|
||||
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
|
||||
ARMMMUIdxBit_SE3);
|
||||
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
|
||||
ARMMMUIdxBit_SE3, bits);
|
||||
}
|
||||
|
||||
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
@@ -6874,10 +6906,11 @@ static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
{
|
||||
int el = arm_current_el(env);
|
||||
|
||||
if (el < 2 &&
|
||||
arm_feature(env, ARM_FEATURE_EL2) &&
|
||||
!(arm_hcr_el2_eff(env) & HCR_ATA)) {
|
||||
return CP_ACCESS_TRAP_EL2;
|
||||
if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
|
||||
uint64_t hcr = arm_hcr_el2_eff(env);
|
||||
if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
|
||||
return CP_ACCESS_TRAP_EL2;
|
||||
}
|
||||
}
|
||||
if (el < 3 &&
|
||||
arm_feature(env, ARM_FEATURE_EL3) &&
|
||||
|
||||
@@ -213,6 +213,19 @@ DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
|
||||
DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
|
||||
DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
|
||||
|
||||
DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, ptr)
|
||||
DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, ptr)
|
||||
DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, ptr)
|
||||
DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, ptr)
|
||||
DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, ptr)
|
||||
DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, ptr)
|
||||
DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, ptr)
|
||||
DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, ptr)
|
||||
DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, ptr)
|
||||
DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, ptr)
|
||||
DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, ptr)
|
||||
DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i32)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user