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Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into staging

Browse Source 
First RISC-V PR for 8.1

* CPURISCVState related cleanup and simplification
* Refactor Zicond and reuse in XVentanaCondOps
* Fix invalid riscv,event-to-mhpmcounters entry
* Support subsets of code size reduction extension
* Fix itrigger when icount is used
* Simplification for RVH related check and code style fix
* Add signature dump function for spike to run ACT tests
* Rework MISA writing
* Fix mstatus.MPP related support
* Use check for relationship between Zdinx/Zhinx{min} and Zfinx
* Fix the H extension TVM trap
* A large collection of mstatus sum changes and cleanups
* Zero init APLIC internal state
* Implement query-cpu-definitions
* Restore the predicate() NULL check behavior
* Fix Guest Physical Address Translation
* Make sure an exception is raised if a pte is malformed
* Add Ventana's Veyron V1 CPU

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# =fVG8
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 05 May 2023 01:53:35 AM BST
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu: (89 commits)
  target/riscv: add Ventana's Veyron V1 CPU
  riscv: Make sure an exception is raised if a pte is malformed
  target/riscv: Fix Guest Physical Address Translation
  target/riscv: Restore the predicate() NULL check behavior
  target/riscv: add TYPE_RISCV_DYNAMIC_CPU
  target/riscv: add query-cpy-definitions support
  target/riscv: add CPU QOM header
  hw/intc/riscv_aplic: Zero init APLIC internal state
  target/riscv: Reorg sum check in get_physical_address
  target/riscv: Reorg access check in get_physical_address
  target/riscv: Merge checks for reserved pte flags
  target/riscv: Don't modify SUM with is_debug
  target/riscv: Suppress pte update with is_debug
  target/riscv: Move leaf pte processing out of level loop
  target/riscv: Hoist pbmte and hade out of the level loop
  target/riscv: Hoist second stage mode change to callers
  target/riscv: Check SUM in the correct register
  target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
  target/riscv: Move hstatus.spvp check to check_access_hlsv
  target/riscv: Introduce mmuidx_2stage
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2023-05-05 09:25:13 +01:00
parent f6b761bdbd e1d084a852
commit a9fe9e191b
45 changed files with 2488 additions and 1300 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+1 -1
View File
@@ -328,7 +328,7 @@ F: target/riscv/xthead*.decode
RISC-V XVentanaCondOps extension
M: Philipp Tomsich <philipp.tomsich@vrull.eu>
L: qemu-riscv@nongnu.org
S: Supported
S: Maintained
F: target/riscv/XVentanaCondOps.decode
F: target/riscv/insn_trans/trans_xventanacondops.c.inc
disas/riscv.c
+227 -1
View File
@@ -163,6 +163,13 @@ typedef enum {
rv_codec_v_i,
rv_codec_vsetvli,
rv_codec_vsetivli,
rv_codec_zcb_ext,
rv_codec_zcb_mul,
rv_codec_zcb_lb,
rv_codec_zcb_lh,
rv_codec_zcmp_cm_pushpop,
rv_codec_zcmp_cm_mv,
rv_codec_zcmt_jt,
} rv_codec;
typedef enum {
@@ -935,6 +942,26 @@ typedef enum {
rv_op_vsetvli = 766,
rv_op_vsetivli = 767,
rv_op_vsetvl = 768,
rv_op_c_zext_b = 769,
rv_op_c_sext_b = 770,
rv_op_c_zext_h = 771,
rv_op_c_sext_h = 772,
rv_op_c_zext_w = 773,
rv_op_c_not = 774,
rv_op_c_mul = 775,
rv_op_c_lbu = 776,
rv_op_c_lhu = 777,
rv_op_c_lh = 778,
rv_op_c_sb = 779,
rv_op_c_sh = 780,
rv_op_cm_push = 781,
rv_op_cm_pop = 782,
rv_op_cm_popret = 783,
rv_op_cm_popretz = 784,
rv_op_cm_mva01s = 785,
rv_op_cm_mvsa01 = 786,
rv_op_cm_jt = 787,
rv_op_cm_jalt = 788,
} rv_op;
/* structures */
@@ -958,6 +985,7 @@ typedef struct {
uint8_t rnum;
uint8_t vm;
uint32_t vzimm;
uint8_t rlist;
} rv_decode;
typedef struct {
@@ -1071,6 +1099,10 @@ static const char rv_vreg_name_sym[32][4] = {
#define rv_fmt_vd_vm "O\tDm"
#define rv_fmt_vsetvli "O\t0,1,v"
#define rv_fmt_vsetivli "O\t0,u,v"
#define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)"
#define rv_fmt_push_rlist "O\tx,-i"
#define rv_fmt_pop_rlist "O\tx,i"
#define rv_fmt_zcmt_index "O\ti"
/* pseudo-instruction constraints */
@@ -2066,7 +2098,27 @@ const rv_opcode_data opcode_data[] = {
{ "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 },
{ "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 },
{ "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 },
{ "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }
{ "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 },
{ "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
{ "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
{ "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
{ "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
{ "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
{ "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
{ "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
{ "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
{ "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
{ "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
{ "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
{ "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
{ "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 },
{ "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
{ "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 },
{ "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
{ "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
{ "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
{ "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
{ "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
};
/* CSR names */
@@ -2085,6 +2137,7 @@ static const char *csr_name(int csrno)
case 0x000a: return "vxrm";
case 0x000f: return "vcsr";
case 0x0015: return "seed";
case 0x0017: return "jvt";
case 0x0040: return "uscratch";
case 0x0041: return "uepc";
case 0x0042: return "ucause";
@@ -2307,6 +2360,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
op = rv_op_c_ld;
}
break;
case 4:
switch ((inst >> 10) & 0b111) {
case 0: op = rv_op_c_lbu; break;
case 1:
if (((inst >> 6) & 1) == 0) {
op = rv_op_c_lhu;
} else {
op = rv_op_c_lh;
}
break;
case 2: op = rv_op_c_sb; break;
case 3:
if (((inst >> 6) & 1) == 0) {
op = rv_op_c_sh;
}
break;
}
break;
case 5:
if (isa == rv128) {
op = rv_op_c_sq;
@@ -2363,6 +2434,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_c_and; break;
case 4: op = rv_op_c_subw; break;
case 5: op = rv_op_c_addw; break;
case 6: op = rv_op_c_mul; break;
case 7:
switch ((inst >> 2) & 0b111) {
case 0: op = rv_op_c_zext_b; break;
case 1: op = rv_op_c_sext_b; break;
case 2: op = rv_op_c_zext_h; break;
case 3: op = rv_op_c_sext_h; break;
case 4: op = rv_op_c_zext_w; break;
case 5: op = rv_op_c_not; break;
}
break;
}
break;
}
@@ -2418,6 +2500,46 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
op = rv_op_c_sqsp;
} else {
op = rv_op_c_fsdsp;
if (((inst >> 12) & 0b01)) {
switch ((inst >> 8) & 0b01111) {
case 8:
if (((inst >> 4) & 0b01111) >= 4) {
op = rv_op_cm_push;
}
break;
case 10:
if (((inst >> 4) & 0b01111) >= 4) {
op = rv_op_cm_pop;
}
break;
case 12:
if (((inst >> 4) & 0b01111) >= 4) {
op = rv_op_cm_popretz;
}
break;
case 14:
if (((inst >> 4) & 0b01111) >= 4) {
op = rv_op_cm_popret;
}
break;
}
} else {
switch ((inst >> 10) & 0b011) {
case 0:
if (((inst >> 2) & 0xFF) >= 32) {
op = rv_op_cm_jalt;
} else {
op = rv_op_cm_jt;
}
break;
case 3:
switch ((inst >> 5) & 0b011) {
case 1: op = rv_op_cm_mvsa01; break;
case 3: op = rv_op_cm_mva01s; break;
}
break;
}
}
}
break;
case 6: op = rv_op_c_swsp; break;
@@ -3662,6 +3784,21 @@ static uint32_t operand_crs2q(rv_inst inst)
return (inst << 59) >> 61;
}
static uint32_t calculate_xreg(uint32_t sreg)
{
return sreg < 2 ? sreg + 8 : sreg + 16;
}
static uint32_t operand_sreg1(rv_inst inst)
{
return calculate_xreg((inst << 54) >> 61);
}
static uint32_t operand_sreg2(rv_inst inst)
{
return calculate_xreg((inst << 59) >> 61);
}
static uint32_t operand_crd(rv_inst inst)
{
return (inst << 52) >> 59;
@@ -3884,6 +4021,46 @@ static uint32_t operand_vm(rv_inst inst)
return (inst << 38) >> 63;
}
static uint32_t operand_uimm_c_lb(rv_inst inst)
{
return (((inst << 58) >> 63) << 1) |
((inst << 57) >> 63);
}
static uint32_t operand_uimm_c_lh(rv_inst inst)
{
return (((inst << 58) >> 63) << 1);
}
static uint32_t operand_zcmp_spimm(rv_inst inst)
{
return ((inst << 60) >> 62) << 4;
}
static uint32_t operand_zcmp_rlist(rv_inst inst)
{
return ((inst << 56) >> 60);
}
static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
{
int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
int regs = rlist == 15 ? 13 : rlist - 3;
uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
return stack_adj_base + spimm;
}
static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
{
return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
operand_zcmp_spimm(inst));
}
static uint32_t operand_tbl_index(rv_inst inst)
{
return ((inst << 54) >> 56);
}
/* decode operands */
static void decode_inst_operands(rv_decode *dec, rv_isa isa)
@@ -4200,6 +4377,34 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
dec->imm = operand_vimm(inst);
dec->vzimm = operand_vzimm10(inst);
break;
case rv_codec_zcb_lb:
dec->rs1 = operand_crs1q(inst) + 8;
dec->rs2 = operand_crs2q(inst) + 8;
dec->imm = operand_uimm_c_lb(inst);
break;
case rv_codec_zcb_lh:
dec->rs1 = operand_crs1q(inst) + 8;
dec->rs2 = operand_crs2q(inst) + 8;
dec->imm = operand_uimm_c_lh(inst);
break;
case rv_codec_zcb_ext:
dec->rd = operand_crs1q(inst) + 8;
break;
case rv_codec_zcb_mul:
dec->rd = operand_crs1rdq(inst) + 8;
dec->rs2 = operand_crs2q(inst) + 8;
break;
case rv_codec_zcmp_cm_pushpop:
dec->imm = operand_zcmp_stack_adj(inst, isa);
dec->rlist = operand_zcmp_rlist(inst);
break;
case rv_codec_zcmp_cm_mv:
dec->rd = operand_sreg1(inst);
dec->rs2 = operand_sreg2(inst);
break;
case rv_codec_zcmt_jt:
dec->imm = operand_tbl_index(inst);
break;
};
}
@@ -4359,6 +4564,9 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
case ')':
append(buf, ")", buflen);
break;
case '-':
append(buf, "-", buflen);
break;
case 'b':
snprintf(tmp, sizeof(tmp), "%d", dec->bs);
append(buf, tmp, buflen);
@@ -4542,6 +4750,24 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
append(buf, vma, buflen);
break;
}
case 'x': {
switch (dec->rlist) {
case 4:
snprintf(tmp, sizeof(tmp), "{ra}");
break;
case 5:
snprintf(tmp, sizeof(tmp), "{ra, s0}");
break;
case 15:
snprintf(tmp, sizeof(tmp), "{ra, s0-s11}");
break;
default:
snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5);
break;
}
append(buf, tmp, buflen);
break;
}
default:
break;
}
hw/char/riscv_htif.c
+43 -1
View File
@@ -29,6 +29,8 @@
#include "chardev/char-fe.h"
#include "qemu/timer.h"
#include "qemu/error-report.h"
#include "exec/address-spaces.h"
#include "sysemu/dma.h"
#define RISCV_DEBUG_HTIF 0
#define HTIF_DEBUG(fmt, ...) \
@@ -51,7 +53,10 @@
/* PK system call number */
#define PK_SYS_WRITE 64
static uint64_t fromhost_addr, tohost_addr;
const char *sig_file;
uint8_t line_size = 16;
static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr;
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
uint64_t st_size)
@@ -68,6 +73,10 @@ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
error_report("HTIF tohost must be 8 bytes");
exit(1);
}
} else if (strcmp("begin_signature", st_name) == 0) {
begin_sig_addr = st_value;
} else if (strcmp("end_signature", st_name) == 0) {
end_sig_addr = st_value;
}
}
@@ -163,6 +172,39 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
if (payload & 0x1) {
/* exit code */
int exit_code = payload >> 1;
/*
* Dump signature data if sig_file is specified and
* begin/end_signature symbols exist.
*/
if (sig_file && begin_sig_addr && end_sig_addr) {
uint64_t sig_len = end_sig_addr - begin_sig_addr;
char *sig_data = g_malloc(sig_len);
dma_memory_read(&address_space_memory, begin_sig_addr,
sig_data, sig_len, MEMTXATTRS_UNSPECIFIED);
FILE *signature = fopen(sig_file, "w");
if (signature == NULL) {
error_report("Unable to open %s with error %s",
sig_file, strerror(errno));
exit(1);
}
for (int i = 0; i < sig_len; i += line_size) {
for (int j = line_size; j > 0; j--) {
if (i + j <= sig_len) {
fprintf(signature, "%02x",
sig_data[i + j - 1] & 0xff);
} else {
fprintf(signature, "%02x", 0);
}
}
fprintf(signature, "\n");
}
fclose(signature);
g_free(sig_data);
}
exit(exit_code);
} else {
uint64_t syscall[8];
hw/intc/riscv_aplic.c
+1 -1
View File
@@ -803,7 +803,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
aplic->state = g_new(uint32_t, aplic->num_irqs);
aplic->state = g_new0(uint32_t, aplic->num_irqs);
aplic->target = g_new0(uint32_t, aplic->num_irqs);
if (!aplic->msimode) {
for (i = 0; i < aplic->num_irqs; i++) {
hw/riscv/spike.c
+13
View File
@@ -332,6 +332,11 @@ static void spike_board_init(MachineState *machine)
htif_custom_base);
}
static void spike_set_signature(Object *obj, const char *val, Error **errp)
{
sig_file = g_strdup(val);
}
static void spike_machine_instance_init(Object *obj)
{
}
@@ -350,6 +355,14 @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
mc->numa_mem_supported = true;
mc->default_ram_id = "riscv.spike.ram";
object_class_property_add_str(oc, "signature", NULL, spike_set_signature);
object_class_property_set_description(oc, "signature",
"File to write ACT test signature");
object_class_property_add_uint8_ptr(oc, "signature-granularity",
&line_size, OBJ_PROP_FLAG_WRITE);
object_class_property_set_description(oc, "signature-granularity",
"Size of each line in ACT signature "
"file");
}
static const TypeInfo spike_machine_typeinfo = {
include/hw/char/riscv_htif.h
+3
View File
@@ -40,6 +40,9 @@ typedef struct HTIFState {
uint64_t pending_read;
} HTIFState;
extern const char *sig_file;
extern uint8_t line_size;
/* HTIF symbol callback */
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
uint64_t st_size);
qapi/machine-target.json
+4 -2
View File
@@ -324,7 +324,8 @@
'TARGET_I386',
'TARGET_S390X',
'TARGET_MIPS',
'TARGET_LOONGARCH64' ] } }
'TARGET_LOONGARCH64',
'TARGET_RISCV' ] } }
##
# @query-cpu-definitions:
@@ -341,4 +342,5 @@
'TARGET_I386',
'TARGET_S390X',
'TARGET_MIPS',
'TARGET_LOONGARCH64' ] } }
'TARGET_LOONGARCH64',
'TARGET_RISCV' ] } }
target/riscv/arch_dump.c
+4 -3
View File
@@ -1,4 +1,5 @@
/* Support for writing ELF notes for RISC-V architectures
/*
* Support for writing ELF notes for RISC-V architectures
*
* Copyright (C) 2021 Huawei Technologies Co., Ltd
*
@@ -180,8 +181,8 @@ int cpu_get_dump_info(ArchDumpInfo *info,
info->d_class = ELFCLASS32;
#endif
info->d_endian = (env->mstatus & MSTATUS_UBE) != 0
? ELFDATA2MSB : ELFDATA2LSB;
info->d_endian = (env->mstatus & MSTATUS_UBE) != 0 ?
ELFDATA2MSB : ELFDATA2LSB;
return 0;
}
target/riscv/cpu-qom.h
+71
View File
@@ -0,0 +1,71 @@
/*
* QEMU RISC-V CPU QOM header
*
* Copyright (c) 2023 Ventana Micro Systems Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef RISCV_CPU_QOM_H
#define RISCV_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_RISCV_CPU "riscv-cpu"
#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
#if defined(TARGET_RISCV32)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
#endif
typedef struct CPUArchState CPURISCVState;
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A RISCV CPU model.
*/
struct RISCVCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#endif /* RISCV_CPU_QOM_H */
target/riscv/cpu.c
+353 -218
View File
File diff suppressed because it is too large Load Diff
target/riscv/cpu.h
+56 -99
View File
@@ -28,6 +28,7 @@
#include "qemu/int128.h"
#include "cpu_bits.h"
#include "qapi/qapi-types-common.h"
#include "cpu-qom.h"
#define TCG_GUEST_DEFAULT_MO 0
@@ -37,38 +38,9 @@
*/
#define TARGET_INSN_START_EXTRA_WORDS 1
#define TYPE_RISCV_CPU "riscv-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
#if defined(TARGET_RISCV32)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
#endif
#define RV(x) ((target_ulong)1 << (x - 'A'))
/*
* Consider updating register_cpu_props() when adding
* new MISA bits here.
*/
/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
#define RVI RV('I')
#define RVE RV('E') /* E and I are mutually exclusive */
#define RVM RV('M')
@@ -81,6 +53,7 @@
#define RVU RV('U')
#define RVH RV('H')
#define RVJ RV('J')
#define RVG RV('G')
/* Privileged specification version */
@@ -99,12 +72,18 @@ enum {
TRANSLATE_G_STAGE_FAIL
};
/* Extension context status */
typedef enum {
EXT_STATUS_DISABLED = 0,
EXT_STATUS_INITIAL,
EXT_STATUS_CLEAN,
EXT_STATUS_DIRTY,
} RISCVExtStatus;
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
typedef struct CPUArchState CPURISCVState;
#if !defined(CONFIG_USER_ONLY)
#include "pmp.h"
#include "debug.h"
@@ -124,7 +103,7 @@ FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
typedef struct PMUCTRState {
/* Current value of a counter */
target_ulong mhpmcounter_val;
/* Current value of a counter in RV32*/
/* Current value of a counter in RV32 */
target_ulong mhpmcounterh_val;
/* Snapshot values of counter */
target_ulong mhpmcounter_prev;
@@ -176,6 +155,8 @@ struct CPUArchState {
/* 128-bit helpers upper part return value */
target_ulong retxh;
target_ulong jvt;
#ifdef CONFIG_USER_ONLY
uint32_t elf_flags;
#endif
@@ -183,7 +164,7 @@ struct CPUArchState {
#ifndef CONFIG_USER_ONLY
target_ulong priv;
/* This contains QEMU specific information about the virt state. */
target_ulong virt;
bool virt_enabled;
target_ulong geilen;
uint64_t resetvec;
@@ -278,8 +259,10 @@ struct CPUArchState {
target_ulong satp_hs;
uint64_t mstatus_hs;
/* Signals whether the current exception occurred with two-stage address
translation active. */
/*
* Signals whether the current exception occurred with two-stage address
* translation active.
*/
bool two_stage_lookup;
/*
* Signals whether the current exception occurred while doing two-stage
@@ -295,10 +278,10 @@ struct CPUArchState {
/* PMU counter state */
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
/* PMU event selector configured values. First three are unused*/
/* PMU event selector configured values. First three are unused */
target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
/* PMU event selector configured values for RV32*/
/* PMU event selector configured values for RV32 */
target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
target_ulong sscratch;
@@ -385,23 +368,6 @@ struct CPUArchState {
uint64_t kvm_timer_frequency;
};
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A RISCV CPU model.
*/
struct RISCVCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
/*
* map is a 16-bit bitmap: the most significant set bit in map is the maximum
* satp mode that is supported. It may be chosen by the user and must respect
@@ -418,19 +384,6 @@ typedef struct {
} RISCVSATPMap;
struct RISCVCPUConfig {
bool ext_i;
bool ext_e;
bool ext_g;
bool ext_m;
bool ext_a;
bool ext_f;
bool ext_d;
bool ext_c;
bool ext_s;
bool ext_u;
bool ext_h;
bool ext_j;
bool ext_v;
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
@@ -438,6 +391,13 @@ struct RISCVCPUConfig {
bool ext_zbkc;
bool ext_zbkx;
bool ext_zbs;
bool ext_zca;
bool ext_zcb;
bool ext_zcd;
bool ext_zce;
bool ext_zcf;
bool ext_zcmp;
bool ext_zcmt;
bool ext_zk;
bool ext_zkn;
bool ext_zknd;
@@ -521,16 +481,16 @@ struct RISCVCPUConfig {
typedef struct RISCVCPUConfig RISCVCPUConfig;
/**
/*
* RISCVCPU:
* @env: #CPURISCVState
*
* A RISCV CPU.
*/
struct ArchCPU {
/*< private >*/
/* < private > */
CPUState parent_obj;
/*< public >*/
/* < public > */
CPUNegativeOffsetState neg;
CPURISCVState env;
@@ -576,13 +536,11 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env);
target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
bool riscv_cpu_vector_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr);
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
@@ -602,7 +560,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
uint64_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
void *arg);
@@ -613,6 +572,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
target_ulong new_val,
target_ulong write_mask),
void *rmw_fn_arg);
RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
@@ -623,33 +584,29 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_PRIV_MMU_MASK 3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
FIELD(TB_FLAGS, LMUL, 3, 3)
FIELD(TB_FLAGS, SEW, 6, 3)
/* Skip MSTATUS_VS (0x600) bits */
FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
FIELD(TB_FLAGS, VILL, 12, 1)
/* Skip MSTATUS_FS (0x6000) bits */
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 15, 1)
FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
FIELD(TB_FLAGS, FS, 3, 2)
/* Vector flags */
FIELD(TB_FLAGS, VS, 5, 2)
FIELD(TB_FLAGS, LMUL, 7, 3)
FIELD(TB_FLAGS, SEW, 10, 3)
FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
FIELD(TB_FLAGS, VILL, 14, 1)
FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
FIELD(TB_FLAGS, XL, 20, 2)
FIELD(TB_FLAGS, XL, 16, 2)
/* If PointerMasking should be applied */
FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
FIELD(TB_FLAGS, VTA, 24, 1)
FIELD(TB_FLAGS, VMA, 25, 1)
FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
FIELD(TB_FLAGS, VTA, 20, 1)
FIELD(TB_FLAGS, VMA, 21, 1)
/* Native debug itrigger */
FIELD(TB_FLAGS, ITRIGGER, 26, 1)
FIELD(TB_FLAGS, ITRIGGER, 22, 1)
/* Virtual mode enabled */
FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
FIELD(TB_FLAGS, PRIV, 24, 2)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
@@ -686,7 +643,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
case PRV_U:
xl = get_field(env->mstatus, MSTATUS64_UXL);
break;
default: /* PRV_S | PRV_H */
default: /* PRV_S */
xl = get_field(env->mstatus, MSTATUS64_SXL);
break;
}
@@ -802,7 +759,7 @@ enum {
CSR_TABLE_SIZE = 0x1000
};
/**
/*
* The event id are encoded based on the encoding specified in the
* SBI specification v0.3
*/
target/riscv/cpu_bits.h
+14 -13
View File
@@ -9,6 +9,9 @@
(((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
(uint64_t)(mask)))
/* Extension context status mask */
#define EXT_STATUS_MASK 0x3ULL
/* Floating point round mode */
#define FSR_RD_SHIFT 5
#define FSR_RD (0x7 << FSR_RD_SHIFT)
@@ -319,6 +322,7 @@
#define SMSTATEEN_MAX_COUNT 4
#define SMSTATEEN0_CS (1ULL << 0)
#define SMSTATEEN0_FCSR (1ULL << 1)
#define SMSTATEEN0_JVT (1ULL << 2)
#define SMSTATEEN0_HSCONTXT (1ULL << 57)
#define SMSTATEEN0_IMSIC (1ULL << 58)
#define SMSTATEEN0_AIA (1ULL << 59)
@@ -523,6 +527,9 @@
/* Crypto Extension */
#define CSR_SEED 0x015
/* Zcmt Extension */
#define CSR_JVT 0x017
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
@@ -604,12 +611,9 @@ typedef enum {
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
#define PRV_H 2 /* Reserved */
#define PRV_RESERVED 2
#define PRV_M 3
/* Virtulisation Register Fields */
#define VIRT_ONOFF 1
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7fc00000
@@ -640,6 +644,7 @@ typedef enum {
#define PTE_SOFT 0x300 /* Reserved for Software */
#define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
#define PTE_N 0x8000000000000000ULL /* NAPOT translation */
#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */
#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
/* Page table PPN shift amount */
@@ -730,17 +735,10 @@ typedef enum RISCVException {
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
/* General PointerMasking CSR bits*/
/* General PointerMasking CSR bits */
#define PM_ENABLE 0x00000001ULL
#define PM_CURRENT 0x00000002ULL
#define PM_INSN 0x00000004ULL
#define PM_XS_MASK 0x00000003ULL
/* PointerMasking XS bits values */
#define PM_EXT_DISABLE 0x00000000ULL
#define PM_EXT_INITIAL 0x00000001ULL
#define PM_EXT_CLEAN 0x00000002ULL
#define PM_EXT_DIRTY 0x00000003ULL
/* Execution enviornment configuration bits */
#define MENVCFG_FIOM BIT(0)
@@ -780,7 +778,7 @@ typedef enum RISCVException {
#define S_OFFSET 5ULL
#define M_OFFSET 8ULL
#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
#define U_PM_INSN (PM_INSN << U_OFFSET)
@@ -898,4 +896,7 @@ typedef enum RISCVException {
#define MHPMEVENT_IDX_MASK 0xFFFFF
#define MHPMEVENT_SSCOF_RESVD 16
/* JVT CSR bits */
#define JVT_MODE 0x3F
#define JVT_BASE (~0x3F)
#endif
target/riscv/cpu_helper.c
+331 -330
View File
File diff suppressed because it is too large Load Diff
target/riscv/cpu_vendorid.h
+4
View File
@@ -3,4 +3,8 @@
#define THEAD_VENDOR_ID 0x5b7
#define VEYRON_V1_MARCHID 0x8000000000010000
#define VEYRON_V1_MIMPID 0x111
#define VEYRON_V1_MVENDORID 0x61f
#endif /* TARGET_RISCV_CPU_VENDORID_H */
target/riscv/csr.c
+191 -140
View File
File diff suppressed because it is too large Load Diff
target/riscv/debug.c
+11 -10
View File
@@ -282,8 +282,8 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,
/* validate size encoding */
size = type2_breakpoint_size(env, ctrl);
if (access_size[size] == -1) {
qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
size);
qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
"SIZE_ANY\n", size);
} else {
val |= (ctrl & TYPE2_SIZELO);
if (riscv_cpu_mxl(env) == MXL_RV64) {
@@ -411,8 +411,8 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
/* validate size encoding */
size = extract32(ctrl, 16, 4);
if (access_size[size] == -1) {
qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
size);
qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
"SIZE_ANY\n", size);
} else {
val |= (ctrl & TYPE6_SIZE);
}
@@ -515,7 +515,7 @@ itrigger_set_count(CPURISCVState *env, int index, int value)
static bool check_itrigger_priv(CPURISCVState *env, int index)
{
target_ulong tdata1 = env->tdata1[index];
if (riscv_cpu_virt_enabled(env)) {
if (env->virt_enabled) {
/* check VU/VS bit against current privilege level */
return (get_field(tdata1, ITRIGGER_VS) == env->priv) ||
(get_field(tdata1, ITRIGGER_VU) == env->priv);
@@ -696,7 +696,8 @@ target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
int trigger_type;
switch (tdata_index) {
case TDATA1:
trigger_type = extract_trigger_type(env, env->tdata1[env->trigger_cur]);
trigger_type = extract_trigger_type(env,
env->tdata1[env->trigger_cur]);
if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) {
return deposit64(env->tdata1[env->trigger_cur], 10, 14,
itrigger_get_adjust_count(env));
@@ -787,7 +788,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
/* type 2 trigger cannot be fired in VU/VS mode */
if (riscv_cpu_virt_enabled(env)) {
if (env->virt_enabled) {
return false;
}
@@ -806,7 +807,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
pc = env->tdata2[i];
if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
if (riscv_cpu_virt_enabled(env)) {
if (env->virt_enabled) {
/* check VU/VS bit against current privilege level */
if ((ctrl >> 23) & BIT(env->priv)) {
return true;
@@ -845,7 +846,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
/* type 2 trigger cannot be fired in VU/VS mode */
if (riscv_cpu_virt_enabled(env)) {
if (env->virt_enabled) {
return false;
}
@@ -880,7 +881,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
}
if ((wp->flags & flags) && (wp->vaddr == addr)) {
if (riscv_cpu_virt_enabled(env)) {
if (env->virt_enabled) {
/* check VU/VS bit against current privilege level */
if ((ctrl >> 23) & BIT(env->priv)) {
return true;
target/riscv/fpu_helper.c
+12 -12
View File
@@ -248,8 +248,8 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
float32 frs1 = check_nanbox_s(env, rs1);
float32 frs2 = check_nanbox_s(env, rs2);
return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
float32_minnum(frs1, frs2, &env->fp_status) :
float32_minimum_number(frs1, frs2, &env->fp_status));
float32_minnum(frs1, frs2, &env->fp_status) :
float32_minimum_number(frs1, frs2, &env->fp_status));
}
uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
@@ -257,8 +257,8 @@ uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
float32 frs1 = check_nanbox_s(env, rs1);
float32 frs2 = check_nanbox_s(env, rs2);
return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
float32_maxnum(frs1, frs2, &env->fp_status) :
float32_maximum_number(frs1, frs2, &env->fp_status));
float32_maxnum(frs1, frs2, &env->fp_status) :
float32_maximum_number(frs1, frs2, &env->fp_status));
}
uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
@@ -361,15 +361,15 @@ uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return env->priv_ver < PRIV_VERSION_1_11_0 ?
float64_minnum(frs1, frs2, &env->fp_status) :
float64_minimum_number(frs1, frs2, &env->fp_status);
float64_minnum(frs1, frs2, &env->fp_status) :
float64_minimum_number(frs1, frs2, &env->fp_status);
}
uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return env->priv_ver < PRIV_VERSION_1_11_0 ?
float64_maxnum(frs1, frs2, &env->fp_status) :
float64_maximum_number(frs1, frs2, &env->fp_status);
float64_maxnum(frs1, frs2, &env->fp_status) :
float64_maximum_number(frs1, frs2, &env->fp_status);
}
uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
@@ -481,8 +481,8 @@ uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
float16 frs1 = check_nanbox_h(env, rs1);
float16 frs2 = check_nanbox_h(env, rs2);
return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
float16_minnum(frs1, frs2, &env->fp_status) :
float16_minimum_number(frs1, frs2, &env->fp_status));
float16_minnum(frs1, frs2, &env->fp_status) :
float16_minimum_number(frs1, frs2, &env->fp_status));
}
uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
@@ -490,8 +490,8 @@ uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
float16 frs1 = check_nanbox_h(env, rs1);
float16 frs2 = check_nanbox_h(env, rs2);
return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
float16_maxnum(frs1, frs2, &env->fp_status) :
float16_maximum_number(frs1, frs2, &env->fp_status));
float16_maxnum(frs1, frs2, &env->fp_status) :
float16_maximum_number(frs1, frs2, &env->fp_status));
}
uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1)
target/riscv/gdbstub.c
+5 -4
View File
@@ -130,7 +130,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
{
uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
if (n < 32) {
int i;
int cnt = 0;
@@ -146,7 +146,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
{
uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
if (n < 32) {
int i;
for (i = 0; i < vlenb; i += 8) {
@@ -203,7 +203,7 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
if (n == 0) {
#ifndef CONFIG_USER_ONLY
cs->priv = ldtul_p(mem_buf) & 0x3;
if (cs->priv == PRV_H) {
if (cs->priv == PRV_RESERVED) {
cs->priv = PRV_S;
}
#endif
@@ -321,7 +321,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
}
if (env->misa_ext & RVV) {
int base_reg = cs->gdb_num_regs;
gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
riscv_gdb_set_vector,
ricsv_gen_dynamic_vector_xml(cs, base_reg),
"riscv-vector.xml", 0);
}
target/riscv/helper.h
+13 -2
View File
@@ -123,8 +123,16 @@ DEF_HELPER_1(itrigger_match, void, env)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hyp_tlb_flush, void, env)
DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)
DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl)
DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
DEF_HELPER_FLAGS_2(hyp_hlv_bu, TCG_CALL_NO_WG, tl, env, tl)
DEF_HELPER_FLAGS_2(hyp_hlv_hu, TCG_CALL_NO_WG, tl, env, tl)
DEF_HELPER_FLAGS_2(hyp_hlv_wu, TCG_CALL_NO_WG, tl, env, tl)
DEF_HELPER_FLAGS_2(hyp_hlv_d, TCG_CALL_NO_WG, tl, env, tl)
DEF_HELPER_FLAGS_2(hyp_hlvx_hu, TCG_CALL_NO_WG, tl, env, tl)
DEF_HELPER_FLAGS_2(hyp_hlvx_wu, TCG_CALL_NO_WG, tl, env, tl)
DEF_HELPER_FLAGS_3(hyp_hsv_b, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_3(hyp_hsv_h, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_3(hyp_hsv_w, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_3(hyp_hsv_d, TCG_CALL_NO_WG, void, env, tl, tl)
#endif
/* Vector functions */
@@ -1142,3 +1150,6 @@ DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
/* Zce helper */
DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32)
target/riscv/insn16.decode
+54 -8
View File
@@ -21,6 +21,8 @@
%rs1_3 7:3 !function=ex_rvc_register
%rs2_3 2:3 !function=ex_rvc_register
%rs2_5 2:5
%r1s 7:3 !function=ex_sreg_register
%r2s 2:3 !function=ex_sreg_register
# Immediates:
%imm_ci 12:s1 2:5
@@ -43,6 +45,11 @@
%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
%imm_lui 12:s1 2:5 !function=ex_shift_12
%uimm_cl_b 5:1 6:1
%uimm_cl_h 5:1 !function=ex_shift_1
%spimm 2:2 !function=ex_shift_4
%urlist 4:4
%index 2:8
# Argument sets imported from insn32.decode:
&empty !extern
@@ -53,7 +60,11 @@
&b imm rs2 rs1 !extern
&u imm rd !extern
&shift shamt rs1 rd !extern
&r2 rd rs1 !extern
&r2_s rs1 rs2 !extern
&cmpp urlist spimm
&cmjt index
# Formats 16:
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
@@ -89,6 +100,15 @@
@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
@cu ... ... ... .. ... .. &r2 rs1=%rs1_3 rd=%rs1_3
@cl_b ... . .. ... .. ... .. &i imm=%uimm_cl_b rs1=%rs1_3 rd=%rs2_3
@cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3
@cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3
@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3
@cm_pp ... ... ........ .. &cmpp %urlist %spimm
@cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s
@cm_jt ... ... ........ .. &cmjt %index
# *** RV32/64C Standard Extension (Quadrant 0) ***
{
# Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
@@ -97,23 +117,23 @@
}
{
lq 001 ... ... .. ... 00 @cl_q
fld 001 ... ... .. ... 00 @cl_d
c_fld 001 ... ... .. ... 00 @cl_d
}
lw 010 ... ... .. ... 00 @cl_w
{
sq 101 ... ... .. ... 00 @cs_q
fsd 101 ... ... .. ... 00 @cs_d
c_fsd 101 ... ... .. ... 00 @cs_d
}
sw 110 ... ... .. ... 00 @cs_w
# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
{
ld 011 ... ... .. ... 00 @cl_d
flw 011 ... ... .. ... 00 @cl_w
c_flw 011 ... ... .. ... 00 @cl_w
}
{
sd 111 ... ... .. ... 00 @cs_d
fsw 111 ... ... .. ... 00 @cs_w
c_fsw 111 ... ... .. ... 00 @cs_w
}
# *** RV32/64C Standard Extension (Quadrant 1) ***
@@ -148,7 +168,7 @@ addw 100 1 11 ... 01 ... 01 @cs_2
slli 000 . ..... ..... 10 @c_shift2
{
lq 001 ... ... .. ... 10 @c_lqsp
fld 001 . ..... ..... 10 @c_ldsp
c_fld 001 . ..... ..... 10 @c_ldsp
}
{
illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
@@ -166,7 +186,19 @@ slli 000 . ..... ..... 10 @c_shift2
}
{
sq 101 ... ... .. ... 10 @c_sqsp
fsd 101 ...... ..... 10 @c_sdsp
c_fsd 101 ...... ..... 10 @c_sdsp
# *** RV64 and RV32 Zcmp/Zcmt Extension ***
[
cm_push 101 11000 .... .. 10 @cm_pp
cm_pop 101 11010 .... .. 10 @cm_pp
cm_popret 101 11110 .... .. 10 @cm_pp
cm_popretz 101 11100 .... .. 10 @cm_pp
cm_mva01s 101 011 ... 11 ... 10 @cm_mv
cm_mvsa01 101 011 ... 01 ... 10 @cm_mv
cm_jalt 101 000 ........ 10 @cm_jt
]
}
sw 110 . ..... ..... 10 @c_swsp
@@ -174,9 +206,23 @@ sw 110 . ..... ..... 10 @c_swsp
{
c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
ld 011 . ..... ..... 10 @c_ldsp
flw 011 . ..... ..... 10 @c_lwsp
c_flw 011 . ..... ..... 10 @c_lwsp
}
{
sd 111 . ..... ..... 10 @c_sdsp
fsw 111 . ..... ..... 10 @c_swsp
c_fsw 111 . ..... ..... 10 @c_swsp
}
# *** RV64 and RV32 Zcb Extension ***
c_zext_b 100 111 ... 11 000 01 @cu
c_sext_b 100 111 ... 11 001 01 @cu
c_zext_h 100 111 ... 11 010 01 @cu
c_sext_h 100 111 ... 11 011 01 @cu
c_zext_w 100 111 ... 11 100 01 @cu
c_not 100 111 ... 11 101 01 @cu
c_mul 100 111 ... 10 ... 01 @cs_2
c_lbu 100 000 ... .. ... 00 @cl_b
c_lhu 100 001 ... 0. ... 00 @cl_h
c_lh 100 001 ... 1. ... 00 @cl_h
c_sb 100 010 ... .. ... 00 @cs_b
c_sh 100 011 ... 0. ... 00 @cs_h

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