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https://github.com/izzy2lost/xemu.git
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Merge tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* New CPU type: cortex-a710
* Implement new architectural features:
- FEAT_PACQARMA3
- FEAT_EPAC
- FEAT_Pauth2
- FEAT_FPAC
- FEAT_FPACCOMBINE
- FEAT_TIDCP1
* Xilinx Versal: Model the CFU/CFI
* Implement RMR_ELx registers
* Implement handling of HCR_EL2.TIDCP trap bit
* arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
* hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
* target/arm: Do not use gen_mte_checkN in trans_STGP
* arm64: Restore trapless ptimer access
# -----BEGIN PGP SIGNATURE-----
#
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# 17MWPoNQlq6G8tHUTPkrJjdA8XLz0iNPXe5G2kwhuM/S0Lv7ORzDc2pq4qBYLvIw
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# kh+aFEdKajPp56UseJiKBQ==
# =5Shq
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 08 Sep 2023 13:05:13 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm: (26 commits)
arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
target/arm: Enable SCTLR_EL1.TIDCP for user-only
target/arm: Implement FEAT_TIDCP1
target/arm: Implement HCR_EL2.TIDCP
target/arm: Implement cortex-a710
target/arm: Implement RMR_ELx
arm64: Restore trapless ptimer access
target/arm: Do not use gen_mte_checkN in trans_STGP
hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
hw/misc: Introduce a model of Xilinx Versal's CFU_APB
hw/misc: Introduce the Xilinx CFI interface
hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE
target/arm: Inform helpers whether a PAC instruction is 'combined'
target/arm: Implement FEAT_Pauth2
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
+10
@@ -1026,6 +1026,16 @@ S: Maintained
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F: hw/ssi/xlnx-versal-ospi.c
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F: include/hw/ssi/xlnx-versal-ospi.h
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Xilinx Versal CFI
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M: Francisco Iglesias <francisco.iglesias@amd.com>
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S: Maintained
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F: hw/misc/xlnx-cfi-if.c
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F: include/hw/misc/xlnx-cfi-if.h
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F: hw/misc/xlnx-versal-cfu.c
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F: include/hw/misc/xlnx-versal-cfu.h
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F: hw/misc/xlnx-versal-cframe-reg.c
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F: include/hw/misc/xlnx-versal-cframe-reg.h
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STM32F100
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M: Alexandre Iooss <erdnaxe@crans.org>
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L: qemu-arm@nongnu.org
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@@ -3763,6 +3763,7 @@ static void kvm_accel_instance_init(Object *obj)
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/* KVM dirty ring is by default off */
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s->kvm_dirty_ring_size = 0;
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s->kvm_dirty_ring_with_bitmap = false;
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s->kvm_eager_split_size = 0;
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s->notify_vmexit = NOTIFY_VMEXIT_OPTION_RUN;
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s->notify_window = 0;
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s->xen_version = 0;
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@@ -210,15 +210,20 @@ TCG VCPU Features
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TCG VCPU features are CPU features that are specific to TCG.
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Below is the list of TCG VCPU features and their descriptions.
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``pauth-impdef``
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When ``FEAT_Pauth`` is enabled, either the *impdef* (Implementation
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Defined) algorithm is enabled or the *architected* QARMA algorithm
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is enabled. By default the impdef algorithm is disabled, and QARMA
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is enabled.
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``pauth``
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Enable or disable ``FEAT_Pauth`` entirely.
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The architected QARMA algorithm has good cryptographic properties,
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but can be quite slow to emulate. The impdef algorithm used by QEMU
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is non-cryptographic but significantly faster.
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``pauth-impdef``
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When ``pauth`` is enabled, select the QEMU implementation defined algorithm.
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``pauth-qarma3``
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When ``pauth`` is enabled, select the architected QARMA3 algorithm.
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Without either ``pauth-impdef`` or ``pauth-qarma3`` enabled,
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the architected QARMA5 algorithm is used. The architected QARMA5
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and QARMA3 algorithms have good cryptographic properties, but can
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be quite slow to emulate. The impdef algorithm used by QEMU is
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non-cryptographic but significantly faster.
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SVE CPU Properties
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==================
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@@ -28,12 +28,15 @@ the following architecture extensions:
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- FEAT_DotProd (Advanced SIMD dot product instructions)
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- FEAT_DoubleFault (Double Fault Extension)
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- FEAT_E0PD (Preventing EL0 access to halves of address maps)
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- FEAT_EPAC (Enhanced pointer authentication)
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- FEAT_ETS (Enhanced Translation Synchronization)
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- FEAT_EVT (Enhanced Virtualization Traps)
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- FEAT_FCMA (Floating-point complex number instructions)
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- FEAT_FGT (Fine-Grained Traps)
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- FEAT_FHM (Floating-point half-precision multiplication instructions)
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- FEAT_FP16 (Half-precision floating-point data processing)
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- FEAT_FPAC (Faulting on AUT* instructions)
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- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
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- FEAT_FRINTTS (Floating-point to integer instructions)
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- FEAT_FlagM (Flag manipulation instructions v2)
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- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
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@@ -57,10 +60,14 @@ the following architecture extensions:
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- FEAT_MTE (Memory Tagging Extension)
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- FEAT_MTE2 (Memory Tagging Extension)
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- FEAT_MTE3 (MTE Asymmetric Fault Handling)
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- FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm)
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- FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm)
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- FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm)
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- FEAT_PAN (Privileged access never)
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- FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
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- FEAT_PAN3 (Support for SCTLR_ELx.EPAN)
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- FEAT_PAuth (Pointer authentication)
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- FEAT_PAuth2 (Enhacements to pointer authentication)
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- FEAT_PMULL (PMULL, PMULL2 instructions)
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- FEAT_PMUv3p1 (PMU Extensions v3.1)
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- FEAT_PMUv3p4 (PMU Extensions v3.4)
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@@ -85,6 +92,7 @@ the following architecture extensions:
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- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
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- FEAT_SPECRES (Speculation restriction instructions)
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- FEAT_SSBS (Speculative Store Bypass Safe)
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- FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality)
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- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
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- FEAT_TLBIRANGE (TLB invalidate range instructions)
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- FEAT_TTCNP (Translation table Common not private translations)
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@@ -58,6 +58,7 @@ Supported guest CPU types:
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- ``cortex-a57`` (64-bit)
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- ``cortex-a72`` (64-bit)
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- ``cortex-a76`` (64-bit)
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- ``cortex-a710`` (64-bit)
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- ``a64fx`` (64-bit)
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- ``host`` (with KVM only)
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- ``neoverse-n1`` (64-bit)
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@@ -211,6 +211,7 @@ static const char *valid_cpus[] = {
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ARM_CPU_TYPE_NAME("cortex-a55"),
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ARM_CPU_TYPE_NAME("cortex-a72"),
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ARM_CPU_TYPE_NAME("cortex-a76"),
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ARM_CPU_TYPE_NAME("cortex-a710"),
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ARM_CPU_TYPE_NAME("a64fx"),
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ARM_CPU_TYPE_NAME("neoverse-n1"),
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ARM_CPU_TYPE_NAME("neoverse-v1"),
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+154
-1
@@ -27,7 +27,7 @@
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#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
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#define GEM_REVISION 0x40070106
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#define VERSAL_NUM_PMC_APB_IRQS 3
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#define VERSAL_NUM_PMC_APB_IRQS 18
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#define NUM_OSPI_IRQ_LINES 3
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static void versal_create_apu_cpus(Versal *s)
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@@ -341,6 +341,7 @@ static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic)
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* - RTC
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* - BBRAM
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* - PMC SLCR
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* - CFRAME regs (input 3 - 17 to the orgate)
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*/
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object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate",
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&s->pmc.apb_irq_orgate, TYPE_OR_IRQ);
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@@ -570,6 +571,157 @@ static void versal_create_ospi(Versal *s, qemu_irq *pic)
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qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
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}
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static void versal_create_cfu(Versal *s, qemu_irq *pic)
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{
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SysBusDevice *sbd;
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DeviceState *dev;
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int i;
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const struct {
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uint64_t reg_base;
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uint64_t fdri_base;
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} cframe_addr[] = {
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{ MM_PMC_CFRAME0_REG, MM_PMC_CFRAME0_FDRI },
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{ MM_PMC_CFRAME1_REG, MM_PMC_CFRAME1_FDRI },
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{ MM_PMC_CFRAME2_REG, MM_PMC_CFRAME2_FDRI },
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{ MM_PMC_CFRAME3_REG, MM_PMC_CFRAME3_FDRI },
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{ MM_PMC_CFRAME4_REG, MM_PMC_CFRAME4_FDRI },
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{ MM_PMC_CFRAME5_REG, MM_PMC_CFRAME5_FDRI },
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{ MM_PMC_CFRAME6_REG, MM_PMC_CFRAME6_FDRI },
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{ MM_PMC_CFRAME7_REG, MM_PMC_CFRAME7_FDRI },
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{ MM_PMC_CFRAME8_REG, MM_PMC_CFRAME8_FDRI },
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{ MM_PMC_CFRAME9_REG, MM_PMC_CFRAME9_FDRI },
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{ MM_PMC_CFRAME10_REG, MM_PMC_CFRAME10_FDRI },
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{ MM_PMC_CFRAME11_REG, MM_PMC_CFRAME11_FDRI },
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{ MM_PMC_CFRAME12_REG, MM_PMC_CFRAME12_FDRI },
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{ MM_PMC_CFRAME13_REG, MM_PMC_CFRAME13_FDRI },
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{ MM_PMC_CFRAME14_REG, MM_PMC_CFRAME14_FDRI },
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};
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const struct {
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uint32_t blktype0_frames;
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uint32_t blktype1_frames;
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uint32_t blktype2_frames;
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uint32_t blktype3_frames;
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uint32_t blktype4_frames;
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uint32_t blktype5_frames;
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uint32_t blktype6_frames;
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} cframe_cfg[] = {
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[0] = { 34111, 3528, 12800, 11, 5, 1, 1 },
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[1] = { 38498, 3841, 15361, 13, 7, 3, 1 },
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[2] = { 38498, 3841, 15361, 13, 7, 3, 1 },
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[3] = { 38498, 3841, 15361, 13, 7, 3, 1 },
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};
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/* CFU FDRO */
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object_initialize_child(OBJECT(s), "cfu-fdro", &s->pmc.cfu_fdro,
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TYPE_XLNX_VERSAL_CFU_FDRO);
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sbd = SYS_BUS_DEVICE(&s->pmc.cfu_fdro);
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sysbus_realize(sbd, &error_fatal);
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memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_FDRO,
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sysbus_mmio_get_region(sbd, 0));
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/* CFRAME REG */
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for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
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g_autofree char *name = g_strdup_printf("cframe%d", i);
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object_initialize_child(OBJECT(s), name, &s->pmc.cframe[i],
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TYPE_XLNX_VERSAL_CFRAME_REG);
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sbd = SYS_BUS_DEVICE(&s->pmc.cframe[i]);
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dev = DEVICE(&s->pmc.cframe[i]);
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if (i < ARRAY_SIZE(cframe_cfg)) {
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object_property_set_int(OBJECT(dev), "blktype0-frames",
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cframe_cfg[i].blktype0_frames,
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&error_abort);
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object_property_set_int(OBJECT(dev), "blktype1-frames",
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cframe_cfg[i].blktype1_frames,
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&error_abort);
|
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object_property_set_int(OBJECT(dev), "blktype2-frames",
|
||||
cframe_cfg[i].blktype2_frames,
|
||||
&error_abort);
|
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object_property_set_int(OBJECT(dev), "blktype3-frames",
|
||||
cframe_cfg[i].blktype3_frames,
|
||||
&error_abort);
|
||||
object_property_set_int(OBJECT(dev), "blktype4-frames",
|
||||
cframe_cfg[i].blktype4_frames,
|
||||
&error_abort);
|
||||
object_property_set_int(OBJECT(dev), "blktype5-frames",
|
||||
cframe_cfg[i].blktype5_frames,
|
||||
&error_abort);
|
||||
object_property_set_int(OBJECT(dev), "blktype6-frames",
|
||||
cframe_cfg[i].blktype6_frames,
|
||||
&error_abort);
|
||||
}
|
||||
object_property_set_link(OBJECT(dev), "cfu-fdro",
|
||||
OBJECT(&s->pmc.cfu_fdro), &error_fatal);
|
||||
|
||||
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
|
||||
|
||||
memory_region_add_subregion(&s->mr_ps, cframe_addr[i].reg_base,
|
||||
sysbus_mmio_get_region(sbd, 0));
|
||||
memory_region_add_subregion(&s->mr_ps, cframe_addr[i].fdri_base,
|
||||
sysbus_mmio_get_region(sbd, 1));
|
||||
sysbus_connect_irq(sbd, 0,
|
||||
qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate),
|
||||
3 + i));
|
||||
}
|
||||
|
||||
/* CFRAME BCAST */
|
||||
object_initialize_child(OBJECT(s), "cframe_bcast", &s->pmc.cframe_bcast,
|
||||
TYPE_XLNX_VERSAL_CFRAME_BCAST_REG);
|
||||
|
||||
sbd = SYS_BUS_DEVICE(&s->pmc.cframe_bcast);
|
||||
dev = DEVICE(&s->pmc.cframe_bcast);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
|
||||
g_autofree char *propname = g_strdup_printf("cframe%d", i);
|
||||
object_property_set_link(OBJECT(dev), propname,
|
||||
OBJECT(&s->pmc.cframe[i]), &error_fatal);
|
||||
}
|
||||
|
||||
sysbus_realize(sbd, &error_fatal);
|
||||
|
||||
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_REG,
|
||||
sysbus_mmio_get_region(sbd, 0));
|
||||
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_FDRI,
|
||||
sysbus_mmio_get_region(sbd, 1));
|
||||
|
||||
/* CFU APB */
|
||||
object_initialize_child(OBJECT(s), "cfu-apb", &s->pmc.cfu_apb,
|
||||
TYPE_XLNX_VERSAL_CFU_APB);
|
||||
sbd = SYS_BUS_DEVICE(&s->pmc.cfu_apb);
|
||||
dev = DEVICE(&s->pmc.cfu_apb);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
|
||||
g_autofree char *propname = g_strdup_printf("cframe%d", i);
|
||||
object_property_set_link(OBJECT(dev), propname,
|
||||
OBJECT(&s->pmc.cframe[i]), &error_fatal);
|
||||
}
|
||||
|
||||
sysbus_realize(sbd, &error_fatal);
|
||||
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_APB,
|
||||
sysbus_mmio_get_region(sbd, 0));
|
||||
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM,
|
||||
sysbus_mmio_get_region(sbd, 1));
|
||||
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM_2,
|
||||
sysbus_mmio_get_region(sbd, 2));
|
||||
sysbus_connect_irq(sbd, 0, pic[VERSAL_CFU_IRQ_0]);
|
||||
|
||||
/* CFU SFR */
|
||||
object_initialize_child(OBJECT(s), "cfu-sfr", &s->pmc.cfu_sfr,
|
||||
TYPE_XLNX_VERSAL_CFU_SFR);
|
||||
|
||||
sbd = SYS_BUS_DEVICE(&s->pmc.cfu_sfr);
|
||||
|
||||
object_property_set_link(OBJECT(&s->pmc.cfu_sfr),
|
||||
"cfu", OBJECT(&s->pmc.cfu_apb), &error_abort);
|
||||
|
||||
sysbus_realize(sbd, &error_fatal);
|
||||
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_SFR,
|
||||
sysbus_mmio_get_region(sbd, 0));
|
||||
}
|
||||
|
||||
static void versal_create_crl(Versal *s, qemu_irq *pic)
|
||||
{
|
||||
SysBusDevice *sbd;
|
||||
@@ -763,6 +915,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
|
||||
versal_create_pmc_iou_slcr(s, pic);
|
||||
versal_create_ospi(s, pic);
|
||||
versal_create_crl(s, pic);
|
||||
versal_create_cfu(s, pic);
|
||||
versal_map_ddr(s);
|
||||
versal_unimp(s);
|
||||
|
||||
|
||||
@@ -330,23 +330,20 @@ static MemTxResult get_vte(GICv3ITSState *s, uint32_t vpeid, VTEntry *vte)
|
||||
if (entry_addr == -1) {
|
||||
/* No L2 table entry, i.e. no valid VTE, or a memory error */
|
||||
vte->valid = false;
|
||||
goto out;
|
||||
trace_gicv3_its_vte_read_fault(vpeid);
|
||||
return MEMTX_OK;
|
||||
}
|
||||
vteval = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, &res);
|
||||
if (res != MEMTX_OK) {
|
||||
goto out;
|
||||
trace_gicv3_its_vte_read_fault(vpeid);
|
||||
return res;
|
||||
}
|
||||
vte->valid = FIELD_EX64(vteval, VTE, VALID);
|
||||
vte->vptsize = FIELD_EX64(vteval, VTE, VPTSIZE);
|
||||
vte->vptaddr = FIELD_EX64(vteval, VTE, VPTADDR);
|
||||
vte->rdbase = FIELD_EX64(vteval, VTE, RDBASE);
|
||||
out:
|
||||
if (res != MEMTX_OK) {
|
||||
trace_gicv3_its_vte_read_fault(vpeid);
|
||||
} else {
|
||||
trace_gicv3_its_vte_read(vpeid, vte->valid, vte->vptsize,
|
||||
vte->vptaddr, vte->rdbase);
|
||||
}
|
||||
trace_gicv3_its_vte_read(vpeid, vte->valid, vte->vptsize,
|
||||
vte->vptaddr, vte->rdbase);
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
@@ -98,6 +98,9 @@ specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
|
||||
system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
|
||||
'xlnx-versal-xramc.c',
|
||||
'xlnx-versal-pmc-iou-slcr.c',
|
||||
'xlnx-versal-cfu.c',
|
||||
'xlnx-cfi-if.c',
|
||||
'xlnx-versal-cframe-reg.c',
|
||||
))
|
||||
system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
|
||||
system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
|
||||
|
||||
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Xilinx CFI interface
|
||||
*
|
||||
* Copyright (C) 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Written by Francisco Iglesias <francisco.iglesias@amd.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
#include "qemu/osdep.h"
|
||||
#include "hw/misc/xlnx-cfi-if.h"
|
||||
|
||||
void xlnx_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt)
|
||||
{
|
||||
XlnxCfiIfClass *xcic = XLNX_CFI_IF_GET_CLASS(cfi_if);
|
||||
|
||||
if (xcic->cfi_transfer_packet) {
|
||||
xcic->cfi_transfer_packet(cfi_if, pkt);
|
||||
}
|
||||
}
|
||||
|
||||
static const TypeInfo xlnx_cfi_if_info = {
|
||||
.name = TYPE_XLNX_CFI_IF,
|
||||
.parent = TYPE_INTERFACE,
|
||||
.class_size = sizeof(XlnxCfiIfClass),
|
||||
};
|
||||
|
||||
static void xlnx_cfi_if_register_types(void)
|
||||
{
|
||||
type_register_static(&xlnx_cfi_if_info);
|
||||
}
|
||||
|
||||
type_init(xlnx_cfi_if_register_types)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -32,6 +32,8 @@
|
||||
#include "hw/misc/xlnx-versal-crl.h"
|
||||
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
|
||||
#include "hw/net/xlnx-versal-canfd.h"
|
||||
#include "hw/misc/xlnx-versal-cfu.h"
|
||||
#include "hw/misc/xlnx-versal-cframe-reg.h"
|
||||
|
||||
#define TYPE_XLNX_VERSAL "xlnx-versal"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
|
||||
@@ -46,6 +48,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
|
||||
#define XLNX_VERSAL_NR_IRQS 192
|
||||
#define XLNX_VERSAL_NR_CANFD 2
|
||||
#define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000)
|
||||
#define XLNX_VERSAL_NR_CFRAME 15
|
||||
|
||||
struct Versal {
|
||||
/*< private >*/
|
||||
@@ -117,6 +120,11 @@ struct Versal {
|
||||
XlnxEFuse efuse;
|
||||
XlnxVersalEFuseCtrl efuse_ctrl;
|
||||
XlnxVersalEFuseCache efuse_cache;
|
||||
XlnxVersalCFUAPB cfu_apb;
|
||||
XlnxVersalCFUFDRO cfu_fdro;
|
||||
XlnxVersalCFUSFR cfu_sfr;
|
||||
XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME];
|
||||
XlnxVersalCFrameBcastReg cframe_bcast;
|
||||
|
||||
OrIRQState apb_irq_orgate;
|
||||
} pmc;
|
||||
@@ -147,6 +155,7 @@ struct Versal {
|
||||
#define VERSAL_GEM1_WAKE_IRQ_0 59
|
||||
#define VERSAL_ADMA_IRQ_0 60
|
||||
#define VERSAL_XRAM_IRQ_0 79
|
||||
#define VERSAL_CFU_IRQ_0 120
|
||||
#define VERSAL_PMC_APB_IRQ 121
|
||||
#define VERSAL_OSPI_IRQ 124
|
||||
#define VERSAL_SD0_IRQ_0 126
|
||||
@@ -240,6 +249,82 @@ struct Versal {
|
||||
#define MM_PMC_EFUSE_CACHE 0xf1250000
|
||||
#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
|
||||
|
||||
#define MM_PMC_CFU_APB 0xf12b0000
|
||||
#define MM_PMC_CFU_APB_SIZE 0x10000
|
||||
#define MM_PMC_CFU_STREAM 0xf12c0000
|
||||
#define MM_PMC_CFU_STREAM_SIZE 0x1000
|
||||
#define MM_PMC_CFU_SFR 0xf12c1000
|
||||
#define MM_PMC_CFU_SFR_SIZE 0x1000
|
||||
#define MM_PMC_CFU_FDRO 0xf12c2000
|
||||
#define MM_PMC_CFU_FDRO_SIZE 0x1000
|
||||
#define MM_PMC_CFU_STREAM_2 0xf1f80000
|
||||
#define MM_PMC_CFU_STREAM_2_SIZE 0x40000
|
||||
|
||||
#define MM_PMC_CFRAME0_REG 0xf12d0000
|
||||
#define MM_PMC_CFRAME0_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME0_FDRI 0xf12d1000
|
||||
#define MM_PMC_CFRAME0_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME1_REG 0xf12d2000
|
||||
#define MM_PMC_CFRAME1_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME1_FDRI 0xf12d3000
|
||||
#define MM_PMC_CFRAME1_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME2_REG 0xf12d4000
|
||||
#define MM_PMC_CFRAME2_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME2_FDRI 0xf12d5000
|
||||
#define MM_PMC_CFRAME2_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME3_REG 0xf12d6000
|
||||
#define MM_PMC_CFRAME3_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME3_FDRI 0xf12d7000
|
||||
#define MM_PMC_CFRAME3_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME4_REG 0xf12d8000
|
||||
#define MM_PMC_CFRAME4_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME4_FDRI 0xf12d9000
|
||||
#define MM_PMC_CFRAME4_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME5_REG 0xf12da000
|
||||
#define MM_PMC_CFRAME5_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME5_FDRI 0xf12db000
|
||||
#define MM_PMC_CFRAME5_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME6_REG 0xf12dc000
|
||||
#define MM_PMC_CFRAME6_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME6_FDRI 0xf12dd000
|
||||
#define MM_PMC_CFRAME6_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME7_REG 0xf12de000
|
||||
#define MM_PMC_CFRAME7_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME7_FDRI 0xf12df000
|
||||
#define MM_PMC_CFRAME7_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME8_REG 0xf12e0000
|
||||
#define MM_PMC_CFRAME8_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME8_FDRI 0xf12e1000
|
||||
#define MM_PMC_CFRAME8_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME9_REG 0xf12e2000
|
||||
#define MM_PMC_CFRAME9_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME9_FDRI 0xf12e3000
|
||||
#define MM_PMC_CFRAME9_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME10_REG 0xf12e4000
|
||||
#define MM_PMC_CFRAME10_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME10_FDRI 0xf12e5000
|
||||
#define MM_PMC_CFRAME10_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME11_REG 0xf12e6000
|
||||
#define MM_PMC_CFRAME11_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME11_FDRI 0xf12e7000
|
||||
#define MM_PMC_CFRAME11_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME12_REG 0xf12e8000
|
||||
#define MM_PMC_CFRAME12_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME12_FDRI 0xf12e9000
|
||||
#define MM_PMC_CFRAME12_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME13_REG 0xf12ea000
|
||||
#define MM_PMC_CFRAME13_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME13_FDRI 0xf12eb000
|
||||
#define MM_PMC_CFRAME13_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME14_REG 0xf12ec000
|
||||
#define MM_PMC_CFRAME14_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME14_FDRI 0xf12ed000
|
||||
#define MM_PMC_CFRAME14_FDRI_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME_BCAST_REG 0xf12ee000
|
||||
#define MM_PMC_CFRAME_BCAST_REG_SIZE 0x1000
|
||||
#define MM_PMC_CFRAME_BCAST_FDRI 0xf12ef000
|
||||
#define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000
|
||||
|
||||
#define MM_PMC_CRP 0xf1260000U
|
||||
#define MM_PMC_CRP_SIZE 0x10000
|
||||
#define MM_PMC_RTC 0xf12a0000
|
||||
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Xilinx CFI interface
|
||||
*
|
||||
* Copyright (C) 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Written by Francisco Iglesias <francisco.iglesias@amd.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
#ifndef XLNX_CFI_IF_H
|
||||
#define XLNX_CFI_IF_H 1
|
||||
|
||||
#include "qemu/help-texts.h"
|
||||
#include "hw/hw.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_XLNX_CFI_IF "xlnx-cfi-if"
|
||||
typedef struct XlnxCfiIfClass XlnxCfiIfClass;
|
||||
DECLARE_CLASS_CHECKERS(XlnxCfiIfClass, XLNX_CFI_IF, TYPE_XLNX_CFI_IF)
|
||||
|
||||
#define XLNX_CFI_IF(obj) \
|
||||
INTERFACE_CHECK(XlnxCfiIf, (obj), TYPE_XLNX_CFI_IF)
|
||||
|
||||
typedef enum {
|
||||
PACKET_TYPE_CFU = 0x52,
|
||||
PACKET_TYPE_CFRAME = 0xA1,
|
||||
} xlnx_cfi_packet_type;
|
||||
|
||||
typedef enum {
|
||||
CFRAME_FAR = 1,
|
||||
CFRAME_SFR = 2,
|
||||
CFRAME_FDRI = 4,
|
||||
CFRAME_CMD = 6,
|
||||
} xlnx_cfi_reg_addr;
|
||||
|
||||
typedef struct XlnxCfiPacket {
|
||||
uint8_t reg_addr;
|
||||
uint32_t data[4];
|
||||
} XlnxCfiPacket;
|
||||
|
||||
typedef struct XlnxCfiIf {
|
||||
Object Parent;
|
||||
} XlnxCfiIf;
|
||||
|
||||
typedef struct XlnxCfiIfClass {
|
||||
InterfaceClass parent;
|
||||
|
||||
void (*cfi_transfer_packet)(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt);
|
||||
} XlnxCfiIfClass;
|
||||
|
||||
/**
|
||||
* Transfer a XlnxCfiPacket.
|
||||
*
|
||||
* @cfi_if: the object implementing this interface
|
||||
* @XlnxCfiPacket: a pointer to the XlnxCfiPacket to transfer
|
||||
*/
|
||||
void xlnx_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt);
|
||||
|
||||
#endif /* XLNX_CFI_IF_H */
|
||||
@@ -0,0 +1,303 @@
|
||||
/*
|
||||
* QEMU model of the Configuration Frame Control module
|
||||
*
|
||||
* Copyright (C) 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Written by Francisco Iglesias <francisco.iglesias@amd.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* References:
|
||||
* [1] Versal ACAP Technical Reference Manual,
|
||||
* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
|
||||
*
|
||||
* [2] Versal ACAP Register Reference,
|
||||
* https://www.xilinx.com/htmldocs/registers/am012/am012-versal-register-reference.html
|
||||
*/
|
||||
#ifndef HW_MISC_XLNX_VERSAL_CFRAME_REG_H
|
||||
#define HW_MISC_XLNX_VERSAL_CFRAME_REG_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/register.h"
|
||||
#include "hw/misc/xlnx-cfi-if.h"
|
||||
#include "hw/misc/xlnx-versal-cfu.h"
|
||||
#include "qemu/fifo32.h"
|
||||
|
||||
#define TYPE_XLNX_VERSAL_CFRAME_REG "xlnx,cframe-reg"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameReg, XLNX_VERSAL_CFRAME_REG)
|
||||
|
||||
#define TYPE_XLNX_VERSAL_CFRAME_BCAST_REG "xlnx.cframe-bcast-reg"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameBcastReg,
|
||||
XLNX_VERSAL_CFRAME_BCAST_REG)
|
||||
|
||||
/*
|
||||
* The registers in this module are 128 bits wide but it is ok to write
|
||||
* and read them through 4 sequential 32 bit accesses (address[3:2] = 0,
|
||||
* 1, 2, 3).
|
||||
*/
|
||||
REG32(CRC0, 0x0)
|
||||
FIELD(CRC, CRC, 0, 32)
|
||||
REG32(CRC1, 0x4)
|
||||
REG32(CRC2, 0x8)
|
||||
REG32(CRC3, 0xc)
|
||||
REG32(FAR0, 0x10)
|
||||
FIELD(FAR0, SEGMENT, 23, 2)
|
||||
FIELD(FAR0, BLOCKTYPE, 20, 3)
|
||||
FIELD(FAR0, FRAME_ADDR, 0, 20)
|
||||
REG32(FAR1, 0x14)
|
||||
REG32(FAR2, 0x18)
|
||||
REG32(FAR3, 0x1c)
|
||||
REG32(FAR_SFR0, 0x20)
|
||||
FIELD(FAR_SFR0, BLOCKTYPE, 20, 3)
|
||||
FIELD(FAR_SFR0, FRAME_ADDR, 0, 20)
|
||||
REG32(FAR_SFR1, 0x24)
|
||||
REG32(FAR_SFR2, 0x28)
|
||||
REG32(FAR_SFR3, 0x2c)
|
||||
REG32(FDRI0, 0x40)
|
||||
REG32(FDRI1, 0x44)
|
||||
REG32(FDRI2, 0x48)
|
||||
REG32(FDRI3, 0x4c)
|
||||
REG32(FRCNT0, 0x50)
|
||||
FIELD(FRCNT0, FRCNT, 0, 32)
|
||||
REG32(FRCNT1, 0x54)
|
||||
REG32(FRCNT2, 0x58)
|
||||
REG32(FRCNT3, 0x5c)
|
||||
REG32(CMD0, 0x60)
|
||||
FIELD(CMD0, CMD, 0, 5)
|
||||
REG32(CMD1, 0x64)
|
||||
REG32(CMD2, 0x68)
|
||||
REG32(CMD3, 0x6c)
|
||||
REG32(CR_MASK0, 0x70)
|
||||
REG32(CR_MASK1, 0x74)
|
||||
REG32(CR_MASK2, 0x78)
|
||||
REG32(CR_MASK3, 0x7c)
|
||||
REG32(CTL0, 0x80)
|
||||
FIELD(CTL, PER_FRAME_CRC, 0, 1)
|
||||
REG32(CTL1, 0x84)
|
||||
REG32(CTL2, 0x88)
|
||||
REG32(CTL3, 0x8c)
|
||||
REG32(CFRM_ISR0, 0x150)
|
||||
FIELD(CFRM_ISR0, READ_BROADCAST_ERROR, 21, 1)
|
||||
FIELD(CFRM_ISR0, CMD_MISSING_ERROR, 20, 1)
|
||||
FIELD(CFRM_ISR0, RW_ROWOFF_ERROR, 19, 1)
|
||||
FIELD(CFRM_ISR0, READ_REG_ADDR_ERROR, 18, 1)
|
||||
FIELD(CFRM_ISR0, READ_BLK_TYPE_ERROR, 17, 1)
|
||||
FIELD(CFRM_ISR0, READ_FRAME_ADDR_ERROR, 16, 1)
|
||||
FIELD(CFRM_ISR0, WRITE_REG_ADDR_ERROR, 15, 1)
|
||||
FIELD(CFRM_ISR0, WRITE_BLK_TYPE_ERROR, 13, 1)
|
||||
FIELD(CFRM_ISR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
|
||||
FIELD(CFRM_ISR0, MFW_OVERRUN_ERROR, 11, 1)
|
||||
FIELD(CFRM_ISR0, FAR_FIFO_UNDERFLOW, 10, 1)
|
||||
FIELD(CFRM_ISR0, FAR_FIFO_OVERFLOW, 9, 1)
|
||||
FIELD(CFRM_ISR0, PER_FRAME_SEQ_ERROR, 8, 1)
|
||||
FIELD(CFRM_ISR0, CRC_ERROR, 7, 1)
|
||||
FIELD(CFRM_ISR0, WRITE_OVERRUN_ERROR, 6, 1)
|
||||
FIELD(CFRM_ISR0, READ_OVERRUN_ERROR, 5, 1)
|
||||
FIELD(CFRM_ISR0, CMD_INTERRUPT_ERROR, 4, 1)
|
||||
FIELD(CFRM_ISR0, WRITE_INTERRUPT_ERROR, 3, 1)
|
||||
FIELD(CFRM_ISR0, READ_INTERRUPT_ERROR, 2, 1)
|
||||
FIELD(CFRM_ISR0, SEU_CRC_ERROR, 1, 1)
|
||||
FIELD(CFRM_ISR0, SEU_ECC_ERROR, 0, 1)
|
||||
REG32(CFRM_ISR1, 0x154)
|
||||
REG32(CFRM_ISR2, 0x158)
|
||||
REG32(CFRM_ISR3, 0x15c)
|
||||
REG32(CFRM_IMR0, 0x160)
|
||||
FIELD(CFRM_IMR0, READ_BROADCAST_ERROR, 21, 1)
|
||||
FIELD(CFRM_IMR0, CMD_MISSING_ERROR, 20, 1)
|
||||
FIELD(CFRM_IMR0, RW_ROWOFF_ERROR, 19, 1)
|
||||
FIELD(CFRM_IMR0, READ_REG_ADDR_ERROR, 18, 1)
|
||||
FIELD(CFRM_IMR0, READ_BLK_TYPE_ERROR, 17, 1)
|
||||
FIELD(CFRM_IMR0, READ_FRAME_ADDR_ERROR, 16, 1)
|
||||
FIELD(CFRM_IMR0, WRITE_REG_ADDR_ERROR, 15, 1)
|
||||
FIELD(CFRM_IMR0, WRITE_BLK_TYPE_ERROR, 13, 1)
|
||||
FIELD(CFRM_IMR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
|
||||
FIELD(CFRM_IMR0, MFW_OVERRUN_ERROR, 11, 1)
|
||||
FIELD(CFRM_IMR0, FAR_FIFO_UNDERFLOW, 10, 1)
|
||||
FIELD(CFRM_IMR0, FAR_FIFO_OVERFLOW, 9, 1)
|
||||
FIELD(CFRM_IMR0, PER_FRAME_SEQ_ERROR, 8, 1)
|
||||
FIELD(CFRM_IMR0, CRC_ERROR, 7, 1)
|
||||
FIELD(CFRM_IMR0, WRITE_OVERRUN_ERROR, 6, 1)
|
||||
FIELD(CFRM_IMR0, READ_OVERRUN_ERROR, 5, 1)
|
||||
FIELD(CFRM_IMR0, CMD_INTERRUPT_ERROR, 4, 1)
|
||||
FIELD(CFRM_IMR0, WRITE_INTERRUPT_ERROR, 3, 1)
|
||||
FIELD(CFRM_IMR0, READ_INTERRUPT_ERROR, 2, 1)
|
||||
FIELD(CFRM_IMR0, SEU_CRC_ERROR, 1, 1)
|
||||
FIELD(CFRM_IMR0, SEU_ECC_ERROR, 0, 1)
|
||||
REG32(CFRM_IMR1, 0x164)
|
||||
REG32(CFRM_IMR2, 0x168)
|
||||
REG32(CFRM_IMR3, 0x16c)
|
||||
REG32(CFRM_IER0, 0x170)
|
||||
FIELD(CFRM_IER0, READ_BROADCAST_ERROR, 21, 1)
|
||||
FIELD(CFRM_IER0, CMD_MISSING_ERROR, 20, 1)
|
||||
FIELD(CFRM_IER0, RW_ROWOFF_ERROR, 19, 1)
|
||||
FIELD(CFRM_IER0, READ_REG_ADDR_ERROR, 18, 1)
|
||||
FIELD(CFRM_IER0, READ_BLK_TYPE_ERROR, 17, 1)
|
||||
FIELD(CFRM_IER0, READ_FRAME_ADDR_ERROR, 16, 1)
|
||||
FIELD(CFRM_IER0, WRITE_REG_ADDR_ERROR, 15, 1)
|
||||
FIELD(CFRM_IER0, WRITE_BLK_TYPE_ERROR, 13, 1)
|
||||
FIELD(CFRM_IER0, WRITE_FRAME_ADDR_ERROR, 12, 1)
|
||||
FIELD(CFRM_IER0, MFW_OVERRUN_ERROR, 11, 1)
|
||||
FIELD(CFRM_IER0, FAR_FIFO_UNDERFLOW, 10, 1)
|
||||
FIELD(CFRM_IER0, FAR_FIFO_OVERFLOW, 9, 1)
|
||||
FIELD(CFRM_IER0, PER_FRAME_SEQ_ERROR, 8, 1)
|
||||
FIELD(CFRM_IER0, CRC_ERROR, 7, 1)
|
||||
FIELD(CFRM_IER0, WRITE_OVERRUN_ERROR, 6, 1)
|
||||
FIELD(CFRM_IER0, READ_OVERRUN_ERROR, 5, 1)
|
||||
FIELD(CFRM_IER0, CMD_INTERRUPT_ERROR, 4, 1)
|
||||
FIELD(CFRM_IER0, WRITE_INTERRUPT_ERROR, 3, 1)
|
||||
FIELD(CFRM_IER0, READ_INTERRUPT_ERROR, 2, 1)
|
||||
FIELD(CFRM_IER0, SEU_CRC_ERROR, 1, 1)
|
||||
FIELD(CFRM_IER0, SEU_ECC_ERROR, 0, 1)
|
||||
REG32(CFRM_IER1, 0x174)
|
||||
REG32(CFRM_IER2, 0x178)
|
||||
REG32(CFRM_IER3, 0x17c)
|
||||
REG32(CFRM_IDR0, 0x180)
|
||||
FIELD(CFRM_IDR0, READ_BROADCAST_ERROR, 21, 1)
|
||||
FIELD(CFRM_IDR0, CMD_MISSING_ERROR, 20, 1)
|
||||
FIELD(CFRM_IDR0, RW_ROWOFF_ERROR, 19, 1)
|
||||
FIELD(CFRM_IDR0, READ_REG_ADDR_ERROR, 18, 1)
|
||||
FIELD(CFRM_IDR0, READ_BLK_TYPE_ERROR, 17, 1)
|
||||
FIELD(CFRM_IDR0, READ_FRAME_ADDR_ERROR, 16, 1)
|
||||
FIELD(CFRM_IDR0, WRITE_REG_ADDR_ERROR, 15, 1)
|
||||
FIELD(CFRM_IDR0, WRITE_BLK_TYPE_ERROR, 13, 1)
|
||||
FIELD(CFRM_IDR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
|
||||
FIELD(CFRM_IDR0, MFW_OVERRUN_ERROR, 11, 1)
|
||||
FIELD(CFRM_IDR0, FAR_FIFO_UNDERFLOW, 10, 1)
|
||||
FIELD(CFRM_IDR0, FAR_FIFO_OVERFLOW, 9, 1)
|
||||
FIELD(CFRM_IDR0, PER_FRAME_SEQ_ERROR, 8, 1)
|
||||
FIELD(CFRM_IDR0, CRC_ERROR, 7, 1)
|
||||
FIELD(CFRM_IDR0, WRITE_OVERRUN_ERROR, 6, 1)
|
||||
FIELD(CFRM_IDR0, READ_OVERRUN_ERROR, 5, 1)
|
||||
FIELD(CFRM_IDR0, CMD_INTERRUPT_ERROR, 4, 1)
|
||||
FIELD(CFRM_IDR0, WRITE_INTERRUPT_ERROR, 3, 1)
|
||||
FIELD(CFRM_IDR0, READ_INTERRUPT_ERROR, 2, 1)
|
||||
FIELD(CFRM_IDR0, SEU_CRC_ERROR, 1, 1)
|
||||
FIELD(CFRM_IDR0, SEU_ECC_ERROR, 0, 1)
|
||||
REG32(CFRM_IDR1, 0x184)
|
||||
REG32(CFRM_IDR2, 0x188)
|
||||
REG32(CFRM_IDR3, 0x18c)
|
||||
REG32(CFRM_ITR0, 0x190)
|
||||
FIELD(CFRM_ITR0, READ_BROADCAST_ERROR, 21, 1)
|
||||
FIELD(CFRM_ITR0, CMD_MISSING_ERROR, 20, 1)
|
||||
FIELD(CFRM_ITR0, RW_ROWOFF_ERROR, 19, 1)
|
||||
FIELD(CFRM_ITR0, READ_REG_ADDR_ERROR, 18, 1)
|
||||
FIELD(CFRM_ITR0, READ_BLK_TYPE_ERROR, 17, 1)
|
||||
FIELD(CFRM_ITR0, READ_FRAME_ADDR_ERROR, 16, 1)
|
||||
FIELD(CFRM_ITR0, WRITE_REG_ADDR_ERROR, 15, 1)
|
||||
FIELD(CFRM_ITR0, WRITE_BLK_TYPE_ERROR, 13, 1)
|
||||
FIELD(CFRM_ITR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
|
||||
FIELD(CFRM_ITR0, MFW_OVERRUN_ERROR, 11, 1)
|
||||
FIELD(CFRM_ITR0, FAR_FIFO_UNDERFLOW, 10, 1)
|
||||
FIELD(CFRM_ITR0, FAR_FIFO_OVERFLOW, 9, 1)
|
||||
FIELD(CFRM_ITR0, PER_FRAME_SEQ_ERROR, 8, 1)
|
||||
FIELD(CFRM_ITR0, CRC_ERROR, 7, 1)
|
||||
FIELD(CFRM_ITR0, WRITE_OVERRUN_ERROR, 6, 1)
|
||||
FIELD(CFRM_ITR0, READ_OVERRUN_ERROR, 5, 1)
|
||||
FIELD(CFRM_ITR0, CMD_INTERRUPT_ERROR, 4, 1)
|
||||
FIELD(CFRM_ITR0, WRITE_INTERRUPT_ERROR, 3, 1)
|
||||
FIELD(CFRM_ITR0, READ_INTERRUPT_ERROR, 2, 1)
|
||||
FIELD(CFRM_ITR0, SEU_CRC_ERROR, 1, 1)
|
||||
FIELD(CFRM_ITR0, SEU_ECC_ERROR, 0, 1)
|
||||
REG32(CFRM_ITR1, 0x194)
|
||||
REG32(CFRM_ITR2, 0x198)
|
||||
REG32(CFRM_ITR3, 0x19c)
|
||||
REG32(SEU_SYNDRM00, 0x1a0)
|
||||
REG32(SEU_SYNDRM01, 0x1a4)
|
||||
REG32(SEU_SYNDRM02, 0x1a8)
|
||||
REG32(SEU_SYNDRM03, 0x1ac)
|
||||
REG32(SEU_SYNDRM10, 0x1b0)
|
||||
REG32(SEU_SYNDRM11, 0x1b4)
|
||||
REG32(SEU_SYNDRM12, 0x1b8)
|
||||
REG32(SEU_SYNDRM13, 0x1bc)
|
||||
REG32(SEU_SYNDRM20, 0x1c0)
|
||||
REG32(SEU_SYNDRM21, 0x1c4)
|
||||
REG32(SEU_SYNDRM22, 0x1c8)
|
||||
REG32(SEU_SYNDRM23, 0x1cc)
|
||||
REG32(SEU_SYNDRM30, 0x1d0)
|
||||
REG32(SEU_SYNDRM31, 0x1d4)
|
||||
REG32(SEU_SYNDRM32, 0x1d8)
|
||||
REG32(SEU_SYNDRM33, 0x1dc)
|
||||
REG32(SEU_VIRTUAL_SYNDRM0, 0x1e0)
|
||||
REG32(SEU_VIRTUAL_SYNDRM1, 0x1e4)
|
||||
REG32(SEU_VIRTUAL_SYNDRM2, 0x1e8)
|
||||
REG32(SEU_VIRTUAL_SYNDRM3, 0x1ec)
|
||||
REG32(SEU_CRC0, 0x1f0)
|
||||
REG32(SEU_CRC1, 0x1f4)
|
||||
REG32(SEU_CRC2, 0x1f8)
|
||||
REG32(SEU_CRC3, 0x1fc)
|
||||
REG32(CFRAME_FAR_BOT0, 0x200)
|
||||
REG32(CFRAME_FAR_BOT1, 0x204)
|
||||
REG32(CFRAME_FAR_BOT2, 0x208)
|
||||
REG32(CFRAME_FAR_BOT3, 0x20c)
|
||||
REG32(CFRAME_FAR_TOP0, 0x210)
|
||||
REG32(CFRAME_FAR_TOP1, 0x214)
|
||||
REG32(CFRAME_FAR_TOP2, 0x218)
|
||||
REG32(CFRAME_FAR_TOP3, 0x21c)
|
||||
REG32(LAST_FRAME_BOT0, 0x220)
|
||||
FIELD(LAST_FRAME_BOT0, BLOCKTYPE1_LAST_FRAME_LSB, 20, 12)
|
||||
FIELD(LAST_FRAME_BOT0, BLOCKTYPE0_LAST_FRAME, 0, 20)
|
||||
REG32(LAST_FRAME_BOT1, 0x224)
|
||||
FIELD(LAST_FRAME_BOT1, BLOCKTYPE3_LAST_FRAME_LSB, 28, 4)
|
||||
FIELD(LAST_FRAME_BOT1, BLOCKTYPE2_LAST_FRAME, 8, 20)
|
||||
FIELD(LAST_FRAME_BOT1, BLOCKTYPE1_LAST_FRAME_MSB, 0, 8)
|
||||
REG32(LAST_FRAME_BOT2, 0x228)
|
||||
FIELD(LAST_FRAME_BOT2, BLOCKTYPE3_LAST_FRAME_MSB, 0, 16)
|
||||
REG32(LAST_FRAME_BOT3, 0x22c)
|
||||
REG32(LAST_FRAME_TOP0, 0x230)
|
||||
FIELD(LAST_FRAME_TOP0, BLOCKTYPE5_LAST_FRAME_LSB, 20, 12)
|
||||
FIELD(LAST_FRAME_TOP0, BLOCKTYPE4_LAST_FRAME, 0, 20)
|
||||
REG32(LAST_FRAME_TOP1, 0x234)
|
||||
FIELD(LAST_FRAME_TOP1, BLOCKTYPE6_LAST_FRAME, 8, 20)
|
||||
FIELD(LAST_FRAME_TOP1, BLOCKTYPE5_LAST_FRAME_MSB, 0, 8)
|
||||
REG32(LAST_FRAME_TOP2, 0x238)
|
||||
REG32(LAST_FRAME_TOP3, 0x23c)
|
||||
|
||||
#define CFRAME_REG_R_MAX (R_LAST_FRAME_TOP3 + 1)
|
||||
|
||||
#define FRAME_NUM_QWORDS 25
|
||||
#define FRAME_NUM_WORDS (FRAME_NUM_QWORDS * 4) /* 25 * 128 bits */
|
||||
|
||||
typedef struct XlnxCFrame {
|
||||
uint32_t data[FRAME_NUM_WORDS];
|
||||
} XlnxCFrame;
|
||||
|
||||
struct XlnxVersalCFrameReg {
|
||||
SysBusDevice parent_obj;
|
||||
MemoryRegion iomem;
|
||||
MemoryRegion iomem_fdri;
|
||||
qemu_irq irq_cfrm_imr;
|
||||
|
||||
/* 128-bit wfifo. */
|
||||
uint32_t wfifo[WFIFO_SZ];
|
||||
|
||||
uint32_t regs[CFRAME_REG_R_MAX];
|
||||
RegisterInfo regs_info[CFRAME_REG_R_MAX];
|
||||
|
||||
bool rowon;
|
||||
bool wcfg;
|
||||
bool rcfg;
|
||||
|
||||
GTree *cframes;
|
||||
Fifo32 new_f_data;
|
||||
|
||||
struct {
|
||||
XlnxCfiIf *cfu_fdro;
|
||||
uint32_t blktype_num_frames[7];
|
||||
} cfg;
|
||||
bool row_configured;
|
||||
};
|
||||
|
||||
struct XlnxVersalCFrameBcastReg {
|
||||
SysBusDevice parent_obj;
|
||||
MemoryRegion iomem_reg;
|
||||
MemoryRegion iomem_fdri;
|
||||
|
||||
/* 128-bit wfifo. */
|
||||
uint32_t wfifo[WFIFO_SZ];
|
||||
|
||||
struct {
|
||||
XlnxCfiIf *cframe[15];
|
||||
} cfg;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,258 @@
|
||||
/*
|
||||
* QEMU model of the CFU Configuration Unit.
|
||||
*
|
||||
* Copyright (C) 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Written by Francisco Iglesias <francisco.iglesias@amd.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* References:
|
||||
* [1] Versal ACAP Technical Reference Manual,
|
||||
* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
|
||||
*
|
||||
* [2] Versal ACAP Register Reference,
|
||||
* https://www.xilinx.com/htmldocs/registers/am012/am012-versal-register-reference.html
|
||||
*/
|
||||
#ifndef HW_MISC_XLNX_VERSAL_CFU_APB_H
|
||||
#define HW_MISC_XLNX_VERSAL_CFU_APB_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/register.h"
|
||||
#include "hw/misc/xlnx-cfi-if.h"
|
||||
#include "qemu/fifo32.h"
|
||||
|
||||
#define TYPE_XLNX_VERSAL_CFU_APB "xlnx,versal-cfu-apb"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUAPB, XLNX_VERSAL_CFU_APB)
|
||||
|
||||
#define TYPE_XLNX_VERSAL_CFU_FDRO "xlnx,versal-cfu-fdro"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUFDRO, XLNX_VERSAL_CFU_FDRO)
|
||||
|
||||
#define TYPE_XLNX_VERSAL_CFU_SFR "xlnx,versal-cfu-sfr"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUSFR, XLNX_VERSAL_CFU_SFR)
|
||||
|
||||
REG32(CFU_ISR, 0x0)
|
||||
FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
|
||||
FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
|
||||
FIELD(CFU_ISR, SLVERR, 7, 1)
|
||||
FIELD(CFU_ISR, DECOMP_ERROR, 6, 1)
|
||||
FIELD(CFU_ISR, BAD_CFI_PACKET, 5, 1)
|
||||
FIELD(CFU_ISR, AXI_ALIGN_ERROR, 4, 1)
|
||||
FIELD(CFU_ISR, CFI_ROW_ERROR, 3, 1)
|
||||
FIELD(CFU_ISR, CRC32_ERROR, 2, 1)
|
||||
FIELD(CFU_ISR, CRC8_ERROR, 1, 1)
|
||||
FIELD(CFU_ISR, SEU_ENDOFCALIB, 0, 1)
|
||||
REG32(CFU_IMR, 0x4)
|
||||
FIELD(CFU_IMR, USR_GTS_EVENT, 9, 1)
|
||||
FIELD(CFU_IMR, USR_GSR_EVENT, 8, 1)
|
||||
FIELD(CFU_IMR, SLVERR, 7, 1)
|
||||
FIELD(CFU_IMR, DECOMP_ERROR, 6, 1)
|
||||
FIELD(CFU_IMR, BAD_CFI_PACKET, 5, 1)
|
||||
FIELD(CFU_IMR, AXI_ALIGN_ERROR, 4, 1)
|
||||
FIELD(CFU_IMR, CFI_ROW_ERROR, 3, 1)
|
||||
FIELD(CFU_IMR, CRC32_ERROR, 2, 1)
|
||||
FIELD(CFU_IMR, CRC8_ERROR, 1, 1)
|
||||
FIELD(CFU_IMR, SEU_ENDOFCALIB, 0, 1)
|
||||
REG32(CFU_IER, 0x8)
|
||||
FIELD(CFU_IER, USR_GTS_EVENT, 9, 1)
|
||||
FIELD(CFU_IER, USR_GSR_EVENT, 8, 1)
|
||||
FIELD(CFU_IER, SLVERR, 7, 1)
|
||||
FIELD(CFU_IER, DECOMP_ERROR, 6, 1)
|
||||
FIELD(CFU_IER, BAD_CFI_PACKET, 5, 1)
|
||||
FIELD(CFU_IER, AXI_ALIGN_ERROR, 4, 1)
|
||||
FIELD(CFU_IER, CFI_ROW_ERROR, 3, 1)
|
||||
FIELD(CFU_IER, CRC32_ERROR, 2, 1)
|
||||
FIELD(CFU_IER, CRC8_ERROR, 1, 1)
|
||||
FIELD(CFU_IER, SEU_ENDOFCALIB, 0, 1)
|
||||
REG32(CFU_IDR, 0xc)
|
||||
FIELD(CFU_IDR, USR_GTS_EVENT, 9, 1)
|
||||
FIELD(CFU_IDR, USR_GSR_EVENT, 8, 1)
|
||||
FIELD(CFU_IDR, SLVERR, 7, 1)
|
||||
FIELD(CFU_IDR, DECOMP_ERROR, 6, 1)
|
||||
FIELD(CFU_IDR, BAD_CFI_PACKET, 5, 1)
|
||||
FIELD(CFU_IDR, AXI_ALIGN_ERROR, 4, 1)
|
||||
FIELD(CFU_IDR, CFI_ROW_ERROR, 3, 1)
|
||||
FIELD(CFU_IDR, CRC32_ERROR, 2, 1)
|
||||
FIELD(CFU_IDR, CRC8_ERROR, 1, 1)
|
||||
FIELD(CFU_IDR, SEU_ENDOFCALIB, 0, 1)
|
||||
REG32(CFU_ITR, 0x10)
|
||||
FIELD(CFU_ITR, USR_GTS_EVENT, 9, 1)
|
||||
FIELD(CFU_ITR, USR_GSR_EVENT, 8, 1)
|
||||
FIELD(CFU_ITR, SLVERR, 7, 1)
|
||||
FIELD(CFU_ITR, DECOMP_ERROR, 6, 1)
|
||||
FIELD(CFU_ITR, BAD_CFI_PACKET, 5, 1)
|
||||
FIELD(CFU_ITR, AXI_ALIGN_ERROR, 4, 1)
|
||||
FIELD(CFU_ITR, CFI_ROW_ERROR, 3, 1)
|
||||
FIELD(CFU_ITR, CRC32_ERROR, 2, 1)
|
||||
FIELD(CFU_ITR, CRC8_ERROR, 1, 1)
|
||||
FIELD(CFU_ITR, SEU_ENDOFCALIB, 0, 1)
|
||||
REG32(CFU_PROTECT, 0x14)
|
||||
FIELD(CFU_PROTECT, ACTIVE, 0, 1)
|
||||
REG32(CFU_FGCR, 0x18)
|
||||
FIELD(CFU_FGCR, GCLK_CAL, 14, 1)
|
||||
FIELD(CFU_FGCR, SC_HBC_TRIGGER, 13, 1)
|
||||
FIELD(CFU_FGCR, GLOW, 12, 1)
|
||||
FIELD(CFU_FGCR, GPWRDWN, 11, 1)
|
||||
FIELD(CFU_FGCR, GCAP, 10, 1)
|
||||
FIELD(CFU_FGCR, GSCWE, 9, 1)
|
||||
FIELD(CFU_FGCR, GHIGH_B, 8, 1)
|
||||
FIELD(CFU_FGCR, GMC_B, 7, 1)
|
||||
FIELD(CFU_FGCR, GWE, 6, 1)
|
||||
FIELD(CFU_FGCR, GRESTORE, 5, 1)
|
||||
FIELD(CFU_FGCR, GTS_CFG_B, 4, 1)
|
||||
FIELD(CFU_FGCR, GLUTMASK, 3, 1)
|
||||
FIELD(CFU_FGCR, EN_GLOBS_B, 2, 1)
|
||||
FIELD(CFU_FGCR, EOS, 1, 1)
|
||||
FIELD(CFU_FGCR, INIT_COMPLETE, 0, 1)
|
||||
REG32(CFU_CTL, 0x1c)
|
||||
FIELD(CFU_CTL, GSR_GSC, 15, 1)
|
||||
FIELD(CFU_CTL, SLVERR_EN, 14, 1)
|
||||
FIELD(CFU_CTL, CRC32_RESET, 13, 1)
|
||||
FIELD(CFU_CTL, AXI_ERROR_EN, 12, 1)
|
||||
FIELD(CFU_CTL, FLUSH_AXI, 11, 1)
|
||||
FIELD(CFU_CTL, SSI_PER_SLR_PR, 10, 1)
|
||||
FIELD(CFU_CTL, GCAP_CLK_EN, 9, 1)
|
||||
FIELD(CFU_CTL, STATUS_SYNC_DISABLE, 8, 1)
|
||||
FIELD(CFU_CTL, IGNORE_CFI_ERROR, 7, 1)
|
||||
FIELD(CFU_CTL, CFRAME_DISABLE, 6, 1)
|
||||
FIELD(CFU_CTL, QWORD_CNT_RESET, 5, 1)
|
||||
FIELD(CFU_CTL, CRC8_DISABLE, 4, 1)
|
||||
FIELD(CFU_CTL, CRC32_CHECK, 3, 1)
|
||||
FIELD(CFU_CTL, DECOMPRESS, 2, 1)
|
||||
FIELD(CFU_CTL, SEU_GO, 1, 1)
|
||||
FIELD(CFU_CTL, CFI_LOCAL_RESET, 0, 1)
|
||||
REG32(CFU_CRAM_RW, 0x20)
|
||||
FIELD(CFU_CRAM_RW, RFIFO_AFULL_DEPTH, 18, 9)
|
||||
FIELD(CFU_CRAM_RW, RD_WAVE_CNT_LEFT, 12, 6)
|
||||
FIELD(CFU_CRAM_RW, RD_WAVE_CNT, 6, 6)
|
||||
FIELD(CFU_CRAM_RW, WR_WAVE_CNT, 0, 6)
|
||||
REG32(CFU_MASK, 0x28)
|
||||
REG32(CFU_CRC_EXPECT, 0x2c)
|
||||
REG32(CFU_CFRAME_LEFT_T0, 0x60)
|
||||
FIELD(CFU_CFRAME_LEFT_T0, NUM, 0, 20)
|
||||
REG32(CFU_CFRAME_LEFT_T1, 0x64)
|
||||
FIELD(CFU_CFRAME_LEFT_T1, NUM, 0, 20)
|
||||
REG32(CFU_CFRAME_LEFT_T2, 0x68)
|
||||
FIELD(CFU_CFRAME_LEFT_T2, NUM, 0, 20)
|
||||
REG32(CFU_ROW_RANGE, 0x6c)
|
||||
FIELD(CFU_ROW_RANGE, HALF_FSR, 5, 1)
|
||||
FIELD(CFU_ROW_RANGE, NUM, 0, 5)
|
||||
REG32(CFU_STATUS, 0x100)
|
||||
FIELD(CFU_STATUS, SEU_WRITE_ERROR, 30, 1)
|
||||
FIELD(CFU_STATUS, FRCNT_ERROR, 29, 1)
|
||||
FIELD(CFU_STATUS, RSVD_ERROR, 28, 1)
|
||||
FIELD(CFU_STATUS, FDRO_ERROR, 27, 1)
|
||||
FIELD(CFU_STATUS, FDRI_ERROR, 26, 1)
|
||||
FIELD(CFU_STATUS, FDRI_READ_ERROR, 25, 1)
|
||||
FIELD(CFU_STATUS, READ_FDRI_ERROR, 24, 1)
|
||||
FIELD(CFU_STATUS, READ_SFR_ERROR, 23, 1)
|
||||
FIELD(CFU_STATUS, READ_STREAM_ERROR, 22, 1)
|
||||
FIELD(CFU_STATUS, UNKNOWN_STREAM_PKT, 21, 1)
|
||||
FIELD(CFU_STATUS, USR_GTS, 20, 1)
|
||||
FIELD(CFU_STATUS, USR_GSR, 19, 1)
|
||||
FIELD(CFU_STATUS, AXI_BAD_WSTRB, 18, 1)
|
||||
FIELD(CFU_STATUS, AXI_BAD_AR_SIZE, 17, 1)
|
||||
FIELD(CFU_STATUS, AXI_BAD_AW_SIZE, 16, 1)
|
||||
FIELD(CFU_STATUS, AXI_BAD_ARADDR, 15, 1)
|
||||
FIELD(CFU_STATUS, AXI_BAD_AWADDR, 14, 1)
|
||||
FIELD(CFU_STATUS, SCAN_CLEAR_PASS, 13, 1)
|
||||
FIELD(CFU_STATUS, HC_SEC_ERROR, 12, 1)
|
||||
FIELD(CFU_STATUS, GHIGH_B_ISHIGH, 11, 1)
|
||||
FIELD(CFU_STATUS, GHIGH_B_ISLOW, 10, 1)
|
||||
FIELD(CFU_STATUS, GMC_B_ISHIGH, 9, 1)
|
||||
FIELD(CFU_STATUS, GMC_B_ISLOW, 8, 1)
|
||||
FIELD(CFU_STATUS, GPWRDWN_B_ISHIGH, 7, 1)
|
||||
FIELD(CFU_STATUS, CFI_SEU_CRC_ERROR, 6, 1)
|
||||
FIELD(CFU_STATUS, CFI_SEU_ECC_ERROR, 5, 1)
|
||||
FIELD(CFU_STATUS, CFI_SEU_HEARTBEAT, 4, 1)
|
||||
FIELD(CFU_STATUS, SCAN_CLEAR_DONE, 3, 1)
|
||||
FIELD(CFU_STATUS, HC_COMPLETE, 2, 1)
|
||||
FIELD(CFU_STATUS, CFI_CFRAME_BUSY, 1, 1)
|
||||
FIELD(CFU_STATUS, CFU_STREAM_BUSY, 0, 1)
|
||||
REG32(CFU_INTERNAL_STATUS, 0x104)
|
||||
FIELD(CFU_INTERNAL_STATUS, SSI_EOS, 22, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, SSI_GWE, 21, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, RFIFO_EMPTY, 20, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, RFIFO_FULL, 19, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, SEL_SFR, 18, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, STREAM_CFRAME, 17, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, FDRI_PHASE, 16, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, CFI_PIPE_EN, 15, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, AWFIFO_DCNT, 10, 5)
|
||||
FIELD(CFU_INTERNAL_STATUS, WFIFO_DCNT, 5, 5)
|
||||
FIELD(CFU_INTERNAL_STATUS, REPAIR_BUSY, 4, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, TRIMU_BUSY, 3, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, TRIMB_BUSY, 2, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, HCLEANR_BUSY, 1, 1)
|
||||
FIELD(CFU_INTERNAL_STATUS, HCLEAN_BUSY, 0, 1)
|
||||
REG32(CFU_QWORD_CNT, 0x108)
|
||||
REG32(CFU_CRC_LIVE, 0x10c)
|
||||
REG32(CFU_PENDING_READ_CNT, 0x110)
|
||||
FIELD(CFU_PENDING_READ_CNT, NUM, 0, 25)
|
||||
REG32(CFU_FDRI_CNT, 0x114)
|
||||
REG32(CFU_ECO1, 0x118)
|
||||
REG32(CFU_ECO2, 0x11c)
|
||||
|
||||
#define R_MAX (R_CFU_ECO2 + 1)
|
||||
|
||||
#define NUM_STREAM 2
|
||||
#define WFIFO_SZ 4
|
||||
|
||||
struct XlnxVersalCFUAPB {
|
||||
SysBusDevice parent_obj;
|
||||
MemoryRegion iomem;
|
||||
MemoryRegion iomem_stream[NUM_STREAM];
|
||||
qemu_irq irq_cfu_imr;
|
||||
|
||||
/* 128-bit wfifo. */
|
||||
uint32_t wfifo[WFIFO_SZ];
|
||||
|
||||
uint32_t regs[R_MAX];
|
||||
RegisterInfo regs_info[R_MAX];
|
||||
|
||||
uint8_t fdri_row_addr;
|
||||
|
||||
struct {
|
||||
XlnxCfiIf *cframe[15];
|
||||
} cfg;
|
||||
};
|
||||
|
||||
|
||||
struct XlnxVersalCFUFDRO {
|
||||
SysBusDevice parent_obj;
|
||||
MemoryRegion iomem_fdro;
|
||||
|
||||
Fifo32 fdro_data;
|
||||
};
|
||||
|
||||
struct XlnxVersalCFUSFR {
|
||||
SysBusDevice parent_obj;
|
||||
MemoryRegion iomem_sfr;
|
||||
|
||||
/* 128-bit wfifo. */
|
||||
uint32_t wfifo[WFIFO_SZ];
|
||||
|
||||
struct {
|
||||
XlnxVersalCFUAPB *cfu;
|
||||
} cfg;
|
||||
};
|
||||
|
||||
/**
|
||||
* This is a helper function for updating a CFI data write fifo, an array of 4
|
||||
* uint32_t and 128 bits of data that are allowed to be written through 4
|
||||
* sequential 32 bit accesses. After the last index has been written into the
|
||||
* write fifo (wfifo), the data is copied to and returned in a secondary fifo
|
||||
* provided to the function (wfifo_ret), and the write fifo is cleared
|
||||
* (zeroized).
|
||||
*
|
||||
* @addr: the address used when calculating the wfifo array index to update
|
||||
* @value: the value to write into the wfifo array
|
||||
* @wfifo: the wfifo to update
|
||||
* @wfifo_out: will return the wfifo data when all 128 bits have been written
|
||||
*
|
||||
* @return: true if all 128 bits have been updated.
|
||||
*/
|
||||
bool update_wfifo(hwaddr addr, uint64_t value,
|
||||
uint32_t *wfifo, uint32_t *wfifo_ret);
|
||||
|
||||
#endif
|
||||
@@ -116,6 +116,7 @@ struct KVMState
|
||||
uint64_t kvm_dirty_ring_bytes; /* Size of the per-vcpu dirty ring */
|
||||
uint32_t kvm_dirty_ring_size; /* Number of dirty GFNs per ring */
|
||||
bool kvm_dirty_ring_with_bitmap;
|
||||
uint64_t kvm_eager_split_size; /* Eager Page Splitting chunk size */
|
||||
struct KVMDirtyRingReaper reaper;
|
||||
NotifyVmexitOption notify_vmexit;
|
||||
uint32_t notify_window;
|
||||
|
||||
@@ -186,6 +186,7 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel,
|
||||
" split-wx=on|off (enable TCG split w^x mapping)\n"
|
||||
" tb-size=n (TCG translation block cache size)\n"
|
||||
" dirty-ring-size=n (KVM dirty ring GFN count, default 0)\n"
|
||||
" eager-split-size=n (KVM Eager Page Split chunk size, default 0, disabled. ARM only)\n"
|
||||
" notify-vmexit=run|internal-error|disable,notify-window=n (enable notify VM exit and set notify window, x86 only)\n"
|
||||
" thread=single|multi (enable multi-threaded TCG)\n", QEMU_ARCH_ALL)
|
||||
SRST
|
||||
@@ -244,6 +245,20 @@ SRST
|
||||
is disabled (dirty-ring-size=0). When enabled, KVM will instead
|
||||
record dirty pages in a bitmap.
|
||||
|
||||
``eager-split-size=n``
|
||||
KVM implements dirty page logging at the PAGE_SIZE granularity and
|
||||
enabling dirty-logging on a huge-page requires breaking it into
|
||||
PAGE_SIZE pages in the first place. KVM on ARM does this splitting
|
||||
lazily by default. There are performance benefits in doing huge-page
|
||||
split eagerly, especially in situations where TLBI costs associated
|
||||
with break-before-make sequences are considerable and also if guest
|
||||
workloads are read intensive. The size here specifies how many pages
|
||||
to break at a time and needs to be a valid block size which is
|
||||
1GB/2MB/4KB, 32MB/16KB and 512MB/64KB for 4KB/16KB/64KB PAGE_SIZE
|
||||
respectively. Be wary of specifying a higher size as it will have an
|
||||
impact on the memory. By default, this feature is disabled
|
||||
(eager-split-size=0).
|
||||
|
||||
``notify-vmexit=run|internal-error|disable,notify-window=n``
|
||||
Enables or disables notify VM exit support on x86 host and specify
|
||||
the corresponding notify window to trigger the VM exit if enabled.
|
||||
|
||||
@@ -95,7 +95,7 @@ static const char *cpu_model_advertised_features[] = {
|
||||
"sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
|
||||
"sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
|
||||
"kvm-no-adjvtime", "kvm-steal-time",
|
||||
"pauth", "pauth-impdef",
|
||||
"pauth", "pauth-impdef", "pauth-qarma3",
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
@@ -243,6 +243,10 @@ static void arm_cpu_reset_hold(Object *obj)
|
||||
SCTLR_EnDA | SCTLR_EnDB);
|
||||
/* Trap on btype=3 for PACIxSP. */
|
||||
env->cp15.sctlr_el[1] |= SCTLR_BT0;
|
||||
/* Trap on implementation defined registers. */
|
||||
if (cpu_isar_feature(aa64_tidcp1, cpu)) {
|
||||
env->cp15.sctlr_el[1] |= SCTLR_TIDCP;
|
||||
}
|
||||
/* and to the FP/Neon instructions */
|
||||
env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
|
||||
CPACR_EL1, FPEN, 3);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user