mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
hw/hppa: Implement DINO system board
Now that we have the prerequisites in target/hppa/, implement the hardware for a PA7100LC. This also enables build for hppa-softmmu. Signed-off-by: Helge Deller <deller@gmx.de> [rth: Since it is all new code, squashed all branch development withing hw/hppa/ to a single patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Helge Deller
committed by
Richard Henderson
Richard Henderson
parent
7b93dab51e
commit
a72bd606ca
@@ -156,6 +156,7 @@ trace-events-subdirs += hw/vfio
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trace-events-subdirs += hw/acpi
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trace-events-subdirs += hw/arm
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trace-events-subdirs += hw/alpha
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trace-events-subdirs += hw/hppa
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trace-events-subdirs += hw/xen
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trace-events-subdirs += hw/ide
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trace-events-subdirs += ui
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@@ -0,0 +1,14 @@
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include pci.mak
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include usb.mak
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CONFIG_SERIAL=y
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CONFIG_SERIAL_ISA=y
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CONFIG_ISA_BUS=y
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CONFIG_I8259=y
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CONFIG_VIRTIO_PCI=$(CONFIG_PCI)
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CONFIG_VIRTIO=y
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CONFIG_E1000_PCI=y
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CONFIG_IDE_ISA=y
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CONFIG_IDE_CMD646=y
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# CONFIG_IDE_MMIO=y
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CONFIG_VIRTIO_VGA=y
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CONFIG_MC146818RTC=y
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@@ -1 +1 @@
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obj-y += machine.o
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obj-y += machine.o pci.o dino.o
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+518
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,40 @@
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/* HPPA cores and system support chips. */
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#define FIRMWARE_START 0xf0000000
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#define FIRMWARE_END 0xf0800000
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#define DEVICE_HPA_LEN 0x00100000
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#define GSC_HPA 0xffc00000
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#define DINO_HPA 0xfff80000
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#define DINO_UART_HPA 0xfff83000
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#define DINO_UART_BASE 0xfff83800
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#define DINO_SCSI_HPA 0xfff8c000
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#define LASI_HPA 0xffd00000
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#define LASI_UART_HPA 0xffd05000
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#define LASI_SCSI_HPA 0xffd06000
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#define LASI_LAN_HPA 0xffd07000
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#define LASI_LPT_HPA 0xffd02000
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#define LASI_AUDIO_HPA 0xffd04000
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#define LASI_PS2KBD_HPA 0xffd08000
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#define LASI_PS2MOU_HPA 0xffd08100
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#define LASI_GFX_HPA 0xf8000000
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#define CPU_HPA 0xfff10000
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#define MEMORY_HPA 0xfffbf000
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#define PCI_HPA DINO_HPA /* PCI bus */
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#define IDE_HPA 0xf9000000 /* Boot disc controller */
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/* offsets to DINO HPA: */
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#define DINO_PCI_ADDR 0x064
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#define DINO_CONFIG_DATA 0x068
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#define DINO_IO_DATA 0x06c
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#define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR)
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#define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA)
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#define PORT_SERIAL1 (DINO_UART_HPA + 0x800)
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#define PORT_SERIAL2 (LASI_UART_HPA + 0x800)
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#define HPPA_MAX_CPUS 32 /* max. number of SMP CPUs */
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#define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */
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@@ -0,0 +1,24 @@
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/* HPPA cores and system support chips. */
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#ifndef HW_HPPA_SYS_H
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#define HW_HPPA_SYS_H
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#include "target/hppa/cpu-qom.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/ide.h"
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#include "hw/i386/pc.h"
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#include "hw/irq.h"
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#include "hw/hppa/hppa_hardware.h"
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PCIBus *dino_init(MemoryRegion *, qemu_irq *, qemu_irq *);
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#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
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/* hppa_pci.c. */
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extern const MemoryRegionOps hppa_pci_ignore_ops;
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extern const MemoryRegionOps hppa_pci_conf1_ops;
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extern const MemoryRegionOps hppa_pci_iack_ops;
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#endif
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+246
-1
@@ -16,20 +16,265 @@
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#include "hw/ide.h"
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#include "hw/timer/i8254.h"
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#include "hw/char/serial.h"
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#include "hw/hppa/hppa_sys.h"
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#include "qemu/cutils.h"
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#include "qapi/error.h"
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#define MAX_IDE_BUS 2
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static ISABus *hppa_isa_bus(void)
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{
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ISABus *isa_bus;
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qemu_irq *isa_irqs;
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MemoryRegion *isa_region;
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isa_region = g_new(MemoryRegion, 1);
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memory_region_init_io(isa_region, NULL, &hppa_pci_ignore_ops,
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NULL, "isa-io", 0x800);
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memory_region_add_subregion(get_system_memory(), IDE_HPA,
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isa_region);
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isa_bus = isa_bus_new(NULL, get_system_memory(), isa_region,
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&error_abort);
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isa_irqs = i8259_init(isa_bus,
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/* qemu_allocate_irq(dino_set_isa_irq, s, 0)); */
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NULL);
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isa_bus_irqs(isa_bus, isa_irqs);
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return isa_bus;
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}
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static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr)
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{
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addr &= (0x10000000 - 1);
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return addr;
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}
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static HPPACPU *cpu[HPPA_MAX_CPUS];
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static uint64_t firmware_entry;
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static void machine_hppa_init(MachineState *machine)
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{
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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PCIBus *pci_bus;
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ISABus *isa_bus;
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qemu_irq rtc_irq, serial_irq;
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char *firmware_filename;
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uint64_t firmware_low, firmware_high;
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long size;
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uint64_t kernel_entry = 0, kernel_low, kernel_high;
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MemoryRegion *addr_space = get_system_memory();
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MemoryRegion *rom_region;
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MemoryRegion *ram_region;
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MemoryRegion *cpu_region;
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long i;
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ram_size = machine->ram_size;
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/* Create CPUs. */
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for (i = 0; i < smp_cpus; i++) {
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cpu[i] = HPPA_CPU(cpu_create(machine->cpu_type));
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cpu_region = g_new(MemoryRegion, 1);
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memory_region_init_io(cpu_region, OBJECT(cpu[i]), &hppa_io_eir_ops,
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cpu[i], g_strdup_printf("cpu%ld-io-eir", i), 4);
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memory_region_add_subregion(addr_space, CPU_HPA + i * 0x1000,
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cpu_region);
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}
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/* Limit main memory. */
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if (ram_size > FIRMWARE_START) {
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machine->ram_size = ram_size = FIRMWARE_START;
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}
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/* Main memory region. */
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ram_region = g_new(MemoryRegion, 1);
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memory_region_allocate_system_memory(ram_region, OBJECT(machine),
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"ram", ram_size);
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memory_region_add_subregion(addr_space, 0, ram_region);
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/* Init Dino (PCI host bus chip). */
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pci_bus = dino_init(addr_space, &rtc_irq, &serial_irq);
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assert(pci_bus);
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/* Create ISA bus. */
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isa_bus = hppa_isa_bus();
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assert(isa_bus);
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/* Realtime clock, used by firmware for PDC_TOD call. */
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mc146818_rtc_init(isa_bus, 2000, rtc_irq);
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/* Serial code setup. */
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if (serial_hds[0]) {
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uint32_t addr = DINO_UART_HPA + 0x800;
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serial_mm_init(addr_space, addr, 0, serial_irq,
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115200, serial_hds[0], DEVICE_BIG_ENDIAN);
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fprintf(stderr, "Serial port created at 0x%x\n", addr);
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}
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/* SCSI disk setup. */
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lsi53c895a_create(pci_bus);
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/* Network setup. e1000 is good enough, failing Tulip support. */
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for (i = 0; i < nb_nics; i++) {
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pci_nic_init_nofail(&nd_table[i], pci_bus, "e1000", NULL);
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}
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/* Load firmware. Given that this is not "real" firmware,
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but one explicitly written for the emulation, we might as
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well load it directly from an ELF image. */
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firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
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bios_name ? bios_name :
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"hppa-firmware.img");
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if (firmware_filename == NULL) {
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error_report("no firmware provided");
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exit(1);
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}
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size = load_elf(firmware_filename, NULL,
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NULL, &firmware_entry, &firmware_low, &firmware_high,
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true, EM_PARISC, 0, 0);
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/* Unfortunately, load_elf sign-extends reading elf32. */
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firmware_entry = (target_ureg)firmware_entry;
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firmware_low = (target_ureg)firmware_low;
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firmware_high = (target_ureg)firmware_high;
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if (size < 0) {
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error_report("could not load firmware '%s'", firmware_filename);
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exit(1);
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}
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fprintf(stderr, "Firmware loaded at 0x%08" PRIx64 "-0x%08" PRIx64
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", entry at 0x%08" PRIx64 ".\n",
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firmware_low, firmware_high, firmware_entry);
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if (firmware_low < ram_size || firmware_high >= FIRMWARE_END) {
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error_report("Firmware overlaps with memory or IO space");
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exit(1);
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}
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g_free(firmware_filename);
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rom_region = g_new(MemoryRegion, 1);
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memory_region_allocate_system_memory(rom_region, OBJECT(machine),
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"firmware",
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(FIRMWARE_END - FIRMWARE_START));
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memory_region_add_subregion(addr_space, FIRMWARE_START, rom_region);
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/* Load kernel */
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if (kernel_filename) {
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fprintf(stderr, "LOADING kernel '%s'\n", kernel_filename);
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size = load_elf(kernel_filename, &cpu_hppa_to_phys,
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NULL, &kernel_entry, &kernel_low, &kernel_high,
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true, EM_PARISC, 0, 0);
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/* Unfortunately, load_elf sign-extends reading elf32. */
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kernel_entry = (target_ureg) cpu_hppa_to_phys(NULL, kernel_entry);
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kernel_low = (target_ureg)kernel_low;
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kernel_high = (target_ureg)kernel_high;
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if (size < 0) {
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error_report("could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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fprintf(stderr, "Kernel loaded at 0x%08" PRIx64 "-0x%08" PRIx64
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", entry at 0x%08" PRIx64 ", size %ld kB.\n",
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kernel_low, kernel_high, kernel_entry, size / 1024);
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if (kernel_cmdline) {
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cpu[0]->env.gr[24] = 0x4000;
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pstrcpy_targphys("cmdline", cpu[0]->env.gr[24],
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TARGET_PAGE_SIZE, kernel_cmdline);
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}
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if (initrd_filename) {
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ram_addr_t initrd_base;
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long initrd_size;
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initrd_size = get_image_size(initrd_filename);
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if (initrd_size < 0) {
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error_report("could not load initial ram disk '%s'",
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initrd_filename);
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exit(1);
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}
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/* Load the initrd image high in memory.
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Mirror the algorithm used by palo:
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(1) Due to sign-extension problems and PDC,
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put the initrd no higher than 1G.
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(2) Reserve 64k for stack. */
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initrd_base = MIN(ram_size, 1024 * 1024 * 1024);
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initrd_base = initrd_base - 64 * 1024;
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initrd_base = (initrd_base - initrd_size) & TARGET_PAGE_MASK;
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if (initrd_base < kernel_high) {
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error_report("kernel and initial ram disk too large!");
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exit(1);
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}
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load_image_targphys(initrd_filename, initrd_base, initrd_size);
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cpu[0]->env.gr[23] = initrd_base;
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cpu[0]->env.gr[22] = initrd_base + initrd_size;
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}
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}
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if (!kernel_entry) {
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/* When booting via firmware, tell firmware if we want interactive
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* mode (kernel_entry=1), and to boot from CD (gr[24]='d')
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* or hard disc * (gr[24]='c').
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*/
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kernel_entry = boot_menu ? 1 : 0;
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cpu[0]->env.gr[24] = machine->boot_order[0];
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}
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/* We jump to the firmware entry routine and pass the
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* various parameters in registers. After firmware initialization,
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* firmware will start the Linux kernel with ramdisk and cmdline.
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*/
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cpu[0]->env.gr[26] = ram_size;
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cpu[0]->env.gr[25] = kernel_entry;
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/* tell firmware how many SMP CPUs to present in inventory table */
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cpu[0]->env.gr[21] = smp_cpus;
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}
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static void hppa_machine_reset(void)
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{
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int i;
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qemu_devices_reset();
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/* Start all CPUs at the firmware entry point.
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* Monarch CPU will initialize firmware, secondary CPUs
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* will enter a small idle look and wait for rendevouz. */
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for (i = 0; i < smp_cpus; i++) {
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cpu_set_pc(CPU(cpu[i]), firmware_entry);
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cpu[i]->env.gr[5] = CPU_HPA + i * 0x1000;
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}
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/* already initialized by machine_hppa_init()? */
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if (cpu[0]->env.gr[26] == ram_size) {
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return;
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}
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cpu[0]->env.gr[26] = ram_size;
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cpu[0]->env.gr[25] = 0; /* no firmware boot menu */
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cpu[0]->env.gr[24] = 'c';
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/* gr22/gr23 unused, no initrd while reboot. */
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cpu[0]->env.gr[21] = smp_cpus;
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}
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static void machine_hppa_machine_init(MachineClass *mc)
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{
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mc->desc = "HPPA generic machine";
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mc->default_cpu_type = TYPE_HPPA_CPU;
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mc->init = machine_hppa_init;
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mc->reset = hppa_machine_reset;
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mc->block_default_type = IF_SCSI;
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mc->max_cpus = 1;
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mc->max_cpus = HPPA_MAX_CPUS;
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mc->default_cpus = 1;
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mc->is_default = 1;
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mc->default_ram_size = 512 * M_BYTE;
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mc->default_boot_order = "cd";
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@@ -0,0 +1,90 @@
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/*
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* QEMU HP-PARISC PCI support functions.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "hppa_sys.h"
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#include "qemu/log.h"
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#include "sysemu/sysemu.h"
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#include "trace.h"
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/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */
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static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size)
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{
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return 0;
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}
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static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size)
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{
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}
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const MemoryRegionOps hppa_pci_ignore_ops = {
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.read = ignore_read,
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.write = ignore_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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/* PCI config space reads/writes, to byte-word addressable memory. */
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static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PCIBus *b = opaque;
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return pci_data_read(b, addr, size);
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}
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static void bw_conf1_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIBus *b = opaque;
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pci_data_write(b, addr, val, size);
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}
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const MemoryRegionOps hppa_pci_conf1_ops = {
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.read = bw_conf1_read,
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.write = bw_conf1_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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/* PCI/EISA Interrupt Acknowledge Cycle. */
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static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
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{
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return pic_read_irq(isa_pic);
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}
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static void special_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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trace_hppa_pci_iack_write();
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}
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const MemoryRegionOps hppa_pci_iack_ops = {
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.read = iack_read,
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.write = special_write,
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.endianness = DEVICE_BIG_ENDIAN,
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||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
},
|
||||
.impl = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,4 @@
|
||||
# See docs/devel/tracing.txt for syntax documentation.
|
||||
|
||||
# hw/hppa/pci.c
|
||||
hppa_pci_iack_write(void) ""
|
||||
Reference in New Issue
Block a user