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target/arm: Add gcs record for BL

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Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20251008215613.300150-56-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
2025-10-10 13:19:10 +01:00
committed by Peter Maydell
parent e85fc2c623
commit a664ba1fc6
1 changed files with 8 additions and 1 deletions
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target/arm/tcg/translate-a64.c
+8 -1
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@@ -1678,7 +1678,14 @@ static bool trans_B(DisasContext *s, arg_i *a)
static bool trans_BL(DisasContext *s, arg_i *a)
{
gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s));
TCGv_i64 link = tcg_temp_new_i64();
gen_pc_plus_diff(s, link, 4);
if (s->gcs_en) {
gen_add_gcs_record(s, link);
}
tcg_gen_mov_i64(cpu_reg(s, 30), link);
reset_btype(s);
gen_goto_tb(s, 0, a->imm);
return true;