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https://github.com/izzy2lost/xemu.git
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Merge tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu into staging
tcg/mips: - Constant formation improvements - Replace MIPS_BE with HOST_BIG_ENDIAN - General cleanups tcg/riscv: - Improve setcond - Support movcond - Support Zbb, Zba # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmRvo9kdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/ECwf/eQSKdXsppLfgH1zj # 1VYOfSHB7kKacm5s9de6n0n0aT5DdBYGT1VkYqczMyanpYrK5jHIyzxYIcxa2KjN # /pMRKALUTq1Aku1wvovpybUT9Qt38+6jHw0U9inj11NJIYX4bheVJon3gztOUBRp # O67Z22RdfBBu+jL6VD00AE8OhCfeU7CZ+Bj9oNRKYCxXyr1ASla9gfTDy8UG+h2k # WqNti04xmgXqOZ+pEQ+ZyOCzhCHNLm8XBCtFjWXBe30ibX1PwWdSXqkuUtddd5nJ # MEbzQV42RCk1CNRrFz0RoAJhpcOEiSeDcI3Vx/PN8xS5mIS2jaWqW+5sMyCcI54h # JcfcUg== # =GI+F # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 May 2023 11:07:21 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu: (23 commits) tcg/riscv: Support CTZ, CLZ from Zbb tcg/riscv: Implement movcond tcg/riscv: Improve setcond expansion tcg/riscv: Support CPOP from Zbb tcg/riscv: Support REV8 from Zbb tcg/riscv: Support rotates from Zbb tcg/riscv: Use ADD.UW for guest address generation tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb tcg/riscv: Support ANDN, ORN, XNOR from Zbb tcg/riscv: Probe for Zba, Zbb, Zicond extensions disas/riscv: Decode czero.{eqz,nez} tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN tcg/mips: Use qemu_build_not_reached for LO/HI_OFF tcg/mips: Try three insns with shift and add in tcg_out_movi tcg/mips: Try tb-relative addresses in tcg_out_movi tcg/mips: Aggressively use the constant pool for n64 calls tcg/mips: Use the constant pool for 64-bit constants tcg/mips: Split out tcg_out_movi_two tcg/mips: Split out tcg_out_movi_one tcg/mips: Create and use TCG_REG_TB ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
@@ -962,6 +962,8 @@ typedef enum {
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rv_op_cm_mvsa01 = 786,
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rv_op_cm_jt = 787,
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rv_op_cm_jalt = 788,
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rv_op_czero_eqz = 789,
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rv_op_czero_nez = 790,
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} rv_op;
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/* structures */
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@@ -2119,6 +2121,8 @@ const rv_opcode_data opcode_data[] = {
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{ "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
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{ "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
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{ "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
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{ "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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};
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/* CSR names */
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@@ -2914,6 +2918,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 45: op = rv_op_minu; break;
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case 46: op = rv_op_max; break;
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case 47: op = rv_op_maxu; break;
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case 075: op = rv_op_czero_eqz; break;
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case 077: op = rv_op_czero_nez; break;
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case 130: op = rv_op_sh1add; break;
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case 132: op = rv_op_sh2add; break;
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case 134: op = rv_op_sh3add; break;
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+237
-71
@@ -25,22 +25,15 @@
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*/
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#include "../tcg-ldst.c.inc"
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#if HOST_BIG_ENDIAN
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# define MIPS_BE 1
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#else
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# define MIPS_BE 0
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#endif
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#include "../tcg-pool.c.inc"
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#if TCG_TARGET_REG_BITS == 32
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# define LO_OFF (MIPS_BE * 4)
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# define LO_OFF (HOST_BIG_ENDIAN * 4)
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# define HI_OFF (4 - LO_OFF)
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#else
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/* To assert at compile-time that these values are never used
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for TCG_TARGET_REG_BITS == 64. */
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int link_error(void);
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# define LO_OFF link_error()
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# define HI_OFF link_error()
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/* Assert at compile-time that these values are never used for 64-bit. */
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# define LO_OFF ({ qemu_build_not_reached(); 0; })
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# define HI_OFF ({ qemu_build_not_reached(); 0; })
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#endif
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#ifdef CONFIG_DEBUG_TCG
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@@ -86,7 +79,12 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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#define TCG_TMP3 TCG_REG_T7
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#ifndef CONFIG_SOFTMMU
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#define TCG_GUEST_BASE_REG TCG_REG_S1
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#define TCG_GUEST_BASE_REG TCG_REG_S7
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#endif
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_REG_TB TCG_REG_S6
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#else
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#define TCG_REG_TB (qemu_build_not_reached(), TCG_REG_ZERO)
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#endif
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/* check if we really need so many registers :P */
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@@ -163,9 +161,18 @@ static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
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static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
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intptr_t value, intptr_t addend)
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{
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tcg_debug_assert(type == R_MIPS_PC16);
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tcg_debug_assert(addend == 0);
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return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
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value += addend;
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switch (type) {
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case R_MIPS_PC16:
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return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
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case R_MIPS_16:
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if (value != (int16_t)value) {
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return false;
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}
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*code_ptr = deposit32(*code_ptr, 0, 16, value);
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return true;
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}
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g_assert_not_reached();
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}
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#define TCG_CT_CONST_ZERO 0x100
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@@ -481,6 +488,11 @@ static void tcg_out_nop(TCGContext *s)
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tcg_out32(s, 0);
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}
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static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
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{
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memset(p, 0, count * sizeof(tcg_insn_unit));
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}
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static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
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{
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tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
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@@ -505,35 +517,125 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
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return true;
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}
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static void tcg_out_movi(TCGContext *s, TCGType type,
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TCGReg ret, tcg_target_long arg)
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static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
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{
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if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
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arg = (int32_t)arg;
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}
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if (arg == (int16_t)arg) {
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tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
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return;
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return true;
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}
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if (arg == (uint16_t)arg) {
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tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
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return true;
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}
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if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
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tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
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return true;
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}
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return false;
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}
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static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg)
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{
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/*
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* All signed 32-bit constants are loadable with two immediates,
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* and everything else requires more work.
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*/
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if (arg == (int32_t)arg) {
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if (!tcg_out_movi_one(s, ret, arg)) {
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tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
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tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
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}
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return true;
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}
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return false;
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}
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static void tcg_out_movi_pool(TCGContext *s, TCGReg ret,
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tcg_target_long arg, TCGReg tbreg)
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{
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new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL));
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tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0);
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}
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static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
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tcg_target_long arg, TCGReg tbreg)
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{
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tcg_target_long tmp;
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int sh, lo;
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if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
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arg = (int32_t)arg;
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}
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/* Load all 32-bit constants. */
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if (tcg_out_movi_two(s, ret, arg)) {
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return;
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}
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if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
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tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
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} else {
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tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
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if (arg & 0xffff0000ull) {
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tcg_out_dsll(s, ret, ret, 16);
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tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
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tcg_out_dsll(s, ret, ret, 16);
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} else {
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tcg_out_dsll(s, ret, ret, 32);
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assert(TCG_TARGET_REG_BITS == 64);
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/* Load addresses within 2GB of TB with 1 or 3 insns. */
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tmp = tcg_tbrel_diff(s, (void *)arg);
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if (tmp == (int16_t)tmp) {
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tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp);
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return;
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}
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if (tcg_out_movi_two(s, ret, tmp)) {
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tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg);
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return;
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}
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/*
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* Load bitmasks with a right-shift. This is good for things
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* like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4.
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* or similarly using LUI. For this to work, bit 31 must be set.
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*/
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if (arg > 0 && (int32_t)arg < 0) {
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sh = clz64(arg);
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if (tcg_out_movi_one(s, ret, arg << sh)) {
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tcg_out_dsrl(s, ret, ret, sh);
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return;
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}
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}
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if (arg & 0xffff) {
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tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
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/*
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* Load slightly larger constants using left-shift.
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* Limit this sequence to 3 insns to avoid too much expansion.
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*/
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sh = ctz64(arg);
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if (sh && tcg_out_movi_two(s, ret, arg >> sh)) {
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tcg_out_dsll(s, ret, ret, sh);
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return;
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}
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/*
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* Load slightly larger constants using left-shift and add/or.
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* Prefer addi with a negative immediate when that would produce
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* a larger shift. For this to work, bits 15 and 16 must be set.
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*/
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lo = arg & 0xffff;
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if (lo) {
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if ((arg & 0x18000) == 0x18000) {
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lo = (int16_t)arg;
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}
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tmp = arg - lo;
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sh = ctz64(tmp);
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tmp >>= sh;
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if (tcg_out_movi_one(s, ret, tmp)) {
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tcg_out_dsll(s, ret, ret, sh);
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tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo);
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return;
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}
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}
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/* Otherwise, put 64-bit constants into the constant pool. */
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tcg_out_movi_pool(s, ret, arg, tbreg);
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}
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static void tcg_out_movi(TCGContext *s, TCGType type,
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TCGReg ret, tcg_target_long arg)
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{
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TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0;
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tcg_out_movi_int(s, type, ret, arg, tbreg);
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}
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static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
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@@ -1048,9 +1150,19 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
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static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
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{
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/* Note that the ABI requires the called function's address to be
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loaded into T9, even if a direct branch is in range. */
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
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/*
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* Note that __mips_abicalls requires the called function's address
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* to be loaded into $25 (t9), even if a direct branch is in range.
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*
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* For n64, always drop the pointer into the constant pool.
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* We can re-use helper addresses often and do not want any
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* of the longer sequences tcg_out_movi may try.
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*/
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if (sizeof(uintptr_t) == 8) {
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tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB);
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} else {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
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}
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/* But do try a direct branch, allowing the cpu better insn prefetch. */
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if (tail) {
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@@ -1321,7 +1433,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
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/* Prefer to load from offset 0 first, but allow for overlap. */
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
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} else if (MIPS_BE ? hi != base : lo == base) {
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} else if (HOST_BIG_ENDIAN ? hi != base : lo == base) {
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tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
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tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
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} else {
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@@ -1337,10 +1449,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
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static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
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TCGReg base, MemOp opc, TCGType type)
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{
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const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR;
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const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL;
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const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR;
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const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL;
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const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR;
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const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL;
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const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR;
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const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL;
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bool sgn = opc & MO_SIGN;
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switch (opc & MO_SIZE) {
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@@ -1379,10 +1491,10 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
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tcg_out_opc_imm(s, ld1, lo, base, 0);
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tcg_out_opc_imm(s, ld2, lo, base, 7);
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} else {
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tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0);
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tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3);
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tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0);
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tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3);
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tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
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tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
|
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tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
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tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
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}
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break;
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@@ -1432,8 +1544,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
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} else {
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tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
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tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
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tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0);
|
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tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4);
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}
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break;
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default:
|
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@@ -1444,10 +1556,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
|
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static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
|
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TCGReg base, MemOp opc)
|
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{
|
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const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR;
|
||||
const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL;
|
||||
const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR;
|
||||
const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL;
|
||||
const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR;
|
||||
const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL;
|
||||
const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR;
|
||||
const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL;
|
||||
|
||||
switch (opc & MO_SIZE) {
|
||||
case MO_16:
|
||||
@@ -1466,10 +1578,10 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
|
||||
tcg_out_opc_imm(s, sd1, lo, base, 0);
|
||||
tcg_out_opc_imm(s, sd2, lo, base, 7);
|
||||
} else {
|
||||
tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0 + 0);
|
||||
tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 0 + 3);
|
||||
tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4 + 0);
|
||||
tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 4 + 3);
|
||||
tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
|
||||
tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
|
||||
tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
|
||||
tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -1547,27 +1659,61 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
|
||||
|
||||
static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
|
||||
{
|
||||
TCGReg b0 = TCG_REG_ZERO;
|
||||
TCGReg base = TCG_REG_ZERO;
|
||||
int16_t lo = 0;
|
||||
|
||||
if (a0 & ~0xffff) {
|
||||
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
|
||||
b0 = TCG_REG_V0;
|
||||
if (a0) {
|
||||
intptr_t ofs;
|
||||
if (TCG_TARGET_REG_BITS == 64) {
|
||||
ofs = tcg_tbrel_diff(s, (void *)a0);
|
||||
lo = ofs;
|
||||
if (ofs == lo) {
|
||||
base = TCG_REG_TB;
|
||||
} else {
|
||||
base = TCG_REG_V0;
|
||||
tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
|
||||
tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB);
|
||||
}
|
||||
} else {
|
||||
ofs = a0;
|
||||
lo = ofs;
|
||||
base = TCG_REG_V0;
|
||||
tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
|
||||
}
|
||||
}
|
||||
if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
|
||||
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr);
|
||||
tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
|
||||
}
|
||||
tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
|
||||
/* delay slot */
|
||||
tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo);
|
||||
}
|
||||
|
||||
static void tcg_out_goto_tb(TCGContext *s, int which)
|
||||
{
|
||||
intptr_t ofs = get_jmp_target_addr(s, which);
|
||||
TCGReg base, dest;
|
||||
|
||||
/* indirect jump method */
|
||||
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
|
||||
get_jmp_target_addr(s, which));
|
||||
tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
|
||||
if (TCG_TARGET_REG_BITS == 64) {
|
||||
dest = TCG_REG_TB;
|
||||
base = TCG_REG_TB;
|
||||
ofs = tcg_tbrel_diff(s, (void *)ofs);
|
||||
} else {
|
||||
dest = TCG_TMP0;
|
||||
base = TCG_REG_ZERO;
|
||||
}
|
||||
tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs);
|
||||
tcg_out_opc_reg(s, OPC_JR, 0, dest, 0);
|
||||
/* delay slot */
|
||||
tcg_out_nop(s);
|
||||
|
||||
set_jmp_reset_offset(s, which);
|
||||
if (TCG_TARGET_REG_BITS == 64) {
|
||||
/* For the unlinked case, need to reset TCG_REG_TB. */
|
||||
tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB,
|
||||
-tcg_current_code_size(s));
|
||||
}
|
||||
}
|
||||
|
||||
void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
|
||||
@@ -1598,7 +1744,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
case INDEX_op_goto_ptr:
|
||||
/* jmp to the given host address (could be epilogue) */
|
||||
tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
|
||||
tcg_out_nop(s);
|
||||
if (TCG_TARGET_REG_BITS == 64) {
|
||||
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
|
||||
} else {
|
||||
tcg_out_nop(s);
|
||||
}
|
||||
break;
|
||||
case INDEX_op_br:
|
||||
tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
|
||||
@@ -2183,15 +2333,15 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
|
||||
}
|
||||
|
||||
static const int tcg_target_callee_save_regs[] = {
|
||||
TCG_REG_S0, /* used for the global env (TCG_AREG0) */
|
||||
TCG_REG_S0,
|
||||
TCG_REG_S1,
|
||||
TCG_REG_S2,
|
||||
TCG_REG_S3,
|
||||
TCG_REG_S4,
|
||||
TCG_REG_S5,
|
||||
TCG_REG_S6,
|
||||
TCG_REG_S7,
|
||||
TCG_REG_S8,
|
||||
TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */
|
||||
TCG_REG_S7, /* used for guest_base */
|
||||
TCG_REG_S8, /* used for the global env (TCG_AREG0) */
|
||||
TCG_REG_RA, /* should be last for ABI compliance */
|
||||
};
|
||||
|
||||
@@ -2312,12 +2462,25 @@ static void tcg_target_qemu_prologue(TCGContext *s)
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SOFTMMU
|
||||
if (guest_base) {
|
||||
tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
|
||||
if (guest_base != (int16_t)guest_base) {
|
||||
/*
|
||||
* The function call abi for n32 and n64 will have loaded $25 (t9)
|
||||
* with the address of the prologue, so we can use that instead
|
||||
* of TCG_REG_TB.
|
||||
*/
|
||||
#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls)
|
||||
# error "Unknown mips abi"
|
||||
#endif
|
||||
tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base,
|
||||
TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0);
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (TCG_TARGET_REG_BITS == 64) {
|
||||
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
|
||||
}
|
||||
|
||||
/* Call generated code */
|
||||
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
|
||||
/* delay slot */
|
||||
@@ -2498,6 +2661,9 @@ static void tcg_target_init(TCGContext *s)
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
|
||||
if (TCG_TARGET_REG_BITS == 64) {
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */
|
||||
}
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
|
||||
@@ -76,7 +76,7 @@ typedef enum {
|
||||
TCG_REG_RA,
|
||||
|
||||
TCG_REG_CALL_STACK = TCG_REG_SP,
|
||||
TCG_AREG0 = TCG_REG_S0,
|
||||
TCG_AREG0 = TCG_REG_S8,
|
||||
} TCGReg;
|
||||
|
||||
/* used for function call generation */
|
||||
@@ -208,5 +208,6 @@ extern bool use_mips32r2_instructions;
|
||||
|
||||
#define TCG_TARGET_DEFAULT_MO 0
|
||||
#define TCG_TARGET_NEED_LDST_LABELS
|
||||
#define TCG_TARGET_NEED_POOL_LABELS
|
||||
|
||||
#endif
|
||||
|
||||
@@ -15,6 +15,9 @@ C_O0_I2(rZ, rZ)
|
||||
C_O1_I1(r, r)
|
||||
C_O1_I2(r, r, ri)
|
||||
C_O1_I2(r, r, rI)
|
||||
C_O1_I2(r, r, rJ)
|
||||
C_O1_I2(r, rZ, rN)
|
||||
C_O1_I2(r, rZ, rZ)
|
||||
C_N1_I2(r, r, rM)
|
||||
C_O1_I4(r, r, rI, rM, rM)
|
||||
C_O2_I4(r, r, rZ, rZ, rM, rM)
|
||||
|
||||
@@ -15,6 +15,7 @@ REGS('r', ALL_GENERAL_REGS)
|
||||
* CONST(letter, TCG_CT_CONST_* bit set)
|
||||
*/
|
||||
CONST('I', TCG_CT_CONST_S12)
|
||||
CONST('J', TCG_CT_CONST_J12)
|
||||
CONST('N', TCG_CT_CONST_N12)
|
||||
CONST('M', TCG_CT_CONST_M12)
|
||||
CONST('Z', TCG_CT_CONST_ZERO)
|
||||
|
||||
+549
-63
File diff suppressed because it is too large
Load Diff
+27
-21
@@ -90,12 +90,18 @@ typedef enum {
|
||||
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
|
||||
#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
|
||||
|
||||
#if defined(__riscv_arch_test) && defined(__riscv_zbb)
|
||||
# define have_zbb true
|
||||
#else
|
||||
extern bool have_zbb;
|
||||
#endif
|
||||
|
||||
/* optional instructions */
|
||||
#define TCG_TARGET_HAS_movcond_i32 0
|
||||
#define TCG_TARGET_HAS_movcond_i32 1
|
||||
#define TCG_TARGET_HAS_div_i32 1
|
||||
#define TCG_TARGET_HAS_rem_i32 1
|
||||
#define TCG_TARGET_HAS_div2_i32 0
|
||||
#define TCG_TARGET_HAS_rot_i32 0
|
||||
#define TCG_TARGET_HAS_rot_i32 have_zbb
|
||||
#define TCG_TARGET_HAS_deposit_i32 0
|
||||
#define TCG_TARGET_HAS_extract_i32 0
|
||||
#define TCG_TARGET_HAS_sextract_i32 0
|
||||
@@ -110,27 +116,27 @@ typedef enum {
|
||||
#define TCG_TARGET_HAS_ext16s_i32 1
|
||||
#define TCG_TARGET_HAS_ext8u_i32 1
|
||||
#define TCG_TARGET_HAS_ext16u_i32 1
|
||||
#define TCG_TARGET_HAS_bswap16_i32 0
|
||||
#define TCG_TARGET_HAS_bswap32_i32 0
|
||||
#define TCG_TARGET_HAS_bswap16_i32 have_zbb
|
||||
#define TCG_TARGET_HAS_bswap32_i32 have_zbb
|
||||
#define TCG_TARGET_HAS_not_i32 1
|
||||
#define TCG_TARGET_HAS_neg_i32 1
|
||||
#define TCG_TARGET_HAS_andc_i32 0
|
||||
#define TCG_TARGET_HAS_orc_i32 0
|
||||
#define TCG_TARGET_HAS_eqv_i32 0
|
||||
#define TCG_TARGET_HAS_andc_i32 have_zbb
|
||||
#define TCG_TARGET_HAS_orc_i32 have_zbb
|
||||
#define TCG_TARGET_HAS_eqv_i32 have_zbb
|
||||
#define TCG_TARGET_HAS_nand_i32 0
|
||||
#define TCG_TARGET_HAS_nor_i32 0
|
||||
#define TCG_TARGET_HAS_clz_i32 0
|
||||
#define TCG_TARGET_HAS_ctz_i32 0
|
||||
#define TCG_TARGET_HAS_ctpop_i32 0
|
||||
#define TCG_TARGET_HAS_clz_i32 have_zbb
|
||||
#define TCG_TARGET_HAS_ctz_i32 have_zbb
|
||||
#define TCG_TARGET_HAS_ctpop_i32 have_zbb
|
||||
#define TCG_TARGET_HAS_brcond2 1
|
||||
#define TCG_TARGET_HAS_setcond2 1
|
||||
#define TCG_TARGET_HAS_qemu_st8_i32 0
|
||||
|
||||
#define TCG_TARGET_HAS_movcond_i64 0
|
||||
#define TCG_TARGET_HAS_movcond_i64 1
|
||||
#define TCG_TARGET_HAS_div_i64 1
|
||||
#define TCG_TARGET_HAS_rem_i64 1
|
||||
#define TCG_TARGET_HAS_div2_i64 0
|
||||
#define TCG_TARGET_HAS_rot_i64 0
|
||||
#define TCG_TARGET_HAS_rot_i64 have_zbb
|
||||
#define TCG_TARGET_HAS_deposit_i64 0
|
||||
#define TCG_TARGET_HAS_extract_i64 0
|
||||
#define TCG_TARGET_HAS_sextract_i64 0
|
||||
@@ -143,19 +149,19 @@ typedef enum {
|
||||
#define TCG_TARGET_HAS_ext8u_i64 1
|
||||
#define TCG_TARGET_HAS_ext16u_i64 1
|
||||
#define TCG_TARGET_HAS_ext32u_i64 1
|
||||
#define TCG_TARGET_HAS_bswap16_i64 0
|
||||
#define TCG_TARGET_HAS_bswap32_i64 0
|
||||
#define TCG_TARGET_HAS_bswap64_i64 0
|
||||
#define TCG_TARGET_HAS_bswap16_i64 have_zbb
|
||||
#define TCG_TARGET_HAS_bswap32_i64 have_zbb
|
||||
#define TCG_TARGET_HAS_bswap64_i64 have_zbb
|
||||
#define TCG_TARGET_HAS_not_i64 1
|
||||
#define TCG_TARGET_HAS_neg_i64 1
|
||||
#define TCG_TARGET_HAS_andc_i64 0
|
||||
#define TCG_TARGET_HAS_orc_i64 0
|
||||
#define TCG_TARGET_HAS_eqv_i64 0
|
||||
#define TCG_TARGET_HAS_andc_i64 have_zbb
|
||||
#define TCG_TARGET_HAS_orc_i64 have_zbb
|
||||
#define TCG_TARGET_HAS_eqv_i64 have_zbb
|
||||
#define TCG_TARGET_HAS_nand_i64 0
|
||||
#define TCG_TARGET_HAS_nor_i64 0
|
||||
#define TCG_TARGET_HAS_clz_i64 0
|
||||
#define TCG_TARGET_HAS_ctz_i64 0
|
||||
#define TCG_TARGET_HAS_ctpop_i64 0
|
||||
#define TCG_TARGET_HAS_clz_i64 have_zbb
|
||||
#define TCG_TARGET_HAS_ctz_i64 have_zbb
|
||||
#define TCG_TARGET_HAS_ctpop_i64 have_zbb
|
||||
#define TCG_TARGET_HAS_add2_i64 1
|
||||
#define TCG_TARGET_HAS_sub2_i64 1
|
||||
#define TCG_TARGET_HAS_mulu2_i64 0
|
||||
|
||||
Reference in New Issue
Block a user