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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
virtio,pc,pci: features, cleanups, fixes vhost-user enabled on non-linux systems beginning of nvme sriov support bigger tx queue for vdpa virtio iommu bypass FADT flag to detect legacy keyboards Fixes, cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 07 Mar 2022 22:43:31 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (47 commits) hw/acpi/microvm: turn on 8042 bit in FADT boot architecture flags if present tests/acpi: i386: update FACP table differences hw/acpi: add indication for i8042 in IA-PC boot flags of the FADT table tests/acpi: i386: allow FACP acpi table changes docs: vhost-user: add subsection for non-Linux platforms configure, meson: allow enabling vhost-user on all POSIX systems vhost: use wfd on functions setting vring call fd event_notifier: add event_notifier_get_wfd() pci: drop COMPAT_PROP_PCP for 2.0 machine types hw/smbios: Add table 4 parameter, "processor-id" x86: cleanup unused compat_apic_id_mode vhost-vsock: detach the virqueue element in case of error pc: add option to disable PS/2 mouse/keyboard acpi: pcihp: pcie: set power on cap on parent slot pci: expose TYPE_XIO3130_DOWNSTREAM name pci: show id info when pci BDF conflict hw/misc/pvpanic: Use standard headers instead headers: Add pvpanic.h pci-bridge/xio3130_downstream: Fix error handling pci-bridge/xio3130_upstream: Fix error handling ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # docs/specs/index.rst
This commit is contained in:
Peter Maydell
@@ -1819,7 +1819,6 @@ F: docs/specs/acpi_hw_reduced_hotplug.rst
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ACPI/VIOT
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M: Jean-Philippe Brucker <jean-philippe@linaro.org>
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R: Ani Sinha <ani@anisinha.ca>
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S: Supported
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F: hw/acpi/viot.c
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F: hw/acpi/viot.h
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@@ -1659,8 +1659,8 @@ fi
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# vhost interdependencies and host support
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# vhost backends
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if test "$vhost_user" = "yes" && test "$linux" != "yes"; then
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error_exit "vhost-user is only available on Linux"
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if test "$vhost_user" = "yes" && test "$mingw32" = "yes"; then
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error_exit "vhost-user is not available on Windows"
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fi
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test "$vhost_vdpa" = "" && vhost_vdpa=$linux
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if test "$vhost_vdpa" = "yes" && test "$linux" != "yes"; then
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@@ -324,6 +324,14 @@ machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
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been implemented), so there is not much value added by this board. Use the
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``ref405ep`` machine instead.
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``pc-i440fx-1.4`` up to ``pc-i440fx-1.7`` (since 7.0)
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'''''''''''''''''''''''''''''''''''''''''''''''''''''
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These old machine types are quite neglected nowadays and thus might have
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various pitfalls with regards to live migration. Use a newer machine type
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instead.
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Backend options
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---------------
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@@ -38,6 +38,26 @@ conventions <backend_conventions>`.
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*Master* and *slave* can be either a client (i.e. connecting) or
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server (listening) in the socket communication.
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Support for platforms other than Linux
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--------------------------------------
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While vhost-user was initially developed targeting Linux, nowadays it
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is supported on any platform that provides the following features:
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- A way for requesting shared memory represented by a file descriptor
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so it can be passed over a UNIX domain socket and then mapped by the
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other process.
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- AF_UNIX sockets with SCM_RIGHTS, so QEMU and the other process can
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exchange messages through it, including ancillary data when needed.
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- Either eventfd or pipe/pipe2. On platforms where eventfd is not
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available, QEMU will automatically fall back to pipe2 or, as a last
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resort, pipe. Each file descriptor will be used for receiving or
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sending events by reading or writing (respectively) an 8-byte value
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to the corresponding it. The 8-value itself has no meaning and
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should not be interpreted.
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Message Specification
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=====================
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@@ -0,0 +1,115 @@
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PCI SR/IOV EMULATION SUPPORT
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============================
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Description
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===========
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SR/IOV (Single Root I/O Virtualization) is an optional extended capability
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of a PCI Express device. It allows a single physical function (PF) to appear as multiple
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virtual functions (VFs) for the main purpose of eliminating software
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overhead in I/O from virtual machines.
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Qemu now implements the basic common functionality to enable an emulated device
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to support SR/IOV. Yet no fully implemented devices exists in Qemu, but a
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proof-of-concept hack of the Intel igb can be found here:
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git://github.com/knuto/qemu.git sriov_patches_v5
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Implementation
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==============
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Implementing emulation of an SR/IOV capable device typically consists of
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implementing support for two types of device classes; the "normal" physical device
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(PF) and the virtual device (VF). From Qemu's perspective, the VFs are just
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like other devices, except that some of their properties are derived from
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the PF.
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A virtual function is different from a physical function in that the BAR
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space for all VFs are defined by the BAR registers in the PFs SR/IOV
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capability. All VFs have the same BARs and BAR sizes.
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Accesses to these virtual BARs then is computed as
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<VF BAR start> + <VF number> * <BAR sz> + <offset>
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From our emulation perspective this means that there is a separate call for
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setting up a BAR for a VF.
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1) To enable SR/IOV support in the PF, it must be a PCI Express device so
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you would need to add a PCI Express capability in the normal PCI
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capability list. You might also want to add an ARI (Alternative
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Routing-ID Interpretation) capability to indicate that your device
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supports functions beyond it's "own" function space (0-7),
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which is necessary to support more than 7 functions, or
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if functions extends beyond offset 7 because they are placed at an
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offset > 1 or have stride > 1.
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...
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#include "hw/pci/pcie.h"
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#include "hw/pci/pcie_sriov.h"
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pci_your_pf_dev_realize( ... )
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{
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...
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int ret = pcie_endpoint_cap_init(d, 0x70);
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...
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pcie_ari_init(d, 0x100, 1);
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...
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/* Add and initialize the SR/IOV capability */
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pcie_sriov_pf_init(d, 0x200, "your_virtual_dev",
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vf_devid, initial_vfs, total_vfs,
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fun_offset, stride);
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/* Set up individual VF BARs (parameters as for normal BARs) */
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pcie_sriov_pf_init_vf_bar( ... )
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...
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}
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|
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For cleanup, you simply call:
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pcie_sriov_pf_exit(device);
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which will delete all the virtual functions and associated resources.
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|
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2) Similarly in the implementation of the virtual function, you need to
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make it a PCI Express device and add a similar set of capabilities
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except for the SR/IOV capability. Then you need to set up the VF BARs as
|
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subregions of the PFs SR/IOV VF BARs by calling
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pcie_sriov_vf_register_bar() instead of the normal pci_register_bar() call:
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||||
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pci_your_vf_dev_realize( ... )
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{
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...
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int ret = pcie_endpoint_cap_init(d, 0x60);
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...
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pcie_ari_init(d, 0x100, 1);
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...
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memory_region_init(mr, ... )
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pcie_sriov_vf_register_bar(d, bar_nr, mr);
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...
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}
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Testing on Linux guest
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||||
======================
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The easiest is if your device driver supports sysfs based SR/IOV
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enabling. Support for this was added in kernel v.3.8, so not all drivers
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support it yet.
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||||
To enable 4 VFs for a device at 01:00.0:
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modprobe yourdriver
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echo 4 > /sys/bus/pci/devices/0000:01:00.0/sriov_numvfs
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You should now see 4 VFs with lspci.
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||||
To turn SR/IOV off again - the standard requires you to turn it off before you can enable
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another VF count, and the emulation enforces this:
|
||||
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||||
echo 0 > /sys/bus/pci/devices/0000:01:00.0/sriov_numvfs
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||||
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||||
Older drivers typically provide a max_vfs module parameter
|
||||
to enable it at load time:
|
||||
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||||
modprobe yourdriver max_vfs=4
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||||
|
||||
To disable the VFs again then, you simply have to unload the driver:
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||||
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||||
rmmod yourdriver
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||||
@@ -0,0 +1,200 @@
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||||
ACPI ERST DEVICE
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||||
================
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||||
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||||
The ACPI ERST device is utilized to support the ACPI Error Record
|
||||
Serialization Table, ERST, functionality. This feature is designed for
|
||||
storing error records in persistent storage for future reference
|
||||
and/or debugging.
|
||||
|
||||
The ACPI specification[1], in Chapter "ACPI Platform Error Interfaces
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||||
(APEI)", and specifically subsection "Error Serialization", outlines a
|
||||
method for storing error records into persistent storage.
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||||
|
||||
The format of error records is described in the UEFI specification[2],
|
||||
in Appendix N "Common Platform Error Record".
|
||||
|
||||
While the ACPI specification allows for an NVRAM "mode" (see
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||||
GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES) where non-volatile RAM is
|
||||
directly exposed for direct access by the OS/guest, this device
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||||
implements the non-NVRAM "mode". This non-NVRAM "mode" is what is
|
||||
implemented by most BIOS (since flash memory requires programming
|
||||
operations in order to update its contents). Furthermore, as of the
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||||
time of this writing, Linux only supports the non-NVRAM "mode".
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||||
|
||||
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||||
Background/Motivation
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||||
---------------------
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||||
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||||
Linux uses the persistent storage filesystem, pstore, to record
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information (eg. dmesg tail) upon panics and shutdowns. Pstore is
|
||||
independent of, and runs before, kdump. In certain scenarios (ie.
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hosts/guests with root filesystems on NFS/iSCSI where networking
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software and/or hardware fails, and thus kdump fails), pstore may
|
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contain information available for post-mortem debugging.
|
||||
|
||||
Two common storage backends for the pstore filesystem are ACPI ERST
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and UEFI. Most BIOS implement ACPI ERST. UEFI is not utilized in all
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guests. With QEMU supporting ACPI ERST, it becomes a viable pstore
|
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storage backend for virtual machines (as it is now for bare metal
|
||||
machines).
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||||
|
||||
Enabling support for ACPI ERST facilitates a consistent method to
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||||
capture kernel panic information in a wide range of guests: from
|
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resource-constrained microvms to very large guests, and in particular,
|
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in direct-boot environments (which would lack UEFI run-time services).
|
||||
|
||||
Note that Microsoft Windows also utilizes the ACPI ERST for certain
|
||||
crash information, if available[3].
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||||
|
||||
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Configuration|Usage
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||||
-------------------
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||||
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||||
To use ACPI ERST, a memory-backend-file object and acpi-erst device
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||||
can be created, for example:
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||||
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||||
qemu ...
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-object memory-backend-file,id=erstnvram,mem-path=acpi-erst.backing,size=0x10000,share=on \
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-device acpi-erst,memdev=erstnvram
|
||||
|
||||
For proper operation, the ACPI ERST device needs a memory-backend-file
|
||||
object with the following parameters:
|
||||
|
||||
- id: The id of the memory-backend-file object is used to associate
|
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this memory with the acpi-erst device.
|
||||
- size: The size of the ACPI ERST backing storage. This parameter is
|
||||
required.
|
||||
- mem-path: The location of the ACPI ERST backing storage file. This
|
||||
parameter is also required.
|
||||
- share: The share=on parameter is required so that updates to the
|
||||
ERST backing store are written to the file.
|
||||
|
||||
and ERST device:
|
||||
|
||||
- memdev: Is the object id of the memory-backend-file.
|
||||
- record_size: Specifies the size of the records (or slots) in the
|
||||
backend storage. Must be a power of two value greater than or
|
||||
equal to 4096 (PAGE_SIZE).
|
||||
|
||||
|
||||
PCI Interface
|
||||
-------------
|
||||
|
||||
The ERST device is a PCI device with two BARs, one for accessing the
|
||||
programming registers, and the other for accessing the record exchange
|
||||
buffer.
|
||||
|
||||
BAR0 contains the programming interface consisting of ACTION and VALUE
|
||||
64-bit registers. All ERST actions/operations/side effects happen on
|
||||
the write to the ACTION, by design. Any data needed by the action must
|
||||
be placed into VALUE prior to writing ACTION. Reading the VALUE
|
||||
simply returns the register contents, which can be updated by a
|
||||
previous ACTION.
|
||||
|
||||
BAR1 contains the 8KiB record exchange buffer, which is the
|
||||
implemented maximum record size.
|
||||
|
||||
|
||||
Backend Storage Format
|
||||
----------------------
|
||||
|
||||
The backend storage is divided into fixed size "slots", 8KiB in
|
||||
length, with each slot storing a single record. Not all slots need to
|
||||
be occupied, and they need not be occupied in a contiguous fashion.
|
||||
The ability to clear/erase specific records allows for the formation
|
||||
of unoccupied slots.
|
||||
|
||||
Slot 0 contains a backend storage header that identifies the contents
|
||||
as ERST and also facilitates efficient access to the records.
|
||||
Depending upon the size of the backend storage, additional slots will
|
||||
be designated to be a part of the slot 0 header. For example, at 8KiB,
|
||||
the slot 0 header can accomodate 1021 records. Thus a storage size
|
||||
of 8MiB (8KiB * 1024) requires an additional slot for use by the
|
||||
header. In this scenario, slot 0 and slot 1 form the backend storage
|
||||
header, and records can be stored starting at slot 2.
|
||||
|
||||
Below is an example layout of the backend storage format (for storage
|
||||
size less than 8MiB). The size of the storage is a multiple of 8KiB,
|
||||
and contains N number of slots to store records. The example below
|
||||
shows two records (in CPER format) in the backend storage, while the
|
||||
remaining slots are empty/available.
|
||||
|
||||
::
|
||||
|
||||
Slot Record
|
||||
<------------------ 8KiB -------------------->
|
||||
+--------------------------------------------+
|
||||
0 | storage header |
|
||||
+--------------------------------------------+
|
||||
1 | empty/available |
|
||||
+--------------------------------------------+
|
||||
2 | CPER |
|
||||
+--------------------------------------------+
|
||||
3 | CPER |
|
||||
+--------------------------------------------+
|
||||
... | |
|
||||
+--------------------------------------------+
|
||||
N | empty/available |
|
||||
+--------------------------------------------+
|
||||
|
||||
The storage header consists of some basic information and an array
|
||||
of CPER record_id's to efficiently access records in the backend
|
||||
storage.
|
||||
|
||||
All fields in the header are stored in little endian format.
|
||||
|
||||
::
|
||||
|
||||
+--------------------------------------------+
|
||||
| magic | 0x0000
|
||||
+--------------------------------------------+
|
||||
| record_offset | record_size | 0x0008
|
||||
+--------------------------------------------+
|
||||
| record_count | reserved | version | 0x0010
|
||||
+--------------------------------------------+
|
||||
| record_id[0] | 0x0018
|
||||
+--------------------------------------------+
|
||||
| record_id[1] | 0x0020
|
||||
+--------------------------------------------+
|
||||
| record_id[...] |
|
||||
+--------------------------------------------+
|
||||
| record_id[N] | 0x1FF8
|
||||
+--------------------------------------------+
|
||||
|
||||
The 'magic' field contains the value 0x524F545354535245.
|
||||
|
||||
The 'record_size' field contains the value 0x2000, 8KiB.
|
||||
|
||||
The 'record_offset' field points to the first record_id in the array,
|
||||
0x0018.
|
||||
|
||||
The 'version' field contains 0x0100, the first version.
|
||||
|
||||
The 'record_count' field contains the number of valid records in the
|
||||
backend storage.
|
||||
|
||||
The 'record_id' array fields are the 64-bit record identifiers of the
|
||||
CPER record in the corresponding slot. Stated differently, the
|
||||
location of a CPER record_id in the record_id[] array provides the
|
||||
slot index for the corresponding record in the backend storage.
|
||||
|
||||
Note that, for example, with a backend storage less than 8MiB, slot 0
|
||||
contains the header, so the record_id[0] will never contain a valid
|
||||
CPER record_id. Instead slot 1 is the first available slot and thus
|
||||
record_id_[1] may contain a CPER.
|
||||
|
||||
A 'record_id' of all 0s or all 1s indicates an invalid record (ie. the
|
||||
slot is available).
|
||||
|
||||
|
||||
References
|
||||
----------
|
||||
|
||||
[1] "Advanced Configuration and Power Interface Specification",
|
||||
version 4.0, June 2009.
|
||||
|
||||
[2] "Unified Extensible Firmware Interface Specification",
|
||||
version 2.1, October 2008.
|
||||
|
||||
[3] "Windows Hardware Error Architecture", specfically
|
||||
"Error Record Persistence Mechanism".
|
||||
@@ -18,4 +18,5 @@ guest hardware that is specific to QEMU.
|
||||
acpi_mem_hotplug
|
||||
acpi_pci_hotplug
|
||||
acpi_nvdimm
|
||||
acpi_erst
|
||||
sev-guest-firmware
|
||||
|
||||
@@ -65,6 +65,7 @@ PCI devices (other than virtio):
|
||||
1b36:000f mdpy (mdev sample device), linux/samples/vfio-mdev/mdpy.c
|
||||
1b36:0010 PCIe NVMe device (-device nvme)
|
||||
1b36:0011 PCI PVPanic device (-device pvpanic-pci)
|
||||
1b36:0012 PCI ACPI ERST device (-device acpi-erst)
|
||||
|
||||
All these devices are documented in docs/specs.
|
||||
|
||||
|
||||
+7
-1
@@ -2152,7 +2152,13 @@ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f,
|
||||
build_append_int_noprefix(tbl, 0, 1); /* DAY_ALRM */
|
||||
build_append_int_noprefix(tbl, 0, 1); /* MON_ALRM */
|
||||
build_append_int_noprefix(tbl, f->rtc_century, 1); /* CENTURY */
|
||||
build_append_int_noprefix(tbl, 0, 2); /* IAPC_BOOT_ARCH */
|
||||
/* IAPC_BOOT_ARCH */
|
||||
if (f->rev == 1) {
|
||||
build_append_int_noprefix(tbl, 0, 2);
|
||||
} else {
|
||||
/* since ACPI v2.0 */
|
||||
build_append_int_noprefix(tbl, f->iapc_boot_arch, 2);
|
||||
}
|
||||
build_append_int_noprefix(tbl, 0, 1); /* Reserved */
|
||||
build_append_int_noprefix(tbl, f->flags, 4); /* Flags */
|
||||
|
||||
|
||||
@@ -80,11 +80,6 @@
|
||||
#define UEFI_CPER_RECORD_MIN_SIZE 128U
|
||||
#define UEFI_CPER_RECORD_LENGTH_OFFSET 20U
|
||||
#define UEFI_CPER_RECORD_ID_OFFSET 96U
|
||||
#define IS_UEFI_CPER_RECORD(ptr) \
|
||||
(((ptr)[0] == 'C') && \
|
||||
((ptr)[1] == 'P') && \
|
||||
((ptr)[2] == 'E') && \
|
||||
((ptr)[3] == 'R'))
|
||||
|
||||
/*
|
||||
* NOTE that when accessing CPER fields within a record, memcpy()
|
||||
|
||||
+11
-1
@@ -32,6 +32,7 @@
|
||||
#include "hw/pci/pci_bridge.h"
|
||||
#include "hw/pci/pci_host.h"
|
||||
#include "hw/pci/pcie_port.h"
|
||||
#include "hw/pci-bridge/xio3130_downstream.h"
|
||||
#include "hw/i386/acpi-build.h"
|
||||
#include "hw/acpi/acpi.h"
|
||||
#include "hw/pci/pci_bus.h"
|
||||
@@ -336,6 +337,8 @@ void acpi_pcihp_device_plug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
|
||||
{
|
||||
PCIDevice *pdev = PCI_DEVICE(dev);
|
||||
int slot = PCI_SLOT(pdev->devfn);
|
||||
PCIDevice *bridge;
|
||||
PCIBus *bus;
|
||||
int bsel;
|
||||
|
||||
/* Don't send event when device is enabled during qemu machine creation:
|
||||
@@ -365,7 +368,14 @@ void acpi_pcihp_device_plug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
|
||||
return;
|
||||
}
|
||||
|
||||
bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev));
|
||||
bus = pci_get_bus(pdev);
|
||||
bridge = pci_bridge_get_device(bus);
|
||||
if (object_dynamic_cast(OBJECT(bridge), TYPE_PCIE_ROOT_PORT) ||
|
||||
object_dynamic_cast(OBJECT(bridge), TYPE_XIO3130_DOWNSTREAM)) {
|
||||
pcie_cap_slot_enable_power(bridge);
|
||||
}
|
||||
|
||||
bsel = acpi_pcihp_get_bsel(bus);
|
||||
g_assert(bsel >= 0);
|
||||
s->acpi_pcihp_pci_status[bsel].up |= (1U << slot);
|
||||
acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
|
||||
|
||||
@@ -38,6 +38,7 @@
|
||||
#include "hw/nvram/fw_cfg.h"
|
||||
#include "hw/acpi/bios-linker-loader.h"
|
||||
#include "hw/isa/isa.h"
|
||||
#include "hw/input/i8042.h"
|
||||
#include "hw/block/fdc.h"
|
||||
#include "hw/acpi/memory_hotplug.h"
|
||||
#include "sysemu/tpm.h"
|
||||
@@ -192,6 +193,13 @@ static void init_common_fadt_data(MachineState *ms, Object *o,
|
||||
.address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
|
||||
* Flags, bit offset 1 - 8042.
|
||||
*/
|
||||
fadt.iapc_boot_arch = iapc_boot_arch_8042();
|
||||
|
||||
*data = fadt;
|
||||
}
|
||||
|
||||
|
||||
@@ -37,6 +37,7 @@
|
||||
#include "hw/pci/pcie_host.h"
|
||||
#include "hw/usb/xhci.h"
|
||||
#include "hw/virtio/virtio-mmio.h"
|
||||
#include "hw/input/i8042.h"
|
||||
|
||||
#include "acpi-common.h"
|
||||
#include "acpi-microvm.h"
|
||||
@@ -187,6 +188,11 @@ static void acpi_build_microvm(AcpiBuildTables *tables,
|
||||
.address = GED_MMIO_BASE_REGS + ACPI_GED_REG_RESET,
|
||||
},
|
||||
.reset_val = ACPI_GED_RESET_VALUE,
|
||||
/*
|
||||
* ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
|
||||
* Flags, bit offset 1 - 8042.
|
||||
*/
|
||||
.iapc_boot_arch = iapc_boot_arch_8042(),
|
||||
};
|
||||
|
||||
table_offsets = g_array_new(false, true /* clear */,
|
||||
|
||||
+13
-1
@@ -3030,6 +3030,13 @@ static int vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu,
|
||||
VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
|
||||
IntelIOMMUState *s = vtd_as->iommu_state;
|
||||
|
||||
/* TODO: add support for VFIO and vhost users */
|
||||
if (s->snoop_control) {
|
||||
error_setg_errno(errp, -ENOTSUP,
|
||||
"Snoop Control with vhost or VFIO is not supported");
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Update per-address-space notifier flags */
|
||||
vtd_as->notifier_flags = new;
|
||||
|
||||
@@ -3113,6 +3120,7 @@ static Property vtd_properties[] = {
|
||||
VTD_HOST_ADDRESS_WIDTH),
|
||||
DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
|
||||
DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
|
||||
DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),
|
||||
DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
@@ -3643,7 +3651,7 @@ static void vtd_init(IntelIOMMUState *s)
|
||||
vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
|
||||
x86_iommu->dt_supported);
|
||||
|
||||
if (s->scalable_mode) {
|
||||
if (s->scalable_mode || s->snoop_control) {
|
||||
vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
|
||||
vtd_spte_rsvd_large[2] &= ~VTD_SPTE_SNP;
|
||||
vtd_spte_rsvd_large[3] &= ~VTD_SPTE_SNP;
|
||||
@@ -3674,6 +3682,10 @@ static void vtd_init(IntelIOMMUState *s)
|
||||
s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
|
||||
}
|
||||
|
||||
if (s->snoop_control) {
|
||||
s->ecap |= VTD_ECAP_SC;
|
||||
}
|
||||
|
||||
vtd_reset_caches(s);
|
||||
|
||||
/* Define registers with default values and bit semantics */
|
||||
|
||||
@@ -188,6 +188,7 @@
|
||||
#define VTD_ECAP_IR (1ULL << 3)
|
||||
#define VTD_ECAP_EIM (1ULL << 4)
|
||||
#define VTD_ECAP_PT (1ULL << 6)
|
||||
#define VTD_ECAP_SC (1ULL << 7)
|
||||
#define VTD_ECAP_MHMV (15ULL << 20)
|
||||
#define VTD_ECAP_SRS (1ULL << 31)
|
||||
#define VTD_ECAP_SMTS (1ULL << 43)
|
||||
|
||||
+26
-4
@@ -318,8 +318,6 @@ GlobalProperty pc_compat_2_0[] = {
|
||||
{ "pci-serial-4x", "prog_if", "0" },
|
||||
{ "virtio-net-pci", "guest_announce", "off" },
|
||||
{ "ICH9-LPC", "memory-hotplug-support", "off" },
|
||||
{ "xio3130-downstream", COMPAT_PROP_PCP, "off" },
|
||||
{ "ioh3420", COMPAT_PROP_PCP, "off" },
|
||||
};
|
||||
const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
|
||||
|
||||
@@ -1014,7 +1012,8 @@ static const MemoryRegionOps ioportF0_io_ops = {
|
||||
},
|
||||
};
|
||||
|
||||
static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
|
||||
static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
|
||||
bool create_i8042, bool no_vmport)
|
||||
{
|
||||
int i;
|
||||
DriveInfo *fd[MAX_FD];
|
||||
@@ -1036,6 +1035,10 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
|
||||
}
|
||||
}
|
||||
|
||||
if (!create_i8042) {
|
||||
return;
|
||||
}
|
||||
|
||||
i8042 = isa_create_simple(isa_bus, "i8042");
|
||||
if (!no_vmport) {
|
||||
isa_create_simple(isa_bus, TYPE_VMPORT);
|
||||
@@ -1131,7 +1134,8 @@ void pc_basic_device_init(struct PCMachineState *pcms,
|
||||
i8257_dma_init(isa_bus, 0);
|
||||
|
||||
/* Super I/O */
|
||||
pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON);
|
||||
pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
|
||||
pcms->vmport != ON_OFF_AUTO_ON);
|
||||
}
|
||||
|
||||
void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
|
||||
@@ -1512,6 +1516,20 @@ static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
|
||||
pcms->hpet_enabled = value;
|
||||
}
|
||||
|
||||
static bool pc_machine_get_i8042(Object *obj, Error **errp)
|
||||
{
|
||||
PCMachineState *pcms = PC_MACHINE(obj);
|
||||
|
||||
return pcms->i8042_enabled;
|
||||
}
|
||||
|
||||
static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
|
||||
{
|
||||
PCMachineState *pcms = PC_MACHINE(obj);
|
||||
|
||||
pcms->i8042_enabled = value;
|
||||
}
|
||||
|
||||
static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
|
||||
{
|
||||
PCMachineState *pcms = PC_MACHINE(obj);
|
||||
@@ -1641,6 +1659,7 @@ static void pc_machine_initfn(Object *obj)
|
||||
pcms->smbus_enabled = true;
|
||||
pcms->sata_enabled = true;
|
||||
pcms->pit_enabled = true;
|
||||
pcms->i8042_enabled = true;
|
||||
pcms->max_fw_size = 8 * MiB;
|
||||
#ifdef CONFIG_HPET
|
||||
pcms->hpet_enabled = true;
|
||||
@@ -1777,6 +1796,9 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
|
||||
object_class_property_set_description(oc, "hpet",
|
||||
"Enable/disable high precision event timer emulation");
|
||||
|
||||
object_class_property_add_bool(oc, PC_MACHINE_I8042,
|
||||
pc_machine_get_i8042, pc_machine_set_i8042);
|
||||
|
||||
object_class_property_add_bool(oc, "default-bus-bypass-iommu",
|
||||
pc_machine_get_default_bus_bypass_iommu,
|
||||
pc_machine_set_default_bus_bypass_iommu);
|
||||
|
||||
@@ -757,6 +757,7 @@ static void pc_i440fx_1_7_machine_options(MachineClass *m)
|
||||
m->hw_version = "1.7.0";
|
||||
m->default_machine_opts = NULL;
|
||||
m->option_rom_has_mr = true;
|
||||
m->deprecation_reason = "old and unattended - use a newer version instead";
|
||||
compat_props_add(m->compat_props, pc_compat_1_7, pc_compat_1_7_len);
|
||||
pcmc->smbios_defaults = false;
|
||||
pcmc->gigabyte_align = false;
|
||||
|
||||
+1
-15
@@ -83,24 +83,11 @@ inline void init_topo_info(X86CPUTopoInfo *topo_info,
|
||||
uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
|
||||
unsigned int cpu_index)
|
||||
{
|
||||
X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
|
||||
X86CPUTopoInfo topo_info;
|
||||
uint32_t correct_id;
|
||||
static bool warned;
|
||||
|
||||
init_topo_info(&topo_info, x86ms);
|
||||
|
||||
correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);
|
||||
if (x86mc->compat_apic_id_mode) {
|
||||
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
|
||||
error_report("APIC IDs set in compatibility mode, "
|
||||
"CPU topology won't match the configuration");
|
||||
warned = true;
|
||||
}
|
||||
return cpu_index;
|
||||
} else {
|
||||
return correct_id;
|
||||
}
|
||||
return x86_apicid_from_cpu_idx(&topo_info, cpu_index);
|
||||
}
|
||||
|
||||
|
||||
@@ -1330,7 +1317,6 @@ static void x86_machine_class_init(ObjectClass *oc, void *data)
|
||||
mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
|
||||
mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
|
||||
mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
|
||||
x86mc->compat_apic_id_mode = false;
|
||||
x86mc->save_tsc_khz = true;
|
||||
x86mc->fwcfg_dma_enabled = true;
|
||||
nc->nmi_monitor_handler = x86_nmi;
|
||||
|
||||
@@ -21,6 +21,7 @@
|
||||
#include "hw/misc/pvpanic.h"
|
||||
#include "qom/object.h"
|
||||
#include "hw/isa/isa.h"
|
||||
#include "standard-headers/linux/pvpanic.h"
|
||||
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(PVPanicISAState, PVPANIC_ISA_DEVICE)
|
||||
|
||||
@@ -64,7 +65,8 @@ static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
|
||||
|
||||
static Property pvpanic_isa_properties[] = {
|
||||
DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicISAState, ioport, 0x505),
|
||||
DEFINE_PROP_UINT8("events", PVPanicISAState, pvpanic.events, PVPANIC_PANICKED | PVPANIC_CRASHLOADED),
|
||||
DEFINE_PROP_UINT8("events", PVPanicISAState, pvpanic.events,
|
||||
PVPANIC_PANICKED | PVPANIC_CRASH_LOADED),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
|
||||
@@ -21,6 +21,7 @@
|
||||
#include "hw/misc/pvpanic.h"
|
||||
#include "qom/object.h"
|
||||
#include "hw/pci/pci.h"
|
||||
#include "standard-headers/linux/pvpanic.h"
|
||||
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(PVPanicPCIState, PVPANIC_PCI_DEVICE)
|
||||
|
||||
@@ -53,7 +54,8 @@ static void pvpanic_pci_realizefn(PCIDevice *dev, Error **errp)
|
||||
}
|
||||
|
||||
static Property pvpanic_pci_properties[] = {
|
||||
DEFINE_PROP_UINT8("events", PVPanicPCIState, pvpanic.events, PVPANIC_PANICKED | PVPANIC_CRASHLOADED),
|
||||
DEFINE_PROP_UINT8("events", PVPanicPCIState, pvpanic.events,
|
||||
PVPANIC_PANICKED | PVPANIC_CRASH_LOADED),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user