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sysbus: apic: ioapic: convert to QEMU Object Model

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This converts three devices because apic and ioapic are subclasses of sysbus.
Converting subclasses independently of their base class is prohibitively hard.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori
2012-01-27 10:50:50 -06:00
parent 40021f0888
commit 999e12bbe8
131 changed files with 2734 additions and 1297 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/a9mpcore.c
+14 -7
View File
@@ -208,13 +208,20 @@ static const VMStateDescription vmstate_a9mp_priv = {
}
};
static SysBusDeviceInfo a9mp_priv_info = {
.init = a9mp_priv_init,
.qdev.name = "a9mpcore_priv",
.qdev.size = sizeof(a9mp_priv_state),
.qdev.vmsd = &vmstate_a9mp_priv,
.qdev.reset = a9mp_priv_reset,
.qdev.props = (Property[]) {
static void a9mp_priv_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = a9mp_priv_init;
}
static DeviceInfo a9mp_priv_info = {
.name = "a9mpcore_priv",
.size = sizeof(a9mp_priv_state),
.vmsd = &vmstate_a9mp_priv,
.reset = a9mp_priv_reset,
.class_init = a9mp_priv_class_init,
.props = (Property[]) {
DEFINE_PROP_UINT32("num-cpu", a9mp_priv_state, num_cpu, 1),
/* The Cortex-A9MP may have anything from 0 to 224 external interrupt
* IRQ lines (with another 32 internal). We default to 64+32, which
hw/alpha_typhoon.c
+12 -5
View File
@@ -808,11 +808,18 @@ static int typhoon_pcihost_init(SysBusDevice *dev)
return 0;
}
static SysBusDeviceInfo typhoon_pcihost_info = {
.init = typhoon_pcihost_init,
.qdev.name = "typhoon-pcihost",
.qdev.size = sizeof(TyphoonState),
.qdev.no_user = 1
static void typhoon_pcihost_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = typhoon_pcihost_init;
}
static DeviceInfo typhoon_pcihost_info = {
.name = "typhoon-pcihost",
.size = sizeof(TyphoonState),
.no_user = 1,
.class_init = typhoon_pcihost_class_init,
};
static void typhoon_register(void)
hw/apb_pci.c
+12 -5
View File
@@ -453,11 +453,18 @@ static DeviceInfo pbm_pci_host_info = {
.class_init = pbm_pci_host_class_init,
};
static SysBusDeviceInfo pbm_host_info = {
.qdev.name = "pbm",
.qdev.size = sizeof(APBState),
.qdev.reset = pci_pbm_reset,
.init = pci_pbm_init_device,
static void pbm_host_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pci_pbm_init_device;
}
static DeviceInfo pbm_host_info = {
.name = "pbm",
.size = sizeof(APBState),
.reset = pci_pbm_reset,
.class_init = pbm_host_class_init,
};
static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
hw/apic.c
+14 -7
View File
@@ -763,13 +763,20 @@ static void apic_init(APICCommonState *s)
local_apics[s->idx] = s;
}
static APICCommonInfo apic_info = {
.busdev.qdev.name = "apic",
.init = apic_init,
.set_base = apic_set_base,
.set_tpr = apic_set_tpr,
.external_nmi = apic_external_nmi,
.post_load = apic_post_load,
static void apic_class_init(ObjectClass *klass, void *data)
{
APICCommonClass *k = APIC_COMMON_CLASS(klass);
k->init = apic_init;
k->set_base = apic_set_base;
k->set_tpr = apic_set_tpr;
k->external_nmi = apic_external_nmi;
k->post_load = apic_post_load;
}
static DeviceInfo apic_info = {
.name = "apic",
.class_init = apic_class_init,
};
static void apic_register_devices(void)
hw/apic_common.c
+57 -33
View File
@@ -25,35 +25,40 @@ static int apic_irq_delivered;
void cpu_set_apic_base(DeviceState *d, uint64_t val)
{
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
APICCommonInfo *info;
trace_cpu_set_apic_base(val);
if (s) {
info = DO_UPCAST(APICCommonInfo, busdev.qdev, qdev_get_info(&s->busdev.qdev));
if (d) {
APICCommonState *s = APIC_COMMON(d);
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
info->set_base(s, val);
}
}
uint64_t cpu_get_apic_base(DeviceState *d)
{
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase : 0);
return s ? s->apicbase : 0;
if (d) {
APICCommonState *s = APIC_COMMON(d);
trace_cpu_get_apic_base((uint64_t)s->apicbase);
return s->apicbase;
} else {
trace_cpu_get_apic_base(0);
return 0;
}
}
void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
{
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
APICCommonInfo *info;
APICCommonState *s;
APICCommonClass *info;
if (s) {
info = DO_UPCAST(APICCommonInfo, busdev.qdev, qdev_get_info(&s->busdev.qdev));
info->set_tpr(s, val);
if (!d) {
return;
}
s = APIC_COMMON(d);
info = APIC_COMMON_GET_CLASS(s);
info->set_tpr(s, val);
}
uint8_t cpu_get_apic_tpr(DeviceState *d)
@@ -86,10 +91,9 @@ int apic_get_irq_delivered(void)
void apic_deliver_nmi(DeviceState *d)
{
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
APICCommonInfo *info;
APICCommonState *s = APIC_COMMON(d);
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
info = DO_UPCAST(APICCommonInfo, busdev.qdev, qdev_get_info(&s->busdev.qdev));
info->external_nmi(s);
}
@@ -223,8 +227,8 @@ static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
static int apic_init_common(SysBusDevice *dev)
{
APICCommonState *s = FROM_SYSBUS(APICCommonState, dev);
APICCommonInfo *info;
APICCommonState *s = APIC_COMMON(dev);
APICCommonClass *info;
static int apic_no;
if (apic_no >= MAX_APICS) {
@@ -232,7 +236,7 @@ static int apic_init_common(SysBusDevice *dev)
}
s->idx = apic_no++;
info = DO_UPCAST(APICCommonInfo, busdev.qdev, qdev_get_info(&s->busdev.qdev));
info = APIC_COMMON_GET_CLASS(s);
info->init(s);
sysbus_init_mmio(&s->busdev, &s->io_memory);
@@ -241,9 +245,8 @@ static int apic_init_common(SysBusDevice *dev)
static int apic_dispatch_post_load(void *opaque, int version_id)
{
APICCommonState *s = opaque;
APICCommonInfo *info =
DO_UPCAST(APICCommonInfo, busdev.qdev, qdev_get_info(&s->busdev.qdev));
APICCommonState *s = APIC_COMMON(opaque);
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
if (info->post_load) {
info->post_load(s);
@@ -289,14 +292,35 @@ static Property apic_properties_common[] = {
DEFINE_PROP_END_OF_LIST(),
};
void apic_qdev_register(APICCommonInfo *info)
static void apic_common_class_init(ObjectClass *klass, void *data)
{
info->busdev.init = apic_init_common;
info->busdev.qdev.size = sizeof(APICCommonState),
info->busdev.qdev.vmsd = &vmstate_apic_common;
info->busdev.qdev.reset = apic_reset_common;
info->busdev.qdev.no_user = 1;
info->busdev.qdev.props = apic_properties_common;
sysbus_register_withprop(&info->busdev);
SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
sc->init = apic_init_common;
}
static TypeInfo apic_common_type = {
.name = TYPE_APIC_COMMON,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(APICCommonState),
.class_size = sizeof(APICCommonClass),
.class_init = apic_common_class_init,
.abstract = true,
};
void apic_qdev_register(DeviceInfo *info)
{
info->size = sizeof(APICCommonState),
info->vmsd = &vmstate_apic_common;
info->reset = apic_reset_common;
info->no_user = 1;
info->props = apic_properties_common;
sysbus_qdev_register_subclass(info, TYPE_APIC_COMMON);
}
static void register_devices(void)
{
type_register_static(&apic_common_type);
}
device_init(register_devices);
hw/apic_internal.h
+20 -12
View File
@@ -67,6 +67,25 @@
typedef struct APICCommonState APICCommonState;
#define TYPE_APIC_COMMON "apic-common"
#define APIC_COMMON(obj) \
OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC_COMMON)
#define APIC_COMMON_CLASS(klass) \
OBJECT_CLASS_CHECK(APICCommonClass, (klass), TYPE_APIC_COMMON)
#define APIC_COMMON_GET_CLASS(obj) \
OBJECT_GET_CLASS(APICCommonClass, (obj), TYPE_APIC_COMMON)
typedef struct APICCommonClass
{
SysBusDeviceClass parent_class;
void (*init)(APICCommonState *s);
void (*set_base)(APICCommonState *s, uint64_t val);
void (*set_tpr)(APICCommonState *s, uint8_t val);
void (*external_nmi)(APICCommonState *s);
void (*post_load)(APICCommonState *s);
} APICCommonClass;
struct APICCommonState {
SysBusDevice busdev;
MemoryRegion io_memory;
@@ -97,19 +116,8 @@ struct APICCommonState {
int wait_for_sipi;
};
typedef struct APICCommonInfo APICCommonInfo;
struct APICCommonInfo {
SysBusDeviceInfo busdev;
void (*init)(APICCommonState *s);
void (*set_base)(APICCommonState *s, uint64_t val);
void (*set_tpr)(APICCommonState *s, uint8_t val);
void (*external_nmi)(APICCommonState *s);
void (*post_load)(APICCommonState *s);
};
void apic_report_irq_delivered(int delivered);
void apic_qdev_register(APICCommonInfo *info);
void apic_qdev_register(DeviceInfo *info);
bool apic_next_timer(APICCommonState *s, int64_t current_time);
#endif /* !QEMU_APIC_INTERNAL_H */
hw/arm11mpcore.c
+43 -25
View File
@@ -201,33 +201,51 @@ static int realview_mpcore_init(SysBusDevice *dev)
return 0;
}
static SysBusDeviceInfo mpcore_rirq_info = {
.init = realview_mpcore_init,
.qdev.name = "realview_mpcore",
.qdev.size = sizeof(mpcore_rirq_state),
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
DEFINE_PROP_END_OF_LIST(),
}
static Property mpcore_rirq_properties[] = {
DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
/* The ARM11 MPCORE TRM says the on-chip controller may have
* anything from 0 to 224 external interrupt IRQ lines (with another
* 32 internal). We default to 32+32, which is the number provided by
* the ARM11 MPCore test chip in the Realview Versatile Express
* coretile. Other boards may differ and should set this property
* appropriately. Some Linux kernels may not boot if the hardware
* has more IRQ lines than the kernel expects.
*/
DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64),
DEFINE_PROP_END_OF_LIST(),
};
static SysBusDeviceInfo mpcore_priv_info = {
.init = mpcore_priv_init,
.qdev.name = "arm11mpcore_priv",
.qdev.size = sizeof(mpcore_priv_state),
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
/* The ARM11 MPCORE TRM says the on-chip controller may have
* anything from 0 to 224 external interrupt IRQ lines (with another
* 32 internal). We default to 32+32, which is the number provided by
* the ARM11 MPCore test chip in the Realview Versatile Express
* coretile. Other boards may differ and should set this property
* appropriately. Some Linux kernels may not boot if the hardware
* has more IRQ lines than the kernel expects.
*/
DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64),
DEFINE_PROP_END_OF_LIST(),
}
static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = realview_mpcore_init;
}
static DeviceInfo mpcore_rirq_info = {
.name = "realview_mpcore",
.size = sizeof(mpcore_rirq_state),
.props = mpcore_rirq_properties,
.class_init = mpcore_rirq_class_init,
};
static Property mpcore_priv_properties[] = {
DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
DEFINE_PROP_END_OF_LIST(),
};
static void mpcore_priv_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = mpcore_priv_init;
}
static DeviceInfo mpcore_priv_info = {
.name = "arm11mpcore_priv",
.size = sizeof(mpcore_priv_state),
.props = mpcore_priv_properties,
.class_init = mpcore_priv_class_init,
};
static void arm11mpcore_register_devices(void)
hw/arm_l2x0.c
+16 -9
View File
@@ -160,22 +160,29 @@ static int l2x0_priv_init(SysBusDevice *dev)
return 0;
}
static SysBusDeviceInfo l2x0_info = {
.init = l2x0_priv_init,
.qdev.name = "l2x0",
.qdev.size = sizeof(l2x0_state),
.qdev.vmsd = &vmstate_l2x0,
.qdev.no_user = 1,
.qdev.props = (Property[]) {
static void l2x0_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = l2x0_priv_init;
}
static DeviceInfo l2x0_info = {
.name = "l2x0",
.size = sizeof(l2x0_state),
.vmsd = &vmstate_l2x0,
.no_user = 1,
.props = (Property[]) {
DEFINE_PROP_UINT32("type", l2x0_state, cache_type, 0x1c100100),
DEFINE_PROP_END_OF_LIST(),
},
.qdev.reset = l2x0_priv_reset,
.reset = l2x0_priv_reset,
.class_init = l2x0_class_init,
};
static void l2x0_register_device(void)
{
sysbus_register_withprop(&l2x0_info);
sysbus_qdev_register(&l2x0_info);
}
device_init(l2x0_register_device)
hw/arm_mptimer.c
+15 -8
View File
@@ -311,14 +311,21 @@ static const VMStateDescription vmstate_arm_mptimer = {
}
};
static SysBusDeviceInfo arm_mptimer_info = {
.init = arm_mptimer_init,
.qdev.name = "arm_mptimer",
.qdev.size = sizeof(arm_mptimer_state),
.qdev.vmsd = &vmstate_arm_mptimer,
.qdev.reset = arm_mptimer_reset,
.qdev.no_user = 1,
.qdev.props = (Property[]) {
static void arm_mptimer_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
sbc->init = arm_mptimer_init;
}
static DeviceInfo arm_mptimer_info = {
.name = "arm_mptimer",
.size = sizeof(arm_mptimer_state),
.vmsd = &vmstate_arm_mptimer,
.reset = arm_mptimer_reset,
.no_user = 1,
.class_init = arm_mptimer_class_init,
.props = (Property[]) {
DEFINE_PROP_UINT32("num-cpu", arm_mptimer_state, num_cpu, 0),
DEFINE_PROP_END_OF_LIST()
}
hw/arm_sysctl.c
+20 -11
View File
@@ -401,17 +401,26 @@ void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
}
static SysBusDeviceInfo arm_sysctl_info = {
.init = arm_sysctl_init1,
.qdev.name = "realview_sysctl",
.qdev.size = sizeof(arm_sysctl_state),
.qdev.vmsd = &vmstate_arm_sysctl,
.qdev.reset = arm_sysctl_reset,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
DEFINE_PROP_END_OF_LIST(),
}
static Property arm_sysctl_properties[] = {
DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void arm_sysctl_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = arm_sysctl_init1;
}
static DeviceInfo arm_sysctl_info = {
.name = "realview_sysctl",
.size = sizeof(arm_sysctl_state),
.vmsd = &vmstate_arm_sysctl,
.reset = arm_sysctl_reset,
.props = arm_sysctl_properties,
.class_init = arm_sysctl_class_init,
};
static void arm_sysctl_register_devices(void)
hw/arm_timer.c
+33 -13
View File
@@ -283,17 +283,6 @@ static int sp804_init(SysBusDevice *dev)
return 0;
}
static SysBusDeviceInfo sp804_info = {
.init = sp804_init,
.qdev.name = "sp804",
.qdev.size = sizeof(sp804_state),
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("freq0", sp804_state, freq0, 1000000),
DEFINE_PROP_UINT32("freq1", sp804_state, freq1, 1000000),
DEFINE_PROP_END_OF_LIST(),
}
};
/* Integrator/CP timer module. */
typedef struct {
@@ -358,10 +347,41 @@ static int icp_pit_init(SysBusDevice *dev)
return 0;
}
static void icp_pit_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
sdc->init = icp_pit_init;
}
static DeviceInfo icp_pit_info = {
.name = "integrator_pit",
.size = sizeof(icp_pit_state),
.class_init = icp_pit_class_init,
};
static void sp804_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
sdc->init = sp804_init;
}
static DeviceInfo sp804_info = {
.name = "sp804",
.size = sizeof(sp804_state),
.class_init = sp804_class_init,
.props = (Property[]) {
DEFINE_PROP_UINT32("freq0", sp804_state, freq0, 1000000),
DEFINE_PROP_UINT32("freq1", sp804_state, freq1, 1000000),
DEFINE_PROP_END_OF_LIST(),
}
};
static void arm_timer_register_devices(void)
{
sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
sysbus_register_withprop(&sp804_info);
sysbus_qdev_register(&icp_pit_info);
sysbus_qdev_register(&sp804_info);
}
device_init(arm_timer_register_devices)
hw/armv7m.c
+17 -8
View File
@@ -245,14 +245,23 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
return pic;
}
static SysBusDeviceInfo bitband_info = {
.init = bitband_init,
.qdev.name = "ARM,bitband-memory",
.qdev.size = sizeof(BitBandState),
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("base", BitBandState, base, 0),
DEFINE_PROP_END_OF_LIST(),
}
static Property bitband_properties[] = {
DEFINE_PROP_UINT32("base", BitBandState, base, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void bitband_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = bitband_init;
}
static DeviceInfo bitband_info = {
.name = "ARM,bitband-memory",
.size = sizeof(BitBandState),
.props = bitband_properties,
.class_init = bitband_class_init,
};
static void armv7m_register_devices(void)
hw/armv7m_nvic.c
+14 -7
View File
@@ -391,12 +391,19 @@ static int armv7m_nvic_init(SysBusDevice *dev)
return 0;
}
static SysBusDeviceInfo armv7m_nvic_priv_info = {
.init = armv7m_nvic_init,
.qdev.name = "armv7m_nvic",
.qdev.size = sizeof(nvic_state),
.qdev.vmsd = &vmstate_nvic,
.qdev.props = (Property[]) {
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
sdc->init = armv7m_nvic_init;
}
static DeviceInfo armv7m_nvic_priv_info = {
.name = "armv7m_nvic",
.size = sizeof(nvic_state),
.vmsd = &vmstate_nvic,
.class_init = armv7m_nvic_class_init,
.props = (Property[]) {
/* The ARM v7m may have anything from 0 to 496 external interrupt
* IRQ lines. We default to 64. Other boards may differ and should
* set this property appropriately.
@@ -408,7 +415,7 @@ static SysBusDeviceInfo armv7m_nvic_priv_info = {
static void armv7m_nvic_register_devices(void)
{
sysbus_register_withprop(&armv7m_nvic_priv_info);
sysbus_qdev_register(&armv7m_nvic_priv_info);
}
device_init(armv7m_nvic_register_devices)
hw/bitbang_i2c.c
+12 -5
View File
@@ -221,11 +221,18 @@ static int gpio_i2c_init(SysBusDevice *dev)
return 0;
}
static SysBusDeviceInfo gpio_i2c_info = {
.init = gpio_i2c_init,
.qdev.name = "gpio_i2c",
.qdev.desc = "Virtual GPIO to I2C bridge",
.qdev.size = sizeof(GPIOI2CState),
static void gpio_i2c_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = gpio_i2c_init;
}
static DeviceInfo gpio_i2c_info = {
.name = "gpio_i2c",
.desc = "Virtual GPIO to I2C bridge",
.size = sizeof(GPIOI2CState),
.class_init = gpio_i2c_class_init,
};
static void bitbang_i2c_register(void)
hw/bonito.c
+12 -5
View File
@@ -786,11 +786,18 @@ static DeviceInfo bonito_info = {
.class_init = bonito_class_init,
};
static SysBusDeviceInfo bonito_pcihost_info = {
.init = bonito_pcihost_initfn,
.qdev.name = "Bonito-pcihost",
.qdev.size = sizeof(BonitoState),
.qdev.no_user = 1,
static void bonito_pcihost_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = bonito_pcihost_initfn;
}
static DeviceInfo bonito_pcihost_info = {
.name = "Bonito-pcihost",
.size = sizeof(BonitoState),
.no_user = 1,
.class_init = bonito_pcihost_class_init,
};
static void bonito_register(void)
hw/container.c
+12 -5
View File
@@ -5,11 +5,18 @@ static int container_initfn(SysBusDevice *dev)
return 0;
}
static SysBusDeviceInfo container_info = {
.init = container_initfn,
.qdev.name = "container",
.qdev.size = sizeof(SysBusDevice),
.qdev.no_user = 1,
static void container_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = container_initfn;
}
static DeviceInfo container_info = {
.name = "container",
.size = sizeof(SysBusDevice),
.no_user = 1,
.class_init = container_class_init,
};
static void container_init(void)
hw/cs4231.c
+18 -9
View File
@@ -151,15 +151,24 @@ static int cs4231_init1(SysBusDevice *dev)
return 0;
}
static SysBusDeviceInfo cs4231_info = {
.init = cs4231_init1,
.qdev.name = "SUNW,CS4231",
.qdev.size = sizeof(CSState),
.qdev.vmsd = &vmstate_cs4231,
.qdev.reset = cs_reset,
.qdev.props = (Property[]) {
{.name = NULL}
}
static Property cs4231_properties[] = {
{.name = NULL},
};
static void cs4231_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = cs4231_init1;
}
static DeviceInfo cs4231_info = {
.name = "SUNW,CS4231",
.size = sizeof(CSState),
.vmsd = &vmstate_cs4231,
.reset = cs_reset,
.props = cs4231_properties,
.class_init = cs4231_class_init,
};
static void cs4231_register_devices(void)
hw/dec_pci.c
+15 -4
View File
@@ -84,7 +84,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
return pci_bridge_get_sec_bus(br);
}
static int pci_dec_21154_init_device(SysBusDevice *dev)
static int pci_dec_21154_device_init(SysBusDevice *dev)
{
DECState *s;
@@ -123,11 +123,22 @@ static DeviceInfo dec_21154_pci_host_info = {
.class_init = dec_21154_pci_host_class_init,
};
static void pci_dec_21154_device_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
sdc->init = pci_dec_21154_device_init;
}
static DeviceInfo pci_dec_21154_device_info = {
.name = "dec-21154",
.size = sizeof(DECState),
.class_init = pci_dec_21154_device_class_init,
};
static void dec_register_devices(void)
{
sysbus_register_dev("dec-21154", sizeof(DECState),
pci_dec_21154_init_device);
sysbus_qdev_register(&pci_dec_21154_device_info);
pci_qdev_register(&dec_21154_pci_host_info);
pci_qdev_register(&dec_21154_pci_bridge_info);
}
hw/ds1225y.c
+19 -10
View File
@@ -134,16 +134,25 @@ static int nvram_sysbus_initfn(SysBusDevice *dev)
return 0;
}
static SysBusDeviceInfo nvram_sysbus_info = {
.qdev.name = "ds1225y",
.qdev.size = sizeof(SysBusNvRamState),
.qdev.vmsd = &vmstate_nvram,
.init = nvram_sysbus_initfn,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
DEFINE_PROP_END_OF_LIST(),
},
static Property nvram_sysbus_properties[] = {
DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
DEFINE_PROP_END_OF_LIST(),
};
static void nvram_sysbus_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = nvram_sysbus_initfn;
}
static DeviceInfo nvram_sysbus_info = {
.name = "ds1225y",
.size = sizeof(SysBusNvRamState),
.vmsd = &vmstate_nvram,
.props = nvram_sysbus_properties,
.class_init = nvram_sysbus_class_init,
};
static void nvram_register(void)
hw/eccmemctl.c
+19 -10
View File
@@ -308,16 +308,25 @@ static int ecc_init1(SysBusDevice *dev)
return 0;
}
static SysBusDeviceInfo ecc_info = {
.init = ecc_init1,
.qdev.name = "eccmemctl",
.qdev.size = sizeof(ECCState),
.qdev.vmsd = &vmstate_ecc,
.qdev.reset = ecc_reset,
.qdev.props = (Property[]) {
DEFINE_PROP_HEX32("version", ECCState, version, -1),
DEFINE_PROP_END_OF_LIST(),
}
static Property ecc_properties[] = {
DEFINE_PROP_HEX32("version", ECCState, version, -1),
DEFINE_PROP_END_OF_LIST(),
};
static void ecc_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = ecc_init1;
}
static DeviceInfo ecc_info = {
.name = "eccmemctl",
.size = sizeof(ECCState),
.vmsd = &vmstate_ecc,
.reset = ecc_reset,
.props = ecc_properties,
.class_init = ecc_class_init,
};

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