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target/arm: Implement CTZ, CNT, ABS

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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250803014019.416797-6-richard.henderson@linaro.org
[PMM: fix tcg_rd/tcg_rn mixup]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2025-08-30 16:37:22 +01:00
parent 8a4bb8b975
commit 994a260fea
2 changed files with 35 additions and 0 deletions
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target/arm/tcg/a64.decode
+4
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@@ -726,6 +726,10 @@ REV64 1 10 11010110 00000 000011 ..... ..... @rr
CLZ . 10 11010110 00000 000100 ..... ..... @rr_sf
CLS . 10 11010110 00000 000101 ..... ..... @rr_sf
CTZ . 10 11010110 00000 000110 ..... ..... @rr_sf
CNT . 10 11010110 00000 000111 ..... ..... @rr_sf
ABS . 10 11010110 00000 001000 ..... ..... @rr_sf
&pacaut rd rn z
@pacaut . .. ........ ..... .. z:1 ... rn:5 rd:5 &pacaut
target/arm/tcg/translate-a64.c
+31
View File
@@ -8308,6 +8308,37 @@ static void gen_cls32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
TRANS(CLZ, gen_rr, a->rd, a->rn, a->sf ? gen_clz64 : gen_clz32)
TRANS(CLS, gen_rr, a->rd, a->rn, a->sf ? tcg_gen_clrsb_i64 : gen_cls32)
static void gen_ctz32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
TCGv_i32 t32 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t32, tcg_rn);
tcg_gen_ctzi_i32(t32, t32, 32);
tcg_gen_extu_i32_i64(tcg_rd, t32);
}
static void gen_ctz64(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
tcg_gen_ctzi_i64(tcg_rd, tcg_rn, 64);
}
static void gen_cnt32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
gen_wrap2_i32(tcg_rd, tcg_rn, tcg_gen_ctpop_i32);
}
static void gen_abs32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
gen_wrap2_i32(tcg_rd, tcg_rn, tcg_gen_abs_i32);
}
TRANS_FEAT(CTZ, aa64_cssc, gen_rr, a->rd, a->rn,
a->sf ? gen_ctz64 : gen_ctz32)
TRANS_FEAT(CNT, aa64_cssc, gen_rr, a->rd, a->rn,
a->sf ? tcg_gen_ctpop_i64 : gen_cnt32)
TRANS_FEAT(ABS, aa64_cssc, gen_rr, a->rd, a->rn,
a->sf ? tcg_gen_abs_i64 : gen_abs32)
static bool gen_pacaut(DisasContext *s, arg_pacaut *a, NeonGenTwo64OpEnvFn fn)
{
TCGv_i64 tcg_rd, tcg_rn;