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hw/rdma: PVRDMA commands and data-path ops
First PVRDMA sub-module - implementation of the PVRDMA device. - PVRDMA commands such as create CQ and create MR. - Data path QP operations - post_send and post_recv. - Completion handler. Reviewed-by: Dotan Barak <dotanb@mellanox.com> Reviewed-by: Zhu Yanjun <yanjun.zhu@oracle.com> Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
This commit is contained in:
Yuval Shaia
committed by
Marcel Apfelbaum
Marcel Apfelbaum
parent
ef6d4ccdc9
commit
98d176f8e5
@@ -1,3 +1,5 @@
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ifeq ($(CONFIG_RDMA),y)
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obj-$(CONFIG_PCI) += rdma_utils.o rdma_backend.o rdma_rm.o
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obj-$(CONFIG_PCI) += vmw/pvrdma_dev_ring.o vmw/pvrdma_cmd.o \
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vmw/pvrdma_qp_ops.o
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endif
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@@ -0,0 +1,122 @@
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/*
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* QEMU VMWARE paravirtual RDMA device definitions
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*
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* Copyright (C) 2018 Oracle
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* Copyright (C) 2018 Red Hat Inc
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*
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* Authors:
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* Yuval Shaia <yuval.shaia@oracle.com>
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef PVRDMA_PVRDMA_H
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#define PVRDMA_PVRDMA_H
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#include <hw/pci/pci.h>
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#include <hw/pci/msix.h>
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#include "../rdma_backend_defs.h"
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#include "../rdma_rm_defs.h"
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#include <standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_ring.h>
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#include <standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h>
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#include "pvrdma_dev_ring.h"
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/* BARs */
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#define RDMA_MSIX_BAR_IDX 0
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#define RDMA_REG_BAR_IDX 1
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#define RDMA_UAR_BAR_IDX 2
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#define RDMA_BAR0_MSIX_SIZE (16 * 1024)
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#define RDMA_BAR1_REGS_SIZE 256
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#define RDMA_BAR2_UAR_SIZE (0x1000 * MAX_UCS) /* each uc gets page */
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/* MSIX */
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#define RDMA_MAX_INTRS 3
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#define RDMA_MSIX_TABLE 0x0000
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#define RDMA_MSIX_PBA 0x2000
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/* Interrupts Vectors */
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#define INTR_VEC_CMD_RING 0
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#define INTR_VEC_CMD_ASYNC_EVENTS 1
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#define INTR_VEC_CMD_COMPLETION_Q 2
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/* HW attributes */
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#define PVRDMA_HW_NAME "pvrdma"
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#define PVRDMA_HW_VERSION 17
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#define PVRDMA_FW_VERSION 14
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typedef struct DSRInfo {
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dma_addr_t dma;
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struct pvrdma_device_shared_region *dsr;
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union pvrdma_cmd_req *req;
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union pvrdma_cmd_resp *rsp;
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struct pvrdma_ring *async_ring_state;
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PvrdmaRing async;
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struct pvrdma_ring *cq_ring_state;
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PvrdmaRing cq;
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} DSRInfo;
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typedef struct PVRDMADev {
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PCIDevice parent_obj;
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MemoryRegion msix;
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MemoryRegion regs;
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uint32_t regs_data[RDMA_BAR1_REGS_SIZE];
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MemoryRegion uar;
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uint32_t uar_data[RDMA_BAR2_UAR_SIZE];
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DSRInfo dsr_info;
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int interrupt_mask;
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struct ibv_device_attr dev_attr;
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uint64_t node_guid;
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char *backend_device_name;
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uint8_t backend_gid_idx;
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uint8_t backend_port_num;
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RdmaBackendDev backend_dev;
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RdmaDeviceResources rdma_dev_res;
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} PVRDMADev;
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#define PVRDMA_DEV(dev) OBJECT_CHECK(PVRDMADev, (dev), PVRDMA_HW_NAME)
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static inline int get_reg_val(PVRDMADev *dev, hwaddr addr, uint32_t *val)
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{
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int idx = addr >> 2;
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if (idx > RDMA_BAR1_REGS_SIZE) {
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return -EINVAL;
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}
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*val = dev->regs_data[idx];
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return 0;
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}
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static inline int set_reg_val(PVRDMADev *dev, hwaddr addr, uint32_t val)
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{
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int idx = addr >> 2;
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if (idx > RDMA_BAR1_REGS_SIZE) {
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return -EINVAL;
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}
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dev->regs_data[idx] = val;
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return 0;
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}
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static inline void post_interrupt(PVRDMADev *dev, unsigned vector)
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{
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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if (likely(!dev->interrupt_mask)) {
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msix_notify(pci_dev, vector);
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}
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}
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int execute_command(PVRDMADev *dev);
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#endif
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,155 @@
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/*
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* QEMU paravirtual RDMA - Device rings
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*
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* Copyright (C) 2018 Oracle
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* Copyright (C) 2018 Red Hat Inc
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*
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* Authors:
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* Yuval Shaia <yuval.shaia@oracle.com>
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <qemu/osdep.h>
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#include <hw/pci/pci.h>
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#include <cpu.h>
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#include "../rdma_utils.h"
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#include <standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_ring.h>
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#include "pvrdma_dev_ring.h"
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int pvrdma_ring_init(PvrdmaRing *ring, const char *name, PCIDevice *dev,
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struct pvrdma_ring *ring_state, uint32_t max_elems,
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size_t elem_sz, dma_addr_t *tbl, dma_addr_t npages)
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{
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int i;
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int rc = 0;
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strncpy(ring->name, name, MAX_RING_NAME_SZ);
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ring->name[MAX_RING_NAME_SZ - 1] = 0;
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pr_dbg("Initializing %s ring\n", ring->name);
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ring->dev = dev;
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ring->ring_state = ring_state;
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ring->max_elems = max_elems;
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ring->elem_sz = elem_sz;
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pr_dbg("ring->elem_sz=%ld\n", ring->elem_sz);
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pr_dbg("npages=%ld\n", npages);
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/* TODO: Give a moment to think if we want to redo driver settings
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atomic_set(&ring->ring_state->prod_tail, 0);
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atomic_set(&ring->ring_state->cons_head, 0);
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*/
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ring->npages = npages;
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ring->pages = g_malloc(npages * sizeof(void *));
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for (i = 0; i < npages; i++) {
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if (!tbl[i]) {
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pr_err("npages=%ld but tbl[%d] is NULL\n", (long)npages, i);
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continue;
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}
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ring->pages[i] = rdma_pci_dma_map(dev, tbl[i], TARGET_PAGE_SIZE);
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if (!ring->pages[i]) {
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rc = -ENOMEM;
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pr_dbg("Failed to map to page %d\n", i);
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goto out_free;
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}
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memset(ring->pages[i], 0, TARGET_PAGE_SIZE);
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}
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goto out;
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out_free:
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while (i--) {
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rdma_pci_dma_unmap(dev, ring->pages[i], TARGET_PAGE_SIZE);
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}
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g_free(ring->pages);
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out:
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return rc;
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}
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void *pvrdma_ring_next_elem_read(PvrdmaRing *ring)
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{
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unsigned int idx = 0, offset;
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/*
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pr_dbg("%s: t=%d, h=%d\n", ring->name, ring->ring_state->prod_tail,
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ring->ring_state->cons_head);
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*/
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if (!pvrdma_idx_ring_has_data(ring->ring_state, ring->max_elems, &idx)) {
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pr_dbg("No more data in ring\n");
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return NULL;
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}
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offset = idx * ring->elem_sz;
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/*
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pr_dbg("idx=%d\n", idx);
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pr_dbg("offset=%d\n", offset);
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*/
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return ring->pages[offset / TARGET_PAGE_SIZE] + (offset % TARGET_PAGE_SIZE);
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}
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void pvrdma_ring_read_inc(PvrdmaRing *ring)
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{
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pvrdma_idx_ring_inc(&ring->ring_state->cons_head, ring->max_elems);
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/*
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pr_dbg("%s: t=%d, h=%d, m=%ld\n", ring->name,
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ring->ring_state->prod_tail, ring->ring_state->cons_head,
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ring->max_elems);
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*/
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}
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void *pvrdma_ring_next_elem_write(PvrdmaRing *ring)
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{
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unsigned int idx, offset, tail;
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/*
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pr_dbg("%s: t=%d, h=%d\n", ring->name, ring->ring_state->prod_tail,
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ring->ring_state->cons_head);
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*/
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if (!pvrdma_idx_ring_has_space(ring->ring_state, ring->max_elems, &tail)) {
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pr_dbg("CQ is full\n");
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return NULL;
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}
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idx = pvrdma_idx(&ring->ring_state->prod_tail, ring->max_elems);
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/* TODO: tail == idx */
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offset = idx * ring->elem_sz;
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return ring->pages[offset / TARGET_PAGE_SIZE] + (offset % TARGET_PAGE_SIZE);
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}
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void pvrdma_ring_write_inc(PvrdmaRing *ring)
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{
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pvrdma_idx_ring_inc(&ring->ring_state->prod_tail, ring->max_elems);
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/*
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pr_dbg("%s: t=%d, h=%d, m=%ld\n", ring->name,
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ring->ring_state->prod_tail, ring->ring_state->cons_head,
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ring->max_elems);
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*/
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}
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void pvrdma_ring_free(PvrdmaRing *ring)
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{
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if (!ring) {
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return;
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}
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if (!ring->pages) {
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return;
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}
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pr_dbg("ring->npages=%d\n", ring->npages);
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while (ring->npages--) {
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rdma_pci_dma_unmap(ring->dev, ring->pages[ring->npages],
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TARGET_PAGE_SIZE);
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}
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g_free(ring->pages);
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ring->pages = NULL;
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}
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@@ -0,0 +1,42 @@
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/*
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* QEMU VMWARE paravirtual RDMA ring utilities
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*
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* Copyright (C) 2018 Oracle
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* Copyright (C) 2018 Red Hat Inc
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*
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* Authors:
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* Yuval Shaia <yuval.shaia@oracle.com>
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef PVRDMA_DEV_RING_H
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#define PVRDMA_DEV_RING_H
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#include <qemu/typedefs.h>
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#define MAX_RING_NAME_SZ 32
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typedef struct PvrdmaRing {
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char name[MAX_RING_NAME_SZ];
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PCIDevice *dev;
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uint32_t max_elems;
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size_t elem_sz;
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struct pvrdma_ring *ring_state; /* used only for unmap */
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int npages;
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void **pages;
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} PvrdmaRing;
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int pvrdma_ring_init(PvrdmaRing *ring, const char *name, PCIDevice *dev,
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struct pvrdma_ring *ring_state, uint32_t max_elems,
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size_t elem_sz, dma_addr_t *tbl, dma_addr_t npages);
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void *pvrdma_ring_next_elem_read(PvrdmaRing *ring);
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void pvrdma_ring_read_inc(PvrdmaRing *ring);
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void *pvrdma_ring_next_elem_write(PvrdmaRing *ring);
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void pvrdma_ring_write_inc(PvrdmaRing *ring);
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void pvrdma_ring_free(PvrdmaRing *ring);
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#endif
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@@ -0,0 +1,222 @@
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/*
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* QEMU paravirtual RDMA - QP implementation
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*
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* Copyright (C) 2018 Oracle
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* Copyright (C) 2018 Red Hat Inc
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*
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* Authors:
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* Yuval Shaia <yuval.shaia@oracle.com>
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <qemu/osdep.h>
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#include "../rdma_utils.h"
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#include "../rdma_rm.h"
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#include "../rdma_backend.h"
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#include "pvrdma.h"
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#include <standard-headers/rdma/vmw_pvrdma-abi.h>
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#include "pvrdma_qp_ops.h"
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typedef struct CompHandlerCtx {
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PVRDMADev *dev;
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uint32_t cq_handle;
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struct pvrdma_cqe cqe;
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} CompHandlerCtx;
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/* Send Queue WQE */
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typedef struct PvrdmaSqWqe {
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struct pvrdma_sq_wqe_hdr hdr;
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struct pvrdma_sge sge[0];
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} PvrdmaSqWqe;
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/* Recv Queue WQE */
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typedef struct PvrdmaRqWqe {
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struct pvrdma_rq_wqe_hdr hdr;
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struct pvrdma_sge sge[0];
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} PvrdmaRqWqe;
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/*
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* 1. Put CQE on send CQ ring
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* 2. Put CQ number on dsr completion ring
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* 3. Interrupt host
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*/
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static int pvrdma_post_cqe(PVRDMADev *dev, uint32_t cq_handle,
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struct pvrdma_cqe *cqe)
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{
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struct pvrdma_cqe *cqe1;
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struct pvrdma_cqne *cqne;
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PvrdmaRing *ring;
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RdmaRmCQ *cq = rdma_rm_get_cq(&dev->rdma_dev_res, cq_handle);
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if (unlikely(!cq)) {
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pr_dbg("Invalid cqn %d\n", cq_handle);
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return -EINVAL;
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}
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ring = (PvrdmaRing *)cq->opaque;
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pr_dbg("ring=%p\n", ring);
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/* Step #1: Put CQE on CQ ring */
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pr_dbg("Writing CQE\n");
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cqe1 = pvrdma_ring_next_elem_write(ring);
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if (unlikely(!cqe1)) {
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return -EINVAL;
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}
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cqe1->wr_id = cqe->wr_id;
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cqe1->qp = cqe->qp;
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cqe1->opcode = cqe->opcode;
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cqe1->status = cqe->status;
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cqe1->vendor_err = cqe->vendor_err;
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pvrdma_ring_write_inc(ring);
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/* Step #2: Put CQ number on dsr completion ring */
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pr_dbg("Writing CQNE\n");
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cqne = pvrdma_ring_next_elem_write(&dev->dsr_info.cq);
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if (unlikely(!cqne)) {
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return -EINVAL;
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}
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cqne->info = cq_handle;
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pvrdma_ring_write_inc(&dev->dsr_info.cq);
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pr_dbg("cq->notify=%d\n", cq->notify);
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if (cq->notify) {
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cq->notify = false;
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post_interrupt(dev, INTR_VEC_CMD_COMPLETION_Q);
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}
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return 0;
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}
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static void pvrdma_qp_ops_comp_handler(int status, unsigned int vendor_err,
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void *ctx)
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{
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CompHandlerCtx *comp_ctx = (CompHandlerCtx *)ctx;
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pr_dbg("cq_handle=%d\n", comp_ctx->cq_handle);
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pr_dbg("wr_id=%ld\n", comp_ctx->cqe.wr_id);
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pr_dbg("status=%d\n", status);
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pr_dbg("vendor_err=0x%x\n", vendor_err);
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comp_ctx->cqe.status = status;
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comp_ctx->cqe.vendor_err = vendor_err;
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pvrdma_post_cqe(comp_ctx->dev, comp_ctx->cq_handle, &comp_ctx->cqe);
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g_free(ctx);
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}
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void pvrdma_qp_ops_fini(void)
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{
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rdma_backend_unregister_comp_handler();
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}
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int pvrdma_qp_ops_init(void)
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{
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rdma_backend_register_comp_handler(pvrdma_qp_ops_comp_handler);
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return 0;
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}
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|
||||
int pvrdma_qp_send(PVRDMADev *dev, uint32_t qp_handle)
|
||||
{
|
||||
RdmaRmQP *qp;
|
||||
PvrdmaSqWqe *wqe;
|
||||
PvrdmaRing *ring;
|
||||
|
||||
pr_dbg("qp_handle=%d\n", qp_handle);
|
||||
|
||||
qp = rdma_rm_get_qp(&dev->rdma_dev_res, qp_handle);
|
||||
if (unlikely(!qp)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ring = (PvrdmaRing *)qp->opaque;
|
||||
pr_dbg("sring=%p\n", ring);
|
||||
|
||||
wqe = (struct PvrdmaSqWqe *)pvrdma_ring_next_elem_read(ring);
|
||||
while (wqe) {
|
||||
CompHandlerCtx *comp_ctx;
|
||||
|
||||
pr_dbg("wr_id=%ld\n", wqe->hdr.wr_id);
|
||||
|
||||
/* Prepare CQE */
|
||||
comp_ctx = g_malloc(sizeof(CompHandlerCtx));
|
||||
comp_ctx->dev = dev;
|
||||
comp_ctx->cq_handle = qp->send_cq_handle;
|
||||
comp_ctx->cqe.wr_id = wqe->hdr.wr_id;
|
||||
comp_ctx->cqe.qp = qp_handle;
|
||||
comp_ctx->cqe.opcode = wqe->hdr.opcode;
|
||||
|
||||
rdma_backend_post_send(&dev->backend_dev, &qp->backend_qp, qp->qp_type,
|
||||
(struct ibv_sge *)&wqe->sge[0], wqe->hdr.num_sge,
|
||||
(union ibv_gid *)wqe->hdr.wr.ud.av.dgid,
|
||||
wqe->hdr.wr.ud.remote_qpn,
|
||||
wqe->hdr.wr.ud.remote_qkey, comp_ctx);
|
||||
|
||||
pvrdma_ring_read_inc(ring);
|
||||
|
||||
wqe = pvrdma_ring_next_elem_read(ring);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pvrdma_qp_recv(PVRDMADev *dev, uint32_t qp_handle)
|
||||
{
|
||||
RdmaRmQP *qp;
|
||||
PvrdmaRqWqe *wqe;
|
||||
PvrdmaRing *ring;
|
||||
|
||||
pr_dbg("qp_handle=%d\n", qp_handle);
|
||||
|
||||
qp = rdma_rm_get_qp(&dev->rdma_dev_res, qp_handle);
|
||||
if (unlikely(!qp)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ring = &((PvrdmaRing *)qp->opaque)[1];
|
||||
pr_dbg("rring=%p\n", ring);
|
||||
|
||||
wqe = (struct PvrdmaRqWqe *)pvrdma_ring_next_elem_read(ring);
|
||||
while (wqe) {
|
||||
CompHandlerCtx *comp_ctx;
|
||||
|
||||
pr_dbg("wr_id=%ld\n", wqe->hdr.wr_id);
|
||||
|
||||
/* Prepare CQE */
|
||||
comp_ctx = g_malloc(sizeof(CompHandlerCtx));
|
||||
comp_ctx->dev = dev;
|
||||
comp_ctx->cq_handle = qp->recv_cq_handle;
|
||||
comp_ctx->cqe.qp = qp_handle;
|
||||
comp_ctx->cqe.wr_id = wqe->hdr.wr_id;
|
||||
|
||||
rdma_backend_post_recv(&dev->backend_dev, &dev->rdma_dev_res,
|
||||
&qp->backend_qp, qp->qp_type,
|
||||
(struct ibv_sge *)&wqe->sge[0], wqe->hdr.num_sge,
|
||||
comp_ctx);
|
||||
|
||||
pvrdma_ring_read_inc(ring);
|
||||
|
||||
wqe = pvrdma_ring_next_elem_read(ring);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pvrdma_cq_poll(RdmaDeviceResources *dev_res, uint32_t cq_handle)
|
||||
{
|
||||
RdmaRmCQ *cq;
|
||||
|
||||
cq = rdma_rm_get_cq(dev_res, cq_handle);
|
||||
if (!cq) {
|
||||
pr_dbg("Invalid CQ# %d\n", cq_handle);
|
||||
}
|
||||
|
||||
rdma_backend_poll_cq(dev_res, &cq->backend_cq);
|
||||
}
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* QEMU VMWARE paravirtual RDMA QP Operations
|
||||
*
|
||||
* Copyright (C) 2018 Oracle
|
||||
* Copyright (C) 2018 Red Hat Inc
|
||||
*
|
||||
* Authors:
|
||||
* Yuval Shaia <yuval.shaia@oracle.com>
|
||||
* Marcel Apfelbaum <marcel@redhat.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PVRDMA_QP_H
|
||||
#define PVRDMA_QP_H
|
||||
|
||||
#include "pvrdma.h"
|
||||
|
||||
int pvrdma_qp_ops_init(void);
|
||||
void pvrdma_qp_ops_fini(void);
|
||||
int pvrdma_qp_send(PVRDMADev *dev, uint32_t qp_handle);
|
||||
int pvrdma_qp_recv(PVRDMADev *dev, uint32_t qp_handle);
|
||||
void pvrdma_cq_poll(RdmaDeviceResources *dev_res, uint32_t cq_handle);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user